Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757957
Frank K. H. Kao, A. Verhulst, W. Vandenberghe, G. Groeseneken, K. De Meyer
We derive an analytical model based on circular tunnel paths along the electric field to describe the behavior of a tunnel FET with a junction angle at the source. The model is compared with simulation results and qualitative agreement is observed. We further demonstrate that a small junction angle prevents TFET performance degradation resulting from a high-k spacer. Finally we optimize the junction angle with an encroaching source structure, studying the dependence on oxide thickness and semiconductor material.
{"title":"The impact of junction angle on tunnel FETs","authors":"Frank K. H. Kao, A. Verhulst, W. Vandenberghe, G. Groeseneken, K. De Meyer","doi":"10.1109/ULIS.2011.5757957","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757957","url":null,"abstract":"We derive an analytical model based on circular tunnel paths along the electric field to describe the behavior of a tunnel FET with a junction angle at the source. The model is compared with simulation results and qualitative agreement is observed. We further demonstrate that a small junction angle prevents TFET performance degradation resulting from a high-k spacer. Finally we optimize the junction angle with an encroaching source structure, studying the dependence on oxide thickness and semiconductor material.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757998
D. Osintsev, V. Sverdlov, Z. Stanojević, A. Makarov, S. Selberherr
We investigate the properties of ballistic spin field-effect transistors (SpinFETs). First we show that the amplitude of the tunneling magnetoresistance oscillations decreases dramatically with increasing temperature in SpinFETs with the semiconductor channel made of InAs. We also demonstrate that the [100] orientation of the silicon fin is preferred for practical realizations of silicon SpinFETs due to stronger modulation of the conductance as a function of spin-orbit interaction and magnetic field.
{"title":"Transport properties of spin field-effect transistors built on Si and InAs","authors":"D. Osintsev, V. Sverdlov, Z. Stanojević, A. Makarov, S. Selberherr","doi":"10.1109/ULIS.2011.5757998","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757998","url":null,"abstract":"We investigate the properties of ballistic spin field-effect transistors (SpinFETs). First we show that the amplitude of the tunneling magnetoresistance oscillations decreases dramatically with increasing temperature in SpinFETs with the semiconductor channel made of InAs. We also demonstrate that the [100] orientation of the silicon fin is preferred for practical realizations of silicon SpinFETs due to stronger modulation of the conductance as a function of spin-orbit interaction and magnetic field.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758013
V. Kilchytska, F. Andrieu, O. Faynot, D. Flandre
In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultra-thin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses as well as channel doping on the degradation of main device parameters over the temperature range.
在本文中，我们首次分析了超薄体(UTB) SOI mosfet的高温视角。通过测量和二维仿真，详细分析了阈值电压、亚阈值斜率、跨导最大值和导通电流的高温行为。特别关注了埋藏氧化物(BOX)和硅膜厚度以及通道掺杂对主要器件参数在温度范围内退化的影响。
{"title":"High-temperature perspectives of UTB SOI MOSFETs","authors":"V. Kilchytska, F. Andrieu, O. Faynot, D. Flandre","doi":"10.1109/ULIS.2011.5758013","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758013","url":null,"abstract":"In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultra-thin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses as well as channel doping on the degradation of main device parameters over the temperature range.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132007470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757960
M. Kalisz, R. Mroczyński, R. B. Beck
In this study, the comparison of methods of improving electro-physical properties of silicon dioxide (SiO2) by means of silicon substrates fluorination in CF4 in PECVD and RIE reactors, prior to oxide deposition, has been performed. The results proved that, in general, fluorination in RIE is superior to the fluorination in PECVD reactor. The observed effects have been referred to the obtained changes in the electrical properties, resulting from both fluorination methods. As a result of this study, it has been proved, that properties change is fluorine concentration dependent.
{"title":"Specific features of fluorination of silicon surface region by RIE in r.f. CF4 plasma — novel method of improving electrical properties of thin PECVD silicon dioxide films","authors":"M. Kalisz, R. Mroczyński, R. B. Beck","doi":"10.1109/ULIS.2011.5757960","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757960","url":null,"abstract":"In this study, the comparison of methods of improving electro-physical properties of silicon dioxide (SiO2) by means of silicon substrates fluorination in CF4 in PECVD and RIE reactors, prior to oxide deposition, has been performed. The results proved that, in general, fluorination in RIE is superior to the fluorination in PECVD reactor. The observed effects have been referred to the obtained changes in the electrical properties, resulting from both fluorination methods. As a result of this study, it has been proved, that properties change is fluorine concentration dependent.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"109 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130675743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757997
A. Kranti, J. Raskin, G. A. Armstrong
We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (gm/Ids) and cut-off frequency (fT) product i.e. gmfT/Ids as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve gmfT/Ids, intrinsic voltage gain (AVO), cut-off frequency (fT) and linearity (VIP3) with downscaling.
{"title":"Source/drain engineered ultra low power analog/RF UTBB MOSFETs","authors":"A. Kranti, J. Raskin, G. A. Armstrong","doi":"10.1109/ULIS.2011.5757997","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757997","url":null,"abstract":"We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (g<inf>m</inf>/I<inf>ds</inf>) and cut-off frequency (f<inf>T</inf>) product i.e. g<inf>m</inf>f<inf>T</inf>/I<inf>ds</inf> as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve g<inf>m</inf>f<inf>T</inf>/I<inf>ds</inf>, intrinsic voltage gain (A<inf>VO</inf>), cut-off frequency (f<inf>T</inf>) and linearity (VIP<inf>3</inf>) with downscaling.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130208163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758005
P. Razavi, G. Fagas, I. Ferain, N. Akhavan, R. Yu, J. Colinge
We investigate the performance of short channel junctionless gate-all-around (GAA) transistors, by comparing the I_V characteristics, subthreshold swing and drain-induced barrier lowring (DIBL) of junctionless GAA transistors with accumulation-mode GAA transistors. We also compare the I_V characteristics of junctionless GAA transistors for different wafer and transport orientations. MuGFETs are investigated for different wafer and channel orientation.
{"title":"Performance investigation of short-channel junctionless multigate transistors","authors":"P. Razavi, G. Fagas, I. Ferain, N. Akhavan, R. Yu, J. Colinge","doi":"10.1109/ULIS.2011.5758005","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758005","url":null,"abstract":"We investigate the performance of short channel junctionless gate-all-around (GAA) transistors, by comparing the I_V characteristics, subthreshold swing and drain-induced barrier lowring (DIBL) of junctionless GAA transistors with accumulation-mode GAA transistors. We also compare the I_V characteristics of junctionless GAA transistors for different wafer and transport orientations. MuGFETs are investigated for different wafer and channel orientation.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129510558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757992
N. Manavizadeh, F. Raissi, E. Soleimani
The performance of nanoscale Field Effect Diode as a function of doping concentration is investigated. Our numerical results show that the Ion/Ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 as the doping concentration of source/drain regions increased from 1016 to 1021 cm−3. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic application.
{"title":"The effect of the doping concentration on nanoscale field effect diode performance","authors":"N. Manavizadeh, F. Raissi, E. Soleimani","doi":"10.1109/ULIS.2011.5757992","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757992","url":null,"abstract":"The performance of nanoscale Field Effect Diode as a function of doping concentration is investigated. Our numerical results show that the I<inf>on</inf>/I<inf>off</inf> ratio which is a significant parameter in digital application can be varied from 10<sup>1</sup> to 10<sup>4</sup> as the doping concentration of source/drain regions increased from 10<sup>16</sup> to 10<sup>21</sup> cm<sup>−3</sup>. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic application.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123042824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757961
R. De Rose, M. Zanuccoli, P. Magnone, E. Sangiorgi, C. Fiegna
The improvement of solar cell efficiency requires device optimization, including the careful design of contacts and doping profiles, and the implementation of light trapping strategies. In this context, electro-optical numerical simulation is essential to analyze the physical mechanisms that limit the cell efficiency and lead to design trade-offs. In this work we discuss the calibration of the relevant physical models for electrical simulation and we put in evidence important limitations of the most common adopted optical simulators.
{"title":"Open issues for the numerical simulation of silicon solar cells","authors":"R. De Rose, M. Zanuccoli, P. Magnone, E. Sangiorgi, C. Fiegna","doi":"10.1109/ULIS.2011.5757961","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757961","url":null,"abstract":"The improvement of solar cell efficiency requires device optimization, including the careful design of contacts and doping profiles, and the implementation of light trapping strategies. In this context, electro-optical numerical simulation is essential to analyze the physical mechanisms that limit the cell efficiency and lead to design trade-offs. In this work we discuss the calibration of the relevant physical models for electrical simulation and we put in evidence important limitations of the most common adopted optical simulators.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128451170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757955
M. Clavel, T. Poiroux, M. Mouis, L. Becerra, J. Thomassin, A. Zenasni, G. Lapertot, D. Rouchon, D. Lafond, O. Faynot
In this study, we investigate the impact of thermal annealing on the electrical characteristics of epitaxial graphene field effect transistors. Top gated devices were fabricated from graphene obtained on silicon carbide (SiC) substrate. Thanks to an annealing at 300°C, the performance of the devices was enhanced by a factor of 90. The maximal transconductance reached really high values such as 5900µS/µm at VD=3V, corresponding to a carrier mobility of 2230 cm2/V.s.
{"title":"Influence of annealing temperature on the performance of graphene / SiC transistors with high-k / metal gate","authors":"M. Clavel, T. Poiroux, M. Mouis, L. Becerra, J. Thomassin, A. Zenasni, G. Lapertot, D. Rouchon, D. Lafond, O. Faynot","doi":"10.1109/ULIS.2011.5757955","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757955","url":null,"abstract":"In this study, we investigate the impact of thermal annealing on the electrical characteristics of epitaxial graphene field effect transistors. Top gated devices were fabricated from graphene obtained on silicon carbide (SiC) substrate. Thanks to an annealing at 300°C, the performance of the devices was enhanced by a factor of 90. The maximal transconductance reached really high values such as 5900µS/µm at VD=3V, corresponding to a carrier mobility of 2230 cm2/V.s.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127766000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757972
J. E. Husseini, F. Martinez, M. Bawedin, M. Valenza, R. Ritzenthaler, F. Lime, B. Iñíguez
In this paper, a new surface potential based compact model for long channel fully depleted SOI MOSFET with lightly doped ultra-thin body is presented. The 1-D Poisson equation is solved using the appropriate boundary conditions, and a closed-form surface potential solution is proposed for the front and back surface potentials. Finally the model was compared to numerical simulations and a good agreement is observed.
{"title":"A surface potential based compact model for lightly doped FD SOI MOSFETs with ultra-thin body","authors":"J. E. Husseini, F. Martinez, M. Bawedin, M. Valenza, R. Ritzenthaler, F. Lime, B. Iñíguez","doi":"10.1109/ULIS.2011.5757972","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757972","url":null,"abstract":"In this paper, a new surface potential based compact model for long channel fully depleted SOI MOSFET with lightly doped ultra-thin body is presented. The 1-D Poisson equation is solved using the appropriate boundary conditions, and a closed-form surface potential solution is proposed for the front and back surface potentials. Finally the model was compared to numerical simulations and a good agreement is observed.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132743413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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