Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757975
P. Magnone, C. Fiegna, G. Greco, G. Bazzano, E. Sangiorgi, S. Rinaudo
In this work we propose a methodology to define an equivalent resistive thermal network that allows to model the lateral heat propagation through the silicon substrate of power devices. The basic idea is to split the substrate in basic elements of length ΔL and to associate to each element, lumped thermal resistances. The proposed model is validated by comparison with electro-thermal numerical simulations in silicon Power MOSFET technology. The proposed thermal network accurately predicts the temperature increase as a function of the distance from the heat source.
{"title":"Modeling of thermal network in silicon power MOSFETs","authors":"P. Magnone, C. Fiegna, G. Greco, G. Bazzano, E. Sangiorgi, S. Rinaudo","doi":"10.1109/ULIS.2011.5757975","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757975","url":null,"abstract":"In this work we propose a methodology to define an equivalent resistive thermal network that allows to model the lateral heat propagation through the silicon substrate of power devices. The basic idea is to split the substrate in basic elements of length ΔL and to associate to each element, lumped thermal resistances. The proposed model is validated by comparison with electro-thermal numerical simulations in silicon Power MOSFET technology. The proposed thermal network accurately predicts the temperature increase as a function of the distance from the heat source.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114317254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757956
S. M. Sultan, K. Sun, J. Partridge, M. Allen, P. Ashburn, H. Chong
ZnO nanowire devices were fabricated from top-down using optical lithography. The nanowires are formed from anisotropic etch of 100 nm Filtered Cathodic Vacuum Arc (FCVA) deposited ZnO thin film. The nanowires are characterized using SEM and Raman spectroscopy via image mapping. The current-voltage characteristics showed a typical ohmic behaviour after contact annealing, reflecting the influence of the lowering of contact barriers between the ZnO nanowire device and the Al metal electrode.
{"title":"Fabrication of ZnO nanowire device using top-down approach","authors":"S. M. Sultan, K. Sun, J. Partridge, M. Allen, P. Ashburn, H. Chong","doi":"10.1109/ULIS.2011.5757956","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757956","url":null,"abstract":"ZnO nanowire devices were fabricated from top-down using optical lithography. The nanowires are formed from anisotropic etch of 100 nm Filtered Cathodic Vacuum Arc (FCVA) deposited ZnO thin film. The nanowires are characterized using SEM and Raman spectroscopy via image mapping. The current-voltage characteristics showed a typical ohmic behaviour after contact annealing, reflecting the influence of the lowering of contact barriers between the ZnO nanowire device and the Al metal electrode.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"136 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123445398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758017
A. Karmous, H. Xu, M. Oehme, E. Kasper, J. Schulze
Schottky diode structures with Ge quantum dots (QDs) have been grown by Molecular Beam Epitaxy (MBE). They have been employed to fabricate NiSi Schottky diodes with Ge dots buried below the metal-semiconductor junctions. These diodes have cut-off frequencies up to 1.1THz (calculated from S-parameter measurements up to 110GHz). Preliminary results demonstrating the implementation of Ge QD Schottky diode in a mm-wave power detection system (RECTENNA) are also presented.
{"title":"Ge quantum dot Schottky diode operated in a 89GHz Rectenna","authors":"A. Karmous, H. Xu, M. Oehme, E. Kasper, J. Schulze","doi":"10.1109/ULIS.2011.5758017","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758017","url":null,"abstract":"Schottky diode structures with Ge quantum dots (QDs) have been grown by Molecular Beam Epitaxy (MBE). They have been employed to fabricate NiSi Schottky diodes with Ge dots buried below the metal-semiconductor junctions. These diodes have cut-off frequencies up to 1.1THz (calculated from S-parameter measurements up to 110GHz). Preliminary results demonstrating the implementation of Ge QD Schottky diode in a mm-wave power detection system (RECTENNA) are also presented.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758002
L. De Michielis, M. Iellina, P. Palestri, A. Ionescu, L. Selmi
In this work a non-local band-to-band tunnelling model has been implemented into a full-band Monte Carlo simulator. Two different approaches for the choice of the tunnelling path have been implemented and their impact on the transfer characteristics of different Tunnel FET structures is investigated. In both the SOI and the DG TFET architectures we have simulated, up to 1 order of magnitude of underestimation in the current and up to 15% of difference in the value of the Subthreshold Slope can be found according to the choice of the tunnelling path.
{"title":"Tunneling path impact on semi-classical numerical simulations of TFET devices","authors":"L. De Michielis, M. Iellina, P. Palestri, A. Ionescu, L. Selmi","doi":"10.1109/ULIS.2011.5758002","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758002","url":null,"abstract":"In this work a non-local band-to-band tunnelling model has been implemented into a full-band Monte Carlo simulator. Two different approaches for the choice of the tunnelling path have been implemented and their impact on the transfer characteristics of different Tunnel FET structures is investigated. In both the SOI and the DG TFET architectures we have simulated, up to 1 order of magnitude of underestimation in the current and up to 15% of difference in the value of the Subthreshold Slope can be found according to the choice of the tunnelling path.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"20 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5757989
A. Pham, B. Sorée, W. Magnus, C. Jungemann, B. Meinerzhagen, G. Pourtois
Junctionless nanowire pinch-off FETs [1–3] are promising device structures for beyond CMOS technologies. The device is called ”junctionless” [3] because it contains a uniform doping level (n+ n+ n+ for nFETs or p+ p+ p+ for pFETs) within the whole device including source, drain, and channel, which is different from the non-uniform n+ pn+ (or p+ np+) doping profiles in conventional nMOSFETs (or pMOSFETs). Therefore, during the fabrication the doping profile in junctionless nanowire pinch-off FETs is easier to control than in the conventional MOSFET case, especially for sub-100 nm gate length devices [3]. In additions, junctionless pinch-off FETs operate similar to JFETs and inversion is not required. In order to turn off the device, a sufficiently large |VGS| is required to extend the depletion region until pinch-off occurs. This is the reason for the name ”pinch-off” FET. If the horizontal cross-section area of the nanowire is scaled, the doping level must be increased in order to keep the threshold voltage unchanged [1]. Due to the high doping levels (typically 1018 cm−3 to 5 × 1019 cm−3) the carriers are strongly influenced by ionized impurity scattering, and as a consequence, the channel effective mobility is low. Therefore, it is important to include stress/strain engineering in combination with non-standard crystallographic channel orientations to boost the transport performance of the junctionless nanowire pinch-off FET.
{"title":"Quantum simulations of electrostatics in Si cylindrical nanowire pinch-off nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations","authors":"A. Pham, B. Sorée, W. Magnus, C. Jungemann, B. Meinerzhagen, G. Pourtois","doi":"10.1109/ULIS.2011.5757989","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5757989","url":null,"abstract":"Junctionless nanowire pinch-off FETs [1–3] are promising device structures for beyond CMOS technologies. The device is called ”junctionless” [3] because it contains a uniform doping level (n<sup>+</sup> n<sup>+</sup> n<sup>+</sup> for nFETs or p<sup>+</sup> p<sup>+</sup> p<sup>+</sup> for pFETs) within the whole device including source, drain, and channel, which is different from the non-uniform n<sup>+</sup> pn<sup>+</sup> (or p<sup>+</sup> np<sup>+</sup>) doping profiles in conventional nMOSFETs (or pMOSFETs). Therefore, during the fabrication the doping profile in junctionless nanowire pinch-off FETs is easier to control than in the conventional MOSFET case, especially for sub-100 nm gate length devices [3]. In additions, junctionless pinch-off FETs operate similar to JFETs and inversion is not required. In order to turn off the device, a sufficiently large |V<inf>GS</inf>| is required to extend the depletion region until pinch-off occurs. This is the reason for the name ”pinch-off” FET. If the horizontal cross-section area of the nanowire is scaled, the doping level must be increased in order to keep the threshold voltage unchanged [1]. Due to the high doping levels (typically 10<sup>18</sup> cm<sup>−3</sup> to 5 × 10<sup>19</sup> cm<sup>−3</sup>) the carriers are strongly influenced by ionized impurity scattering, and as a consequence, the channel effective mobility is low. Therefore, it is important to include stress/strain engineering in combination with non-standard crystallographic channel orientations to boost the transport performance of the junctionless nanowire pinch-off FET.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"31 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132359765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758003
S. Rigante, P. Livi, A. Hierlemann, A. Ionescu
Two different silicon nanowire (SiNW) based devices are discussed as potential ion and biological sensors. Three-dimensional TCAD simulations are used to investigate and compare the efficiency of such devices upon applying an external voltage difference of ΔVg = 50 mV. The simulation results presented in this work reveal that an n-doped shell acts as sensitivity booster for uniformly doped SiNWs. It is demonstrated that a 10 nm n-type shell surrounding a p-type core can produce a sensitivity enhancement of more than 50%.
{"title":"A simulation study of N-shell silicon nanowires as biological sensors","authors":"S. Rigante, P. Livi, A. Hierlemann, A. Ionescu","doi":"10.1109/ULIS.2011.5758003","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758003","url":null,"abstract":"Two different silicon nanowire (SiNW) based devices are discussed as potential ion and biological sensors. Three-dimensional TCAD simulations are used to investigate and compare the efficiency of such devices upon applying an external voltage difference of ΔVg = 50 mV. The simulation results presented in this work reveal that an n-doped shell acts as sensitivity booster for uniformly doped SiNWs. It is demonstrated that a 10 nm n-type shell surrounding a p-type core can produce a sensitivity enhancement of more than 50%.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114104634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758007
M. Naiini, G. Malm, M. Ostling
Compact broadband grating couplers are designed and studied utilizing Atomic Layer Deposited Horizontal Slot waveguides, with four well-known material layers as the slot. Fabrication process conditions are experimentally studied to obtain more optimized designs. With the precision of the film thickness and refractive index provided by ALD, fabrication of reproducible grating couplers is feasible. An overview of design guidelines regarding the slot size and slot material is provided by 2D Finite Element Method calculations.
{"title":"Fully etched grating couplers for atomic layer deposited horizontal slot waveguides","authors":"M. Naiini, G. Malm, M. Ostling","doi":"10.1109/ULIS.2011.5758007","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758007","url":null,"abstract":"Compact broadband grating couplers are designed and studied utilizing Atomic Layer Deposited Horizontal Slot waveguides, with four well-known material layers as the slot. Fabrication process conditions are experimentally studied to obtain more optimized designs. With the precision of the film thickness and refractive index provided by ALD, fabrication of reproducible grating couplers is feasible. An overview of design guidelines regarding the slot size and slot material is provided by 2D Finite Element Method calculations.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116772981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758010
G. Duesberg
Silicon based devices form the foundation of today's integrated circuitry. However, as advancements in information and communication technologies demand ever decreasing device feature sizes, conventional materials are ultimately reaching processing limits. Consequently, extensive research is being carried out on novel materials for future device fabrication. In this paper research on nano-carbon structures for applications beyond CMOS devices is reviewed. Progress in the synthesis, processing and integration of ultra-thin conducting carbon films, graphene and nanotubes for applications such as interconnects, transistors, spintronics and sensing are critically reviewed.
{"title":"Nanocarbon structures for electronic applications — A critical review","authors":"G. Duesberg","doi":"10.1109/ULIS.2011.5758010","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758010","url":null,"abstract":"Silicon based devices form the foundation of today's integrated circuitry. However, as advancements in information and communication technologies demand ever decreasing device feature sizes, conventional materials are ultimately reaching processing limits. Consequently, extensive research is being carried out on novel materials for future device fabrication. In this paper research on nano-carbon structures for applications beyond CMOS devices is reviewed. Progress in the synthesis, processing and integration of ultra-thin conducting carbon films, graphene and nanotubes for applications such as interconnects, transistors, spintronics and sensing are critically reviewed.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129476207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758004
R. Ishihara, N. Golshani, J. Derakhshandeh, M. R. T. Mofrad, C. Beenakker
We propose monolithic 3D-ICs based on single grain Si TFTs where transistors are fabricated inside a silicon grain. Location of the grain was controlled by the µ-Czochralski process which is based on pulsed-laser crystallization of a-Si. Two single-grain TFTs layers were monolithically stacked with electron and hole mobilities of 600 cm2/Vs and 200 cm2/Vs, respectively. Electrical properties are presented of fabricated 6T-SRAM and lateral photodiodes with in-pixel amplifier. Photodiode pixels have a light sensitivity of 100 while SRAM cells fabricated in 128F2 area shows a static noise margin of 0.75V with a supply voltage of 5V.
{"title":"Monolithic 3D-ICs with single grain Si thin film transistors","authors":"R. Ishihara, N. Golshani, J. Derakhshandeh, M. R. T. Mofrad, C. Beenakker","doi":"10.1109/ULIS.2011.5758004","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758004","url":null,"abstract":"We propose monolithic 3D-ICs based on single grain Si TFTs where transistors are fabricated inside a silicon grain. Location of the grain was controlled by the µ-Czochralski process which is based on pulsed-laser crystallization of a-Si. Two single-grain TFTs layers were monolithically stacked with electron and hole mobilities of 600 cm2/Vs and 200 cm2/Vs, respectively. Electrical properties are presented of fabricated 6T-SRAM and lateral photodiodes with in-pixel amplifier. Photodiode pixels have a light sensitivity of 100 while SRAM cells fabricated in 128F2 area shows a static noise margin of 0.75V with a supply voltage of 5V.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127627473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-14DOI: 10.1109/ULIS.2011.5758012
T. Rudenko, V. Kilchytska, M. Arshad, J. Raskin, A. Nazarov, D. Flandre
In this work, we study the effect of the drain voltage on the threshold voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.
在这项工作中，我们利用在UTB SOI mosfet上获得的分析建模和实验数据，通过跨导和跨导电流比变化方法研究了漏极电压对长通道mosfet阈值电压提取的影响。
{"title":"Influence of drain voltage on MOSFET threshold voltage determination by transconductance change and gm/Id methods","authors":"T. Rudenko, V. Kilchytska, M. Arshad, J. Raskin, A. Nazarov, D. Flandre","doi":"10.1109/ULIS.2011.5758012","DOIUrl":"https://doi.org/10.1109/ULIS.2011.5758012","url":null,"abstract":"In this work, we study the effect of the drain voltage on the threshold voltage extraction in long-channel MOSFETs by the transconductance and transconductance-to-current-ratio change methods, using analytical modeling and experimental data obtained on UTB SOI MOSFETs.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127904544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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