Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488312
F. Piazza, C. Boccaccio, S. Bruyère, Riccardo Cea, Bill Clark, N. Degors, Christopher N. Collins, A. Gandolfo, A. Gilardini, E. Gomiero, Pierre-Marie Mans, G. Mastracchio, D. Pacelli, N. Planes, J. Simon, M. Weybright, A. Maurelli
In this paper the results obtained for a new process flow that integrates a high performance flash cell for automotive application with a state of the art 65nm CMOS have been presented. Despite the several specific process steps introduced for the first time on embedded technologies, the MOS performances have not been impacted by the integration of the Flash cell and the related HV MOS and the results obtained on a 4Mbit Flash array are very promising.
{"title":"High performance Flash memory for 65 nm embedded automotive application","authors":"F. Piazza, C. Boccaccio, S. Bruyère, Riccardo Cea, Bill Clark, N. Degors, Christopher N. Collins, A. Gandolfo, A. Gilardini, E. Gomiero, Pierre-Marie Mans, G. Mastracchio, D. Pacelli, N. Planes, J. Simon, M. Weybright, A. Maurelli","doi":"10.1109/IMW.2010.5488312","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488312","url":null,"abstract":"In this paper the results obtained for a new process flow that integrates a high performance flash cell for automotive application with a state of the art 65nm CMOS have been presented. Despite the several specific process steps introduced for the first time on embedded technologies, the MOS performances have not been impacted by the integration of the Flash cell and the related HV MOS and the results obtained on a 4Mbit Flash array are very promising.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122502973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488382
S. Lai, Chih-Ping Chen, P. Du, H. Lue, D. Heh, Chih-Yen Shen, F. Hsueh, H. Wu, J. Liao, J. Hsieh, M.T. Wu, F. Hsu, S. Hong, C. Yeh, Yung-tai Hung, K. Hsieh, Chih-Yuan Lu
The behavior of barrier engineered charge trapping devices incorporating Al2O3 and HfO2 high-K layers has been critically examined. We propose to use a thicker buffer oxide (≫ 6 nm) and thin (≪5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it also reduces the undesired transient read current relaxation. These effects are due to the bulk trapped charge in high-K material during programming/erasing. By reducing the high-K thickness these reliability issues can be minimized. We also found that HfO2 has a better thickness scaling capability than Al2O3. Finally, a high-performance BE-SHONOS (with n+-poly gate and HfO2 top capping layer) transistor is demonstrated in this work.
{"title":"A study of barrier engineered Al2O3 and HfO2 high-K charge trapping devices (BE-MAONOS and BE-MHONOS) with optimal high-K thickness","authors":"S. Lai, Chih-Ping Chen, P. Du, H. Lue, D. Heh, Chih-Yen Shen, F. Hsueh, H. Wu, J. Liao, J. Hsieh, M.T. Wu, F. Hsu, S. Hong, C. Yeh, Yung-tai Hung, K. Hsieh, Chih-Yuan Lu","doi":"10.1109/IMW.2010.5488382","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488382","url":null,"abstract":"The behavior of barrier engineered charge trapping devices incorporating Al<inf>2</inf>O<inf>3</inf> and HfO<inf>2</inf> high-K layers has been critically examined. We propose to use a thicker buffer oxide (≫ 6 nm) and thin (≪5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it also reduces the undesired transient read current relaxation. These effects are due to the bulk trapped charge in high-K material during programming/erasing. By reducing the high-K thickness these reliability issues can be minimized. We also found that HfO<inf>2</inf> has a better thickness scaling capability than Al<inf>2</inf>O<inf>3</inf>. Finally, a high-performance BE-SHONOS (with n<sup>+</sup>-poly gate and HfO<inf>2</inf> top capping layer) transistor is demonstrated in this work.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131110861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488404
Lahcen Hamouche, B. Allard
Embedded cache memories consumes a large percentage of the dynamic and static energy in System-On-Chip (SOC). Energy consumption expects to increase in advanced technologies. Write and read operations operate charging and discharging of large bitline capacitances. Multiplexors are introduced in 6T-SRAM to reduce column size. Unfortunately read current is not reduced and even increases. Considering the 5T Portless SRAM, an original multiplexor structure is presented that offers a significant gain in active energy consumption. The multiplexor benefits from a hard line duplication technique that copies an addressed line into an other line in one clock cycle. The advantages of the latter duplication technique are presented in details. Moreover Portless bitcell is more stable, suffers less leakage than 6T SRAM bitcell. The paper confirms that Portless SRAM is a candidate alternative structure to 6T SRAM in advanced technologies.
{"title":"PORTLESS low power mux architecture with line hard duplication","authors":"Lahcen Hamouche, B. Allard","doi":"10.1109/IMW.2010.5488404","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488404","url":null,"abstract":"Embedded cache memories consumes a large percentage of the dynamic and static energy in System-On-Chip (SOC). Energy consumption expects to increase in advanced technologies. Write and read operations operate charging and discharging of large bitline capacitances. Multiplexors are introduced in 6T-SRAM to reduce column size. Unfortunately read current is not reduced and even increases. Considering the 5T Portless SRAM, an original multiplexor structure is presented that offers a significant gain in active energy consumption. The multiplexor benefits from a hard line duplication technique that copies an addressed line into an other line in one clock cycle. The advantages of the latter duplication technique are presented in details. Moreover Portless bitcell is more stable, suffers less leakage than 6T SRAM bitcell. The paper confirms that Portless SRAM is a candidate alternative structure to 6T SRAM in advanced technologies.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131269207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488327
L. Goux, G. Hurkx, X. P. Wang, Romain Delhougne, K. Attenborough, Dirk J. Gravesteijn, Dirk Wouters, J. P. Gonzalez
In this work we propose a novel method for fast and reliable evaluation of the retention properties of phase-change memory cells, based on the modeling of the temperature-ramp characteristics. Using this method we investigate the influence of the length and thickness of the amorphous mark on the retention lifetime. The results show that the degradation of the retention properties with the cell scaling is limited.
{"title":"Extraction of the retention properties of a phase-change cell from temperature-ramp tests using a novel method","authors":"L. Goux, G. Hurkx, X. P. Wang, Romain Delhougne, K. Attenborough, Dirk J. Gravesteijn, Dirk Wouters, J. P. Gonzalez","doi":"10.1109/IMW.2010.5488327","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488327","url":null,"abstract":"In this work we propose a novel method for fast and reliable evaluation of the retention properties of phase-change memory cells, based on the modeling of the temperature-ramp characteristics. Using this method we investigate the influence of the length and thickness of the amorphous mark on the retention lifetime. The results show that the degradation of the retention properties with the cell scaling is limited.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124027609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488330
S. Baek, S. Yang, Jae-young Ahn, B. Koo, K. Hwang, Siyoung Choi, C. Kang, J. Moon
We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO2/a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can be modified, which made it possible to achieve tunnel barrier engineering without employing high-k material. By reducing the erase voltage, the reliabilities of NAND flash memory was improved.
我们提出了异质堆叠氧化物(HSO)作为未来高密度NAND闪存隧道氧化物的材料。HSO采用隧道屏障工程的概念，结构为SiO2/a- si /a- siox。通过使用HSO隧道势垒，可以制造出比单层隧道氧化物更厚、更薄的隧道氧化物。可以改变a-SiOx的带隙，从而实现不使用高k材料的隧道障壁工程。通过降低擦除电压，提高了NAND闪存的可靠性。
{"title":"Characterization of novel SiO2/a-Si/a-SiOx tunnel barrier engineered oxide","authors":"S. Baek, S. Yang, Jae-young Ahn, B. Koo, K. Hwang, Siyoung Choi, C. Kang, J. Moon","doi":"10.1109/IMW.2010.5488330","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488330","url":null,"abstract":"We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO2/a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can be modified, which made it possible to achieve tunnel barrier engineering without employing high-k material. By reducing the erase voltage, the reliabilities of NAND flash memory was improved.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115599168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488395
A. Bivens, Parijat Dube, M. Franceschini, J. Karidis, L. Lastras, M. Tsao
New enterprise workloads requiring fast, reliable access to increasing amounts of data have pushed today's memory systems to power and capacity limits while creating bottlenecks as they ensure transactions are persistently tracked for reliability. New storage class memory technologies (such as phase change memory) have the potential to offer high capacity within latency and bandwidth ranges acceptable for a computer memory system and persistence which may help ease the system-level burden of balancing performance and reliability. This paper describes architectural options for addressing the challenges of future, heterogeneous memory systems as well as the attributes required of the next generation memory devices.
{"title":"Architectural design for next generation heterogeneous memory systems","authors":"A. Bivens, Parijat Dube, M. Franceschini, J. Karidis, L. Lastras, M. Tsao","doi":"10.1109/IMW.2010.5488395","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488395","url":null,"abstract":"New enterprise workloads requiring fast, reliable access to increasing amounts of data have pushed today's memory systems to power and capacity limits while creating bottlenecks as they ensure transactions are persistently tracked for reliability. New storage class memory technologies (such as phase change memory) have the potential to offer high capacity within latency and bandwidth ranges acceptable for a computer memory system and persistence which may help ease the system-level burden of balancing performance and reliability. This paper describes architectural options for addressing the challenges of future, heterogeneous memory systems as well as the attributes required of the next generation memory devices.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128394942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488388
Yunbong Lee, Byoungjun Park, DaeHwan Yun, YeonJoo Jeong, P. H. Kim, Ji Yul Park, Hae chang Yang, M. Cho, K. Ahn, Y. Koh
This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed Vth level, new HCI disturbance and charge loss in the highest programmed level.
{"title":"The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology","authors":"Yunbong Lee, Byoungjun Park, DaeHwan Yun, YeonJoo Jeong, P. H. Kim, Ji Yul Park, Hae chang Yang, M. Cho, K. Ahn, Y. Koh","doi":"10.1109/IMW.2010.5488388","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488388","url":null,"abstract":"This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed Vth level, new HCI disturbance and charge loss in the highest programmed level.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488326
C. Zambelli, A. Chimenton, P. Olivo
In this work we have investigated the seasoning effect in SET state occurring during cycling of multimegabit Phase Change Memory arrays. The impact of the erasing waveform on this phenomenon has been experimentally evaluated. The physical nature of the phenomenon has been discussed in relation to the electro-thermal characteristics of the active material. The study of such phenomenon is also important to comprehend the transition dynamics of the GST material towards its crystalline state and to develop accurate models allowing an estimate of the PCM cells behavior as a function of the operative cycles.
{"title":"Experimental characterization of SET seasoning on Phase Change Memory arrays","authors":"C. Zambelli, A. Chimenton, P. Olivo","doi":"10.1109/IMW.2010.5488326","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488326","url":null,"abstract":"In this work we have investigated the seasoning effect in SET state occurring during cycling of multimegabit Phase Change Memory arrays. The impact of the erasing waveform on this phenomenon has been experimentally evaluated. The physical nature of the phenomenon has been discussed in relation to the electro-thermal characteristics of the active material. The study of such phenomenon is also important to comprehend the transition dynamics of the GST material towards its crystalline state and to develop accurate models allowing an estimate of the PCM cells behavior as a function of the operative cycles.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114106471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488317
F. Nardi, D. Ielmini, C. Cagli, S. Spiga, M. Fanciulli, L. Goux, D. Wouters
NiO-based resistive-switching memory (RRAM) is attracting a growing research interest for high-density non-volatile storage applications. One of the most difficult challenges for RRAM-based high-density memories is the high current necessary for the reset operation (Ireset), which limits the possibilities of scaling for the select diode in the cross-bar memory array. This work addresses the scalability of the reset current Ireset in NiO-based RRAM by limiting the set current through an integrated series MOSFET. Ireset is shown to be controllable down to below 10 µA. The consequences of these findings for the select diode in the cross-bar array structure are finally discussed.
{"title":"Sub-10 µA reset in NiO-based resistive switching memory (RRAM) cells","authors":"F. Nardi, D. Ielmini, C. Cagli, S. Spiga, M. Fanciulli, L. Goux, D. Wouters","doi":"10.1109/IMW.2010.5488317","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488317","url":null,"abstract":"NiO-based resistive-switching memory (RRAM) is attracting a growing research interest for high-density non-volatile storage applications. One of the most difficult challenges for RRAM-based high-density memories is the high current necessary for the reset operation (Ireset), which limits the possibilities of scaling for the select diode in the cross-bar memory array. This work addresses the scalability of the reset current Ireset in NiO-based RRAM by limiting the set current through an integrated series MOSFET. Ireset is shown to be controllable down to below 10 µA. The consequences of these findings for the select diode in the cross-bar array structure are finally discussed.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122887281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488411
T. Tanzawa
For decades, advances in lithography and improvements in device technology have been scaling the NAND Flash memory cells in L and W directions. On the other hand, Z direction, or tunnel oxide thickness, has not been scaled. This is because of stress-induced leakage current that results in program and erase voltages and high-voltage (HV) transistors unscaled. This paper focuses on scaling the HV transistors with a proposed circuit design relaxing the gate stress. The proposed circuit enables the gate oxide thickness of HV transistors to be reduced by 10%, which results in a die size reduction of 2.4%. This paper also proposes a simple estimation equation for HV PMOS negative bias temperature instability (NBTI) lifetime in case of step-up programming pulses.
{"title":"NBTI stress relaxation design for scaling high-voltage transistors in NAND Flash memories","authors":"T. Tanzawa","doi":"10.1109/IMW.2010.5488411","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488411","url":null,"abstract":"For decades, advances in lithography and improvements in device technology have been scaling the NAND Flash memory cells in L and W directions. On the other hand, Z direction, or tunnel oxide thickness, has not been scaled. This is because of stress-induced leakage current that results in program and erase voltages and high-voltage (HV) transistors unscaled. This paper focuses on scaling the HV transistors with a proposed circuit design relaxing the gate stress. The proposed circuit enables the gate oxide thickness of HV transistors to be reduced by 10%, which results in a die size reduction of 2.4%. This paper also proposes a simple estimation equation for HV PMOS negative bias temperature instability (NBTI) lifetime in case of step-up programming pulses.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114790975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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