Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488387
E. Nowak, A. Hubert, L. Perniola, T. Ernst, G. Ghibaudo, G. Reimbold, B. De Salvo, F. Boulanger
In this work, we present a detailed investigation of the electrical characteristics of 3D Gate-All-Around (GAA) Silicon nanowire (down to 6nm-diameter) SONOS memories compared to standard planar SONOS devices. In particular, by means of TCAD simulations, the write, erase and retention characteristics under uniform FN stress are explained and the main geometrical and electrostatic effects of 3D cylindrical devices are put in evidence. The physical mechanisms dominating the 3D devices performance and reliability are identified. In particular, the great influence of band-to-band phenomenon in the erase characteristics is underlined.
{"title":"In-depth analysis of 3D Silicon nanowire SONOS memory characteristics by TCAD simulations","authors":"E. Nowak, A. Hubert, L. Perniola, T. Ernst, G. Ghibaudo, G. Reimbold, B. De Salvo, F. Boulanger","doi":"10.1109/IMW.2010.5488387","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488387","url":null,"abstract":"In this work, we present a detailed investigation of the electrical characteristics of 3D Gate-All-Around (GAA) Silicon nanowire (down to 6nm-diameter) SONOS memories compared to standard planar SONOS devices. In particular, by means of TCAD simulations, the write, erase and retention characteristics under uniform FN stress are explained and the main geometrical and electrostatic effects of 3D cylindrical devices are put in evidence. The physical mechanisms dominating the 3D devices performance and reliability are identified. In particular, the great influence of band-to-band phenomenon in the erase characteristics is underlined.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133639956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488406
Byoungchan Oh, Heung-Jae Cho, Heesang Kim, Hyungcheol Shin
Multi level RTNs have been measured in GIDL current of DRAM cell transistor. Three-level RTN which has not been reported in GIDL current was observed. We found that this RTN has unique characteristics which could be distinguished from two-level RTN by single trap and four-level RTN due to two traps. Also, we discussed bias dependency of time constants of the three-level RTN.
{"title":"Observation of three-level random telegraph noise in GIDL current of Saddle-Fin type DRAM cell transistor","authors":"Byoungchan Oh, Heung-Jae Cho, Heesang Kim, Hyungcheol Shin","doi":"10.1109/IMW.2010.5488406","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488406","url":null,"abstract":"Multi level RTNs have been measured in GIDL current of DRAM cell transistor. Three-level RTN which has not been reported in GIDL current was observed. We found that this RTN has unique characteristics which could be distinguished from two-level RTN by single trap and four-level RTN due to two traps. Also, we discussed bias dependency of time constants of the three-level RTN.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116282706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488315
K. Kinoshita, T. Okutani, H. Tanaka, T. Hinoki, H. Agura, K. Yazawa, K. Ohmi, S. Kishida
Fabrication of flexible transparent ReRAM consisting of the GZO memory layer and GZO-electrodes on the PEN sheet with large area was attained by the introduction of the RF plasma assist DC magnetron sputtering method. Resistive switching mechanism of all-GZO-FT-ReRAM can be explained by the redox model as well as that of conventional binary transition metal oxides. Reset switching of all-GZO-FT-ReRAM which memory layer is GZO(RH2=5%) is smooth and continuous, which enables the verify operation and the multilevel application.
{"title":"Flexible and transparent ReRAM with GZO-memory-layer and GZO-electrodes on large PEN sheet","authors":"K. Kinoshita, T. Okutani, H. Tanaka, T. Hinoki, H. Agura, K. Yazawa, K. Ohmi, S. Kishida","doi":"10.1109/IMW.2010.5488315","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488315","url":null,"abstract":"Fabrication of flexible transparent ReRAM consisting of the GZO memory layer and GZO-electrodes on the PEN sheet with large area was attained by the introduction of the RF plasma assist DC magnetron sputtering method. Resistive switching mechanism of all-GZO-FT-ReRAM can be explained by the redox model as well as that of conventional binary transition metal oxides. Reset switching of all-GZO-FT-ReRAM which memory layer is GZO(RH2=5%) is smooth and continuous, which enables the verify operation and the multilevel application.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114644351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488400
H. Yang, L. P. Shi, H. K. Lee, R. Zhao, M.H. Li, J.M. Li, K. G. Lim, T. Chong
A multi-layer lateral PCM with N-doped Sb70Te30 was proposed and demonstrated. Both current sweep and pulse mode dynamic resistance test show that multi states exist in the device, which can be used for multi-level data storage. Simulation shows the working mechanism of multi-level and confirms the experiment results. More intermediate states can be realized by increasing the cycles of N-doped Sb70Te30 and ZnS-SiO2 deposited and by using different film thickness, which will be a promising solution to increase the data storage capacity for PCM largely.
{"title":"Multi-level lateral phase change memory based on N-doped Sb70Te30 super-lattice like structure","authors":"H. Yang, L. P. Shi, H. K. Lee, R. Zhao, M.H. Li, J.M. Li, K. G. Lim, T. Chong","doi":"10.1109/IMW.2010.5488400","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488400","url":null,"abstract":"A multi-layer lateral PCM with N-doped Sb70Te30 was proposed and demonstrated. Both current sweep and pulse mode dynamic resistance test show that multi states exist in the device, which can be used for multi-level data storage. Simulation shows the working mechanism of multi-level and confirms the experiment results. More intermediate states can be realized by increasing the cycles of N-doped Sb70Te30 and ZnS-SiO2 deposited and by using different film thickness, which will be a promising solution to increase the data storage capacity for PCM largely.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121565891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488401
S. Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, C. Chappert, P. Mazoyer
In this paper, we present a new design of TAS-MRAM, which is dedicated for the embedded applications. The Thermally Assisted Switching (TAS) approach allows the low power memory programming and Pre-Charge Sense Amplifiers (PCSA) enable the reliable, high speed and low power sensing. By using a TAS-MTJ spice model integrating the precise experimental parameters and CMOS 130nm technology, simulations have been done to demonstrate the expected performances; a 128Kb prototype has been developed to validate experimentally the new design by means of standard cell and automatic macro generation techniques.
{"title":"Design of TAS-MRAM prototype for NV embedded memory applications","authors":"S. Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, C. Chappert, P. Mazoyer","doi":"10.1109/IMW.2010.5488401","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488401","url":null,"abstract":"In this paper, we present a new design of TAS-MRAM, which is dedicated for the embedded applications. The Thermally Assisted Switching (TAS) approach allows the low power memory programming and Pre-Charge Sense Amplifiers (PCSA) enable the reliable, high speed and low power sensing. By using a TAS-MTJ spice model integrating the precise experimental parameters and CMOS 130nm technology, simulations have been done to demonstrate the expected performances; a 128Kb prototype has been developed to validate experimentally the new design by means of standard cell and automatic macro generation techniques.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121091892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488322
K. Miyaji, S. Noda, T. Hatanaka, Mitsue Takahashi, S. Sakai, K. Takeuchi
A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe-) NAND flash memories. In the proposed SCSB scheme, only the channel voltage of the cell to which the program voltage VPGM is applied is self-boosted in the program-inhibit NAND string. The proposed program scheme shows an excellent tolerance to the program disturb at the power supply voltage, VCC=1.0V. The power consumption of the Fe-NAND at VCC=1.0V decreases by 86% compared with the conventional floating gate (FG-) NAND at VCC=1.8V without degrading the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.9 times. As a result, the 9.5GByte/sec write throughput of the Fe-NAND SSD is achieved for an enterprise application.
{"title":"A 1.0V power supply, 9.5GByte/sec write speed, Single-Cell Self-Boost program scheme for Ferroelectric NAND Flash SSD","authors":"K. Miyaji, S. Noda, T. Hatanaka, Mitsue Takahashi, S. Sakai, K. Takeuchi","doi":"10.1109/IMW.2010.5488322","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488322","url":null,"abstract":"A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe-) NAND flash memories. In the proposed SCSB scheme, only the channel voltage of the cell to which the program voltage VPGM is applied is self-boosted in the program-inhibit NAND string. The proposed program scheme shows an excellent tolerance to the program disturb at the power supply voltage, VCC=1.0V. The power consumption of the Fe-NAND at VCC=1.0V decreases by 86% compared with the conventional floating gate (FG-) NAND at VCC=1.8V without degrading the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.9 times. As a result, the 9.5GByte/sec write throughput of the Fe-NAND SSD is achieved for an enterprise application.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117118501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488398
R. Bez, S. Bossi, B. Gleixner, F. Pellizzer, A. Pirovano, G. Servalli, M. Tosi
At the beginning of this decade, in early 2000, few disruptive technologies had been proposed to replace the industry standard Non-Volatile Memory (NVM) technology and to enlarge the Flash application base [1]. A widely accepted statement was that if any technology will succeed, it will materialize in the next decade.
{"title":"Phase Change Memory development trends","authors":"R. Bez, S. Bossi, B. Gleixner, F. Pellizzer, A. Pirovano, G. Servalli, M. Tosi","doi":"10.1109/IMW.2010.5488398","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488398","url":null,"abstract":"At the beginning of this decade, in early 2000, few disruptive technologies had been proposed to replace the industry standard Non-Volatile Memory (NVM) technology and to enlarge the Flash application base [1]. A widely accepted statement was that if any technology will succeed, it will materialize in the next decade.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"1958 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129586396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488385
G. Van den bosch, A. Arreghini, L. Breuil, A. Cacciato, T. Schram, A. Suhane, M. Zahid, M. Jurczak, J. van Houdt
In TANOS memory, deeper erase is pursued by implementing a high work function (p-type) metal gate. Our experiments show that the metal gate may also change program and retention in a way that cannot be explained by simple electrostatic considerations. Instead, we suggest that some metal gates may give rise to a change in the properties of the underlying blocking dielectric or the interface with the nitride, leading to the abovementioned observations. Hydrogen appears to be involved in this process.
{"title":"Understanding the impact of metal gate on TANOS performance and retention","authors":"G. Van den bosch, A. Arreghini, L. Breuil, A. Cacciato, T. Schram, A. Suhane, M. Zahid, M. Jurczak, J. van Houdt","doi":"10.1109/IMW.2010.5488385","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488385","url":null,"abstract":"In TANOS memory, deeper erase is pursued by implementing a high work function (p-type) metal gate. Our experiments show that the metal gate may also change program and retention in a way that cannot be explained by simple electrostatic considerations. Instead, we suggest that some metal gates may give rise to a change in the properties of the underlying blocking dielectric or the interface with the nitride, leading to the abovementioned observations. Hydrogen appears to be involved in this process.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133378677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488397
K. Takeuchi
A 3D-integrated Solid-State Drive (SSD with an adaptive program-voltage generator is introduced. The proposed boost converter is composed of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The 5 × 5mm2 spiral inductor is implemented in an interposer. The high-voltage MOS circuit is fabricated with a matured NAND flash process. The AFD controller is manufactured with a conventional 0.18um low-voltage CMOS process. The AFD controller dynamically optimizes clock frequencies and duty cycles at different values, depending on the output voltage. As a result, the power consumption, rising time, and circuit area of the program-voltage generator decreases by 88%, 73%, and 85%, respectively. The total power consumption of the NAND flash memory decreases by 68%.
{"title":"Low power 3D-integrated Solid-State Drive (SSD) with adaptive voltage generator","authors":"K. Takeuchi","doi":"10.1109/IMW.2010.5488397","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488397","url":null,"abstract":"A 3D-integrated Solid-State Drive (SSD with an adaptive program-voltage generator is introduced. The proposed boost converter is composed of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The 5 × 5mm2 spiral inductor is implemented in an interposer. The high-voltage MOS circuit is fabricated with a matured NAND flash process. The AFD controller is manufactured with a conventional 0.18um low-voltage CMOS process. The AFD controller dynamically optimizes clock frequencies and duty cycles at different values, depending on the output voltage. As a result, the power consumption, rising time, and circuit area of the program-voltage generator decreases by 88%, 73%, and 85%, respectively. The total power consumption of the NAND flash memory decreases by 68%.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488393
Kinam Kim
The rapid evolution of flash memory technologies in the previous decade has been achieved through the two distinctive ways; overcoming the scaling challenges and devising multi-bit cell transistors. The scaling challenges such as cell-to-cell interference, cell programming disturbance and patterning limit have been tackled with several breakthroughs; incorporating low-k material, relieving the stress on tunnel oxide and double patterning technology(DPT). Multi-bit cell transistors have multiplied the chip density up to 4 times with the new circuit technology and the controller algorithms. And now, the key technology in the sub-20nm technology region is finding how to integrate all the available solutions of process, device, circuit and controller issues with the most efficient ways. In the aspect of integrating each technology, we discuss technical scaling barrier in sub-20nm region and present the future candidate for high-density devices.
{"title":"Technology challenges for deep-nano semiconductor","authors":"Kinam Kim","doi":"10.1109/IMW.2010.5488393","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488393","url":null,"abstract":"The rapid evolution of flash memory technologies in the previous decade has been achieved through the two distinctive ways; overcoming the scaling challenges and devising multi-bit cell transistors. The scaling challenges such as cell-to-cell interference, cell programming disturbance and patterning limit have been tackled with several breakthroughs; incorporating low-k material, relieving the stress on tunnel oxide and double patterning technology(DPT). Multi-bit cell transistors have multiplied the chip density up to 4 times with the new circuit technology and the controller algorithms. And now, the key technology in the sub-20nm technology region is finding how to integrate all the available solutions of process, device, circuit and controller issues with the most efficient ways. In the aspect of integrating each technology, we discuss technical scaling barrier in sub-20nm region and present the future candidate for high-density devices.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115265322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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