Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811880
N. Mahalingam, Yisheng Wang, Kaixue Ma, Shouxian Mou, K. Yeo
This paper presents the design and experimental measurement of 24 GHz phase-locked loop frequency synthesizer for 60 GHz low power transceiver implemented in 0.18 μm SiGe BiCMOS process. The synthesizer employs a novel architecture with multi-coupled LC tanks for voltage controlled oscillator and injection locked frequency divide-by-2; low loss wideband power splitter and power combiner; reconfigurable divider for both integer and fractional mode of operation with choice of multiple reference frequencies. The synthesizer chip exhibits a locking range of 23.07 GHz to 26.48 GHz with a phase noise of -100.2 dBc/Hz at 1 MHz offset. The fully integrated synthesizer is controlled by slave serial peripheral interface and dissipates 42 mW from a 1.8V supply with external loop filter.
{"title":"A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPAN","authors":"N. Mahalingam, Yisheng Wang, Kaixue Ma, Shouxian Mou, K. Yeo","doi":"10.1109/ASICON.2013.6811880","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811880","url":null,"abstract":"This paper presents the design and experimental measurement of 24 GHz phase-locked loop frequency synthesizer for 60 GHz low power transceiver implemented in 0.18 μm SiGe BiCMOS process. The synthesizer employs a novel architecture with multi-coupled LC tanks for voltage controlled oscillator and injection locked frequency divide-by-2; low loss wideband power splitter and power combiner; reconfigurable divider for both integer and fractional mode of operation with choice of multiple reference frequencies. The synthesizer chip exhibits a locking range of 23.07 GHz to 26.48 GHz with a phase noise of -100.2 dBc/Hz at 1 MHz offset. The fully integrated synthesizer is controlled by slave serial peripheral interface and dissipates 42 mW from a 1.8V supply with external loop filter.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126905479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811853
Jinmei Lai, Yanquan Luo, Qianming Shao, Lichun Bao, Xueling Liu
This paper represents a Time-to-digital Converter (TDC) architecture based in a FPGA. The proposed architecture relies on a single tapped-delay line to implement time-to-digital conversion, taking advantage of the fast dedicated carry chains available within FPGAs. The results of post-route simulation indicate that this architecture offered a time resolution of 34ps with a 12 ps precision. In a Virtex-4 FPGA that is fabricated in the 90nm process this structure achieved a resolution of 48ps and a precision of 35ps.Commonly, to design a TDC on a FPGA requires iterative manual adjustment in the placement and route of the circuit; however, in the architecture presented in this paper, we controls the performance of pivotal parts of the circuit with user constraints instead of manual adjustment, which makes this TDC architecture access to portability.
{"title":"A high-resolution TDC implemented in a 90nm process FPGA","authors":"Jinmei Lai, Yanquan Luo, Qianming Shao, Lichun Bao, Xueling Liu","doi":"10.1109/ASICON.2013.6811853","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811853","url":null,"abstract":"This paper represents a Time-to-digital Converter (TDC) architecture based in a FPGA. The proposed architecture relies on a single tapped-delay line to implement time-to-digital conversion, taking advantage of the fast dedicated carry chains available within FPGAs. The results of post-route simulation indicate that this architecture offered a time resolution of 34ps with a 12 ps precision. In a Virtex-4 FPGA that is fabricated in the 90nm process this structure achieved a resolution of 48ps and a precision of 35ps.Commonly, to design a TDC on a FPGA requires iterative manual adjustment in the placement and route of the circuit; however, in the architecture presented in this paper, we controls the performance of pivotal parts of the circuit with user constraints instead of manual adjustment, which makes this TDC architecture access to portability.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126172676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tire pressure monitoring system (TPMS) is very important for the driver's safety, and it provides the status of the tires in real-time to ensure a safety driving. The design of a mixed-signal System on Chip (SoC) is the key to reduce the cost of the system. According to the recommendations of GB/T 26149-2010 TPM Sensor Module based Tire Pressure Monitoring systems for motor vehicles published in 2011; our design of a mixed-signal SoC for TPMS has been accomplished. The mixed-signal SoC is designed and fabricated using 0.35μm ASMC BCD&EE automotive process. It has been taped out. Base on the post-simulation, this mixed-signal SoC can detect the tire pressure that is ranging from 100Kpa to 750Kpa and the tire temperature ranging from -40°C to 105°C. The range of supply voltage is from 3.2V to 4.3V. Furthermore, since the battery of TPMS can't be replaced, we proposed two low power designs.
{"title":"Mixed-signal SoC design and low power research for tire pressure monitoring systems","authors":"Yangyang Guo, Liji Wu, Tengfei Zhai, Xiao Yu, Xiangmin Zhang","doi":"10.1109/ASICON.2013.6812005","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812005","url":null,"abstract":"Tire pressure monitoring system (TPMS) is very important for the driver's safety, and it provides the status of the tires in real-time to ensure a safety driving. The design of a mixed-signal System on Chip (SoC) is the key to reduce the cost of the system. According to the recommendations of GB/T 26149-2010 TPM Sensor Module based Tire Pressure Monitoring systems for motor vehicles published in 2011; our design of a mixed-signal SoC for TPMS has been accomplished. The mixed-signal SoC is designed and fabricated using 0.35μm ASMC BCD&EE automotive process. It has been taped out. Base on the post-simulation, this mixed-signal SoC can detect the tire pressure that is ranging from 100Kpa to 750Kpa and the tire temperature ranging from -40°C to 105°C. The range of supply voltage is from 3.2V to 4.3V. Furthermore, since the battery of TPMS can't be replaced, we proposed two low power designs.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126047356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811944
Peng-Fei Nan, Xu Wang, X. Qu
Ag dendrite formed on the Cu pyramids was fabricated as the SERS substrate by wet etching of Si, magnetron sputtering and galvanic displacement process. A flat sample with Ag dendrite on Cu film was prepared as a reference. The SEM results show that the Ag dendrite structure formed on the Cu pyramids exhibits much larger surface area and more nanoparticles and gaps than the flat one. Rhodamine 6G (R6G) was used to testify the Raman enhancement characteristics. It shows that the Raman peak intensity of the composite structure is 1.5 times larger than the flat one.
{"title":"Ag dendrite formed on the Cu pyramids as SERS substrate","authors":"Peng-Fei Nan, Xu Wang, X. Qu","doi":"10.1109/ASICON.2013.6811944","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811944","url":null,"abstract":"Ag dendrite formed on the Cu pyramids was fabricated as the SERS substrate by wet etching of Si, magnetron sputtering and galvanic displacement process. A flat sample with Ag dendrite on Cu film was prepared as a reference. The SEM results show that the Ag dendrite structure formed on the Cu pyramids exhibits much larger surface area and more nanoparticles and gaps than the flat one. Rhodamine 6G (R6G) was used to testify the Raman enhancement characteristics. It shows that the Raman peak intensity of the composite structure is 1.5 times larger than the flat one.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127486632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811989
Zhe Chen, Jie Yang, Cong Shi, N. Wu
This paper presents a novel architecture of the local memory for the programmable SIMD vision chip. The memory architecture consists of 8 × 8 local memory cells, among which each 8 static latches in the master stage share one dynamic latch in the slave stage. The local memory performs single bit read and write in each clock cycle, and the compact area of 14.33 μm2/bit increases the integration level of the processor. A prototype chip with 64 × 64 processing units has been manufactured in 0.18 μm CMOS technology. Five types of local memory architecture have been designed, and an 8-bit input data buffer based on dedicated latch structures has been designed as the input data buffer for each processing unit. Test results show that the presented structure is suitable for real-time computer vision applications such as the edge detection at the speed of 1000 fps.
{"title":"A novel architecture of local memory for programmable SIMD vision chip","authors":"Zhe Chen, Jie Yang, Cong Shi, N. Wu","doi":"10.1109/ASICON.2013.6811989","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811989","url":null,"abstract":"This paper presents a novel architecture of the local memory for the programmable SIMD vision chip. The memory architecture consists of 8 × 8 local memory cells, among which each 8 static latches in the master stage share one dynamic latch in the slave stage. The local memory performs single bit read and write in each clock cycle, and the compact area of 14.33 μm2/bit increases the integration level of the processor. A prototype chip with 64 × 64 processing units has been manufactured in 0.18 μm CMOS technology. Five types of local memory architecture have been designed, and an 8-bit input data buffer based on dedicated latch structures has been designed as the input data buffer for each processing unit. Test results show that the presented structure is suitable for real-time computer vision applications such as the edge detection at the speed of 1000 fps.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811928
Hanbin Hu, G. Shi, Yan Zhu
Symbolic methods for analog circuit analysis and modeling have been well studied. However, little is known on how to create symbolic models incrementally while a circuit topology is being modified. This paper proposes an incremental symbolic construction method applicable to incremental circuit topology change based on a previously developed data structure called GPDD (graph-pair decision diagram). An incremental GPDD algorithm (iGPDD) is proposed. It is demonstrated experimentally that with proper symbol ordering the iGPDD method outperforms the restarted GPDD construction method.
{"title":"Incremental symbolic construction for topological modeling of analog circuits","authors":"Hanbin Hu, G. Shi, Yan Zhu","doi":"10.1109/ASICON.2013.6811928","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811928","url":null,"abstract":"Symbolic methods for analog circuit analysis and modeling have been well studied. However, little is known on how to create symbolic models incrementally while a circuit topology is being modified. This paper proposes an incremental symbolic construction method applicable to incremental circuit topology change based on a previously developed data structure called GPDD (graph-pair decision diagram). An incremental GPDD algorithm (iGPDD) is proposed. It is demonstrated experimentally that with proper symbol ordering the iGPDD method outperforms the restarted GPDD construction method.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122087461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an efficient implementation for 3780-point FFT on multi-core processors, which makes full use of the parallelism of FFT application and multi-core system. Experiment results demonstrate that multi-core 3780-point FFT implementation not only achieves a speedup ratio of 6.475 over single core implementation but also maintains a great flexibility compared with ASIC implement.
{"title":"Efficient implementation of 3780-point FFT on a 16-core processor","authors":"Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng","doi":"10.1109/ASICON.2013.6811851","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811851","url":null,"abstract":"The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an efficient implementation for 3780-point FFT on multi-core processors, which makes full use of the parallelism of FFT application and multi-core system. Experiment results demonstrate that multi-core 3780-point FFT implementation not only achieves a speedup ratio of 6.475 over single core implementation but also maintains a great flexibility compared with ASIC implement.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122108273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811874
Zitao Shi, Xin Wang, Albert Z. H. Wang, Yuhua Cheng
Electrostatic discharge (ESD) protection is required for all ICs. However, ESD protection inevitably introduce parasitic effects that will negatively affect IC performance, especially for parasitic-sensitive radio-frequency (RF) ICs. This paper reports design optimization of a 2.4GHz power amplifier (PA) circuit with 5kB full-chip ESD protection designed in an 180nm commercial RFCMOS technology. The PA design splits confirm that even an optimized ESD protection structure will affect PA circuit performance, which can be substantially recovered by careful PA-ESD co-design consideration.
{"title":"A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique","authors":"Zitao Shi, Xin Wang, Albert Z. H. Wang, Yuhua Cheng","doi":"10.1109/ASICON.2013.6811874","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811874","url":null,"abstract":"Electrostatic discharge (ESD) protection is required for all ICs. However, ESD protection inevitably introduce parasitic effects that will negatively affect IC performance, especially for parasitic-sensitive radio-frequency (RF) ICs. This paper reports design optimization of a 2.4GHz power amplifier (PA) circuit with 5kB full-chip ESD protection designed in an 180nm commercial RFCMOS technology. The PA design splits confirm that even an optimized ESD protection structure will affect PA circuit performance, which can be substantially recovered by careful PA-ESD co-design consideration.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"28 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131893574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811983
Yuan Xu, Haodong Yao, Liwei Gong, Mingcheng Zhu, Robert K. F. Teng
This paper presents a real-time stereo video processing system based on FPGA. The system takes rectification and histogram equalization as its pre-processing, and the depth detection of this system is using generalized census transform and block matching method. With the help of on-line generated projected pattern by the pattern controller inside FPGA, this system can be used in various environments. The median filter is used as the post-processing step of depth map. In comparison to the software solution method, this system takes the advantage of the parallel nature of FPGA and got higher speed in generating the depth map. Therefore, it can be applied to the applications demanded for better performance.
{"title":"A FPGA real-time stereo vision system with luminance control and projected pattern","authors":"Yuan Xu, Haodong Yao, Liwei Gong, Mingcheng Zhu, Robert K. F. Teng","doi":"10.1109/ASICON.2013.6811983","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811983","url":null,"abstract":"This paper presents a real-time stereo video processing system based on FPGA. The system takes rectification and histogram equalization as its pre-processing, and the depth detection of this system is using generalized census transform and block matching method. With the help of on-line generated projected pattern by the pattern controller inside FPGA, this system can be used in various environments. The median filter is used as the post-processing step of depth map. In comparison to the software solution method, this system takes the advantage of the parallel nature of FPGA and got higher speed in generating the depth map. Therefore, it can be applied to the applications demanded for better performance.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811825
Hanyang Xu, Jinmei Lai
To meet the increasing computational requirements in Field Programmable Gate Array (FPGA) devices, high performance DSP core is needed to make up the disadvantage of traditional Configurable Logic Blocks (CLB) in computing. This paper presents a novel DSP architecture with high throughput capability. In Arithmetic Logical Unit (ALU), we implement a 6-stage pipelined multiplier to enhance data throughput, and an adder which supports the Single Instruction Multiple Data (SIMD) feature to provide data level parallelism. A cascade carry signal is implemented in control logic to avoid overflow error. Performance of the designed DSP core is evaluated against the XtremeDSP core embedded in Xilinx FPGA devices. Comparison result shows 2x higher performance than the XtremeDSP in average.
{"title":"A high throughput FPGA embedded DSP architecture design","authors":"Hanyang Xu, Jinmei Lai","doi":"10.1109/ASICON.2013.6811825","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811825","url":null,"abstract":"To meet the increasing computational requirements in Field Programmable Gate Array (FPGA) devices, high performance DSP core is needed to make up the disadvantage of traditional Configurable Logic Blocks (CLB) in computing. This paper presents a novel DSP architecture with high throughput capability. In Arithmetic Logical Unit (ALU), we implement a 6-stage pipelined multiplier to enhance data throughput, and an adder which supports the Single Instruction Multiple Data (SIMD) feature to provide data level parallelism. A cascade carry signal is implemented in control logic to avoid overflow error. Performance of the designed DSP core is evaluated against the XtremeDSP core embedded in Xilinx FPGA devices. Comparison result shows 2x higher performance than the XtremeDSP in average.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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