Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507796
L. Thomas, H. Kow, Selvam Palasundram
The tungsten-rhenium (WRe) 3mil cantilever probe is widely used in wafer probe at ON Semiconductors. The maximum current that can be supplied to a DUT is restricted by the current capacity of the probe needles. A typical 3 mil tip probe can carry 2 - 3 Amps at a short burst current (I short) for a <;10 ms pulse time. Probing at a higher current level with minimal number of probes can cause current over crowding at probe tip which produces excessive heat due to electric charge and contact resistance. This heat can melt surface material and contaminant which can attach to the probe tip causing it to be deformed thus increasing resistance and temperature at the contact point. Accordingly more heat is generated by this causing the contaminant at probe tip to be further oxidized producing an insulating layer between DUT and probe. This results in spark occurrence during high current testing which may cause damage to the device. This paper describes the experiments carried out to guarantee the appropriate pulsed current level that can be carried through a single 3 mil tip probe without causing the probe tip to melt, get oxidized and generate sparks which could lead to devices damage due to EOS. Two MOSFET devices with current ratings of 2.0 Amps and 2.6 Amps respectively were used for this evaluation to determine the allowable operating pulsed current a probe can withstand. A Total of 85 K dies were probed, assembled and final tested. The test fallouts that were analyzed did not show any indication of an EOS signature on die cause by probe needles.
{"title":"Current capacity evaluation of a cantilever probe","authors":"L. Thomas, H. Kow, Selvam Palasundram","doi":"10.1109/IEMT.2008.5507796","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507796","url":null,"abstract":"The tungsten-rhenium (WRe) 3mil cantilever probe is widely used in wafer probe at ON Semiconductors. The maximum current that can be supplied to a DUT is restricted by the current capacity of the probe needles. A typical 3 mil tip probe can carry 2 - 3 Amps at a short burst current (I short) for a <;10 ms pulse time. Probing at a higher current level with minimal number of probes can cause current over crowding at probe tip which produces excessive heat due to electric charge and contact resistance. This heat can melt surface material and contaminant which can attach to the probe tip causing it to be deformed thus increasing resistance and temperature at the contact point. Accordingly more heat is generated by this causing the contaminant at probe tip to be further oxidized producing an insulating layer between DUT and probe. This results in spark occurrence during high current testing which may cause damage to the device. This paper describes the experiments carried out to guarantee the appropriate pulsed current level that can be carried through a single 3 mil tip probe without causing the probe tip to melt, get oxidized and generate sparks which could lead to devices damage due to EOS. Two MOSFET devices with current ratings of 2.0 Amps and 2.6 Amps respectively were used for this evaluation to determine the allowable operating pulsed current a probe can withstand. A Total of 85 K dies were probed, assembled and final tested. The test fallouts that were analyzed did not show any indication of an EOS signature on die cause by probe needles.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115916175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507797
I. Chin, Shaw Fong Wong, P. Malatkar, R. Canham
This paper presents a unified mechanical fatigue assessment methodology that characterizes and predicts the fatigue life performance of electronic components. It involves establishing the relationship between a solder ball damage metric and the fatigue cycles-to-failure. With the proposal of board strain as a metric, single BGA component test boards are used to produce a fatigue characterization curve - the E-N curve. The methodology was initially established using high cycle fatigue but later extended to the lower cycle fatigue region to give a complete picture of the characteristics. The methodology has been validated by predicting fatigue failure of a system board under random vibration using the rainflow-counting algorithm and Palmgren-Miner's damage accumulation. Discussion on board design implications and features to improve fatigue performance are presented. Furthermore, a case study with the methodology used to assess the mechanical integrity risk of two mobile devices is shared. The sensitivity of the methodology towards various board and package attributes is also demonstrated.
{"title":"A mechanical fatigue assessment methodology to study solder joint reliability","authors":"I. Chin, Shaw Fong Wong, P. Malatkar, R. Canham","doi":"10.1109/IEMT.2008.5507797","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507797","url":null,"abstract":"This paper presents a unified mechanical fatigue assessment methodology that characterizes and predicts the fatigue life performance of electronic components. It involves establishing the relationship between a solder ball damage metric and the fatigue cycles-to-failure. With the proposal of board strain as a metric, single BGA component test boards are used to produce a fatigue characterization curve - the E-N curve. The methodology was initially established using high cycle fatigue but later extended to the lower cycle fatigue region to give a complete picture of the characteristics. The methodology has been validated by predicting fatigue failure of a system board under random vibration using the rainflow-counting algorithm and Palmgren-Miner's damage accumulation. Discussion on board design implications and features to improve fatigue performance are presented. Furthermore, a case study with the methodology used to assess the mechanical integrity risk of two mobile devices is shared. The sensitivity of the methodology towards various board and package attributes is also demonstrated.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"100 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116322174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507798
W. L. Tan, K. Y. Chew, N. M. Hirmizi, M. A. Abu Bakar, J. Ismail, L. C. Sim, Azmah
The study on the influence of solvent environments on the Cu2O particles preparation via aqueous to organic phase transfer technique is described. In aqueous, the morphologies of the as-formed particles are of whisker-like or ellipsoidal shape dependent on the amount of CTAB used. At lower concentration of CTAB (r=2.7), Cu2O particles tend to form bundle of fine needle-like structures with an average diameter of 14.1±4.3 nm. Upon phase transfer process, transformation of Cu2O morphology occurred. Two organic solvents namely chloroform and toluene is studied. Chloroform with higher dielectric constant and dipole moment exert better particle-solvent interaction thus give better particle dispersion as compared to toluene. Addition of 10% v/v epoxy in the organic solvent further affects the particles morphology. Spherical particles as small as 8.1 ± 2.1 nm are obtained for Cu2O particles transferred into the 10%v/v epoxy/chloroform. Better solvation of epoxy resin in chloroform makes it a better stabilizer thus protecting the particles from agglomeration and secondary growth.
{"title":"Solvent effect on the morphology of copper (I) oxide: A fundamental study towards copper (I) oxide-epoxy composites","authors":"W. L. Tan, K. Y. Chew, N. M. Hirmizi, M. A. Abu Bakar, J. Ismail, L. C. Sim, Azmah","doi":"10.1109/IEMT.2008.5507798","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507798","url":null,"abstract":"The study on the influence of solvent environments on the Cu2O particles preparation via aqueous to organic phase transfer technique is described. In aqueous, the morphologies of the as-formed particles are of whisker-like or ellipsoidal shape dependent on the amount of CTAB used. At lower concentration of CTAB (r=2.7), Cu2O particles tend to form bundle of fine needle-like structures with an average diameter of 14.1±4.3 nm. Upon phase transfer process, transformation of Cu2O morphology occurred. Two organic solvents namely chloroform and toluene is studied. Chloroform with higher dielectric constant and dipole moment exert better particle-solvent interaction thus give better particle dispersion as compared to toluene. Addition of 10% v/v epoxy in the organic solvent further affects the particles morphology. Spherical particles as small as 8.1 ± 2.1 nm are obtained for Cu2O particles transferred into the 10%v/v epoxy/chloroform. Better solvation of epoxy resin in chloroform makes it a better stabilizer thus protecting the particles from agglomeration and secondary growth.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122154914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507850
N. Annamalai, Choo Pak Kee, K. S. Yeoh, W. Ismail
Productivity and cost savings are known key challenges in this competitive semiconductor industries. It has become more complex with the introduction of a new equipment, NGSHBI (Next Generation Self Heat Burn-In) integration into Test Operation. NGSHBI module was developed and deployed to support the product for Burn In requirement for chipset product. Moving into high product mix environment, the team encountered complexities with different package size design interception. With this multi form factor requirement, the design team provided fungible kit solution with new actuation bar design. The solution was not effective and also not factory friendly. This paper will outline how the key unproductive line item has been narrowed and solved through innovative solution
{"title":"NGSHBI throughput optimization through innovative solution","authors":"N. Annamalai, Choo Pak Kee, K. S. Yeoh, W. Ismail","doi":"10.1109/IEMT.2008.5507850","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507850","url":null,"abstract":"Productivity and cost savings are known key challenges in this competitive semiconductor industries. It has become more complex with the introduction of a new equipment, NGSHBI (Next Generation Self Heat Burn-In) integration into Test Operation. NGSHBI module was developed and deployed to support the product for Burn In requirement for chipset product. Moving into high product mix environment, the team encountered complexities with different package size design interception. With this multi form factor requirement, the design team provided fungible kit solution with new actuation bar design. The solution was not effective and also not factory friendly. This paper will outline how the key unproductive line item has been narrowed and solved through innovative solution","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"97 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120911362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507868
Yoon-Peng Yee
Wafer fabrication technology has overcome many challenges and achieved small pitch at high current density nowadays, hence durable and sustainable probing tools are essential. Since good qualification process determines good tools to use, the scope of study in probe card fabrication has to be comprehensive enough to cover all that needed to be covered in forming an effective wafer probing characteristics. National Semiconductor has conducted a series of experiments looking into probing characteristics over a period of time. From the experimental results, conclusions were reached to setup guidelines to be applied to probe card fabrication with correct probe pressure.
{"title":"Important qualification process to wafer probing","authors":"Yoon-Peng Yee","doi":"10.1109/IEMT.2008.5507868","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507868","url":null,"abstract":"Wafer fabrication technology has overcome many challenges and achieved small pitch at high current density nowadays, hence durable and sustainable probing tools are essential. Since good qualification process determines good tools to use, the scope of study in probe card fabrication has to be comprehensive enough to cover all that needed to be covered in forming an effective wafer probing characteristics. National Semiconductor has conducted a series of experiments looking into probing characteristics over a period of time. From the experimental results, conclusions were reached to setup guidelines to be applied to probe card fabrication with correct probe pressure.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129121471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507776
T. Jang, Won-Su Yun, Soohyun Kim, Kyung-Soo Kim
In this paper, we develop the novel ultrasonic bonding method for mounting LCD driver IC which has a number of small bumps with high pin-density. Since the materials for bumps and pads are different metals, the an-isotropic conductive film (ACF) is used for adhesion. The conventional methods based on the thermal energy under pressure suffer from the high failure rate at high temperature process and, in particular, the low productivity due to the long bonding process time. To avoid these, the thermo-compression ultrasonic approach is newly proposed, and, validated by experiments. The experimental results show that lower values of bonding pressure and temperature than recommended by the ACF specification can be adopted for reliable bonding, which proves the feasibility of the ultrasonic bonding technique. In addition, we address a new concept of horn design for high precision bonding. Since the proposed method is utilizing the mechanical vibration, the misalignment between bumps and pads may be the major issue. To solve this, the active controllable horn design is further discussed.
{"title":"Using ultrasonic energy for reducing ACF bonding process time","authors":"T. Jang, Won-Su Yun, Soohyun Kim, Kyung-Soo Kim","doi":"10.1109/IEMT.2008.5507776","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507776","url":null,"abstract":"In this paper, we develop the novel ultrasonic bonding method for mounting LCD driver IC which has a number of small bumps with high pin-density. Since the materials for bumps and pads are different metals, the an-isotropic conductive film (ACF) is used for adhesion. The conventional methods based on the thermal energy under pressure suffer from the high failure rate at high temperature process and, in particular, the low productivity due to the long bonding process time. To avoid these, the thermo-compression ultrasonic approach is newly proposed, and, validated by experiments. The experimental results show that lower values of bonding pressure and temperature than recommended by the ACF specification can be adopted for reliable bonding, which proves the feasibility of the ultrasonic bonding technique. In addition, we address a new concept of horn design for high precision bonding. Since the proposed method is utilizing the mechanical vibration, the misalignment between bumps and pads may be the major issue. To solve this, the active controllable horn design is further discussed.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128172824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507892
H. Habib, Ow Yong Soon Tatt
Attaching small component size of 8 Terminal Capacitors onto fully populated pin of PGA substrate has become very challenging during assembly process. A methodology was developed to precisely control the 50 um high accuracy of capacitor placement prior to solder paste reflow. Four corners holding top clamp on chip shooter machine was used to ensure the sitting of all singulated substrates onto respective cavity of carrier are firmed hold. Single piece nozzle design made of ceramic for capacitor pickup has proven to effectively holding the capacitor during pickup, transporting and placement without damaging the nozzle tip which can cause misaligned capacitor during placement. Besides, implementation of interval blow-off feature before each capacitor pickup has managed to eliminate dust clogging in the nozzle. Additional periodical placement accuracy checking for calibration on precise singulated glass plate per carrier cavity matrix was carried out to control equipment capability in achieving 50 um placement accuracy at all time.
{"title":"Precise control of 8 terminal capacitor placement on fully populated PGA singulated substrate","authors":"H. Habib, Ow Yong Soon Tatt","doi":"10.1109/IEMT.2008.5507892","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507892","url":null,"abstract":"Attaching small component size of 8 Terminal Capacitors onto fully populated pin of PGA substrate has become very challenging during assembly process. A methodology was developed to precisely control the 50 um high accuracy of capacitor placement prior to solder paste reflow. Four corners holding top clamp on chip shooter machine was used to ensure the sitting of all singulated substrates onto respective cavity of carrier are firmed hold. Single piece nozzle design made of ceramic for capacitor pickup has proven to effectively holding the capacitor during pickup, transporting and placement without damaging the nozzle tip which can cause misaligned capacitor during placement. Besides, implementation of interval blow-off feature before each capacitor pickup has managed to eliminate dust clogging in the nozzle. Additional periodical placement accuracy checking for calibration on precise singulated glass plate per carrier cavity matrix was carried out to control equipment capability in achieving 50 um placement accuracy at all time.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128198219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507821
Tae Hoon Kim, J. Jeon, Y. P. Kwak, Tae Ho Kim, Yun Jung Lim, Jang Ho Park, Seogmoon Choi, Sung Yi
Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on smaller and lower cost package process. However, glass wafer which is substrate material of wafer level package for crystal unit device is difficult to make via by using novel method. The structure of wafer level crystal unit package for low cost and high performance is designed and optimized. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting or laser drilling and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The interconnection via process for wafer level crystal unit package with 2.0×1.6×0.45 mm3 size and results of electrical performance is evaluated.
{"title":"Interconnection via technology and wafer level package for crystal unit device","authors":"Tae Hoon Kim, J. Jeon, Y. P. Kwak, Tae Ho Kim, Yun Jung Lim, Jang Ho Park, Seogmoon Choi, Sung Yi","doi":"10.1109/IEMT.2008.5507821","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507821","url":null,"abstract":"Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on smaller and lower cost package process. However, glass wafer which is substrate material of wafer level package for crystal unit device is difficult to make via by using novel method. The structure of wafer level crystal unit package for low cost and high performance is designed and optimized. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting or laser drilling and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The interconnection via process for wafer level crystal unit package with 2.0×1.6×0.45 mm3 size and results of electrical performance is evaluated.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121471852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507820
Rusli Ibrahim, Au Yin Kheng, Y. Choi
Gold ball bonding remains to be the key technology in the assembly of semiconductor packaging. In response to the demand for higher I/O's and increased package functionality, the bond pad pitch (BPP) and bond pad opening (BPO) will subsequently decrease. This technology trend demands the use of finer wire diameters and provide good wire bonding process. However, wire bond reliability continues to be the most challenging area with ever finer pitch devices, particularly to meet automotive requirement. Non-stick on pad (NSOP) and insufficient intermetallic coverage (IMC) due to either wafer surface contaminants, wire bond process and material set are still the main issue in Low-K wire bonding technology. Decapsulation and wire pull after temperature cycling is another challenge that needs in depth focus. This paper specifically discusses various phenomenons of bondability, wafer variation and reliability issue towards meeting the automotive reliability requirements. Failure analysis results are also briefly discussed.
{"title":"The challenges in automotive Low-k fine pitch bonding","authors":"Rusli Ibrahim, Au Yin Kheng, Y. Choi","doi":"10.1109/IEMT.2008.5507820","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507820","url":null,"abstract":"Gold ball bonding remains to be the key technology in the assembly of semiconductor packaging. In response to the demand for higher I/O's and increased package functionality, the bond pad pitch (BPP) and bond pad opening (BPO) will subsequently decrease. This technology trend demands the use of finer wire diameters and provide good wire bonding process. However, wire bond reliability continues to be the most challenging area with ever finer pitch devices, particularly to meet automotive requirement. Non-stick on pad (NSOP) and insufficient intermetallic coverage (IMC) due to either wafer surface contaminants, wire bond process and material set are still the main issue in Low-K wire bonding technology. Decapsulation and wire pull after temperature cycling is another challenge that needs in depth focus. This paper specifically discusses various phenomenons of bondability, wafer variation and reliability issue towards meeting the automotive reliability requirements. Failure analysis results are also briefly discussed.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507843
S. Hian, A. M. Yassin, Y. S. Won
Anhydride hardener molding compound has been widely accepted as an encapsulation technology for high voltage application products. The roles of encapsulation materials extend beyond just encapsulating the device; these materials also provide heat dissipation and insulation between the device and the package that essentially affects the performance of the device while operating in the field. The recent more stringent electrical test requirement for high voltage application package raises a great challenge to the molding encapsulation technology especially those without using anhydride hardener in the formulation. Anhydride hardener is particularly attractive because of its known intrinsic superior electrical properties and high degree of cross-linking. In this paper, material properties analysis, moldability studies, electrical performance and reliability testing for several types of molding compounds such as anhydride hardener, crystalline filler, low stress Ortho Cresol Novolac (OCN), and Biphenyl/Phenolic molding encapsulations will be presented. The low stress OCN green molding compound was found to work exceptionally well with no significant degradation of electrical performance when compared to anhydride hardener molding compound. More importantly, the low stress OCN molding encapsulation is more cost-effective, provides excellent moldability, good delamination performance and possibly a more reliable package.
{"title":"Analysis and characterization of green compound material for high voltage application","authors":"S. Hian, A. M. Yassin, Y. S. Won","doi":"10.1109/IEMT.2008.5507843","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507843","url":null,"abstract":"Anhydride hardener molding compound has been widely accepted as an encapsulation technology for high voltage application products. The roles of encapsulation materials extend beyond just encapsulating the device; these materials also provide heat dissipation and insulation between the device and the package that essentially affects the performance of the device while operating in the field. The recent more stringent electrical test requirement for high voltage application package raises a great challenge to the molding encapsulation technology especially those without using anhydride hardener in the formulation. Anhydride hardener is particularly attractive because of its known intrinsic superior electrical properties and high degree of cross-linking. In this paper, material properties analysis, moldability studies, electrical performance and reliability testing for several types of molding compounds such as anhydride hardener, crystalline filler, low stress Ortho Cresol Novolac (OCN), and Biphenyl/Phenolic molding encapsulations will be presented. The low stress OCN green molding compound was found to work exceptionally well with no significant degradation of electrical performance when compared to anhydride hardener molding compound. More importantly, the low stress OCN molding encapsulation is more cost-effective, provides excellent moldability, good delamination performance and possibly a more reliable package.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131573166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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