Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507839
C. Foong, K. W. Shim, Min Ding
Mechanical stresses induced by the mismatch of coefficient of thermal expansion (CTE) among different materials are the major driving force of fracture failures in silicon dies of microelectronic packages. The stresses induced are concentrated at locations where different materials interfaced and geometrical singularities such as die corners and die edges. Stress analyses using finite element mechanical modeling demonstrated that the stresses close to the die corners are 30% ~ 80% higher compared to the inner regions of the die. In addition, cracks inside the bulk mold compound and interfacial delamination on top of the die have been found due to these high stresses. DEP (Die Edge Protection) epoxy, a low-stress high CTE polymeric material, has been used to cover the corners and edges of the die to reduce stress levels with the objective of eradicating failures associated with these stress singularities. It acts as a buffering medium to mechanically shield the die corners and edges from being in direct contact to the high modulus molding compound materials. The DEP coating is achieved by dispensing the liquid DEP epoxy outside the wire bonded die area and allowing the epoxy to creep up along the die corners and edges. The DEP dispense process takes place after wire bonding. In the subsequent molding process step, areas coated with DEP will be shielded from the mold compound. It was observed from experimental evaluations that the DEP coating managed to prevent die corners cracking and delamination. This paper examines the simulation of the DEP coating, and discusses the DEP process development required to implement such a scheme into high volume production.
{"title":"Modeling and process development of Die Edge Protection to alleviate thermo-mechanical stresses on silicon dies in PBGA packages","authors":"C. Foong, K. W. Shim, Min Ding","doi":"10.1109/IEMT.2008.5507839","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507839","url":null,"abstract":"Mechanical stresses induced by the mismatch of coefficient of thermal expansion (CTE) among different materials are the major driving force of fracture failures in silicon dies of microelectronic packages. The stresses induced are concentrated at locations where different materials interfaced and geometrical singularities such as die corners and die edges. Stress analyses using finite element mechanical modeling demonstrated that the stresses close to the die corners are 30% ~ 80% higher compared to the inner regions of the die. In addition, cracks inside the bulk mold compound and interfacial delamination on top of the die have been found due to these high stresses. DEP (Die Edge Protection) epoxy, a low-stress high CTE polymeric material, has been used to cover the corners and edges of the die to reduce stress levels with the objective of eradicating failures associated with these stress singularities. It acts as a buffering medium to mechanically shield the die corners and edges from being in direct contact to the high modulus molding compound materials. The DEP coating is achieved by dispensing the liquid DEP epoxy outside the wire bonded die area and allowing the epoxy to creep up along the die corners and edges. The DEP dispense process takes place after wire bonding. In the subsequent molding process step, areas coated with DEP will be shielded from the mold compound. It was observed from experimental evaluations that the DEP coating managed to prevent die corners cracking and delamination. This paper examines the simulation of the DEP coating, and discusses the DEP process development required to implement such a scheme into high volume production.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129955350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507879
S. Bhatta, T. Seetharam
A three dimensional study of air cooling from an array of heated blocks in a rectangular channel for a range of Reynolds number is presented. Heated blocks represent electronic modules mounted on horizontal circuit boards. Numerically obtained average heat transfer coefficients for the top surface of the heated modules are compared with experimentally obtained values, and it is found that there is a good agreement between the two at low Reynolds numbers. Further, circular cylinders, semi-circular cylinders, and semicircular cylindrical shells with length equal to the width of the channel are introduced as flow barriers in the domain separately to study the influence on heat transfer and pressure drop. These horizontal cylinders over each row of modules in cross flow augment heat transfer from the heated modules considerably. The heat transfer enhancement is found to be more dependent on the vertical position of the cylinders with respect to the modules than on the horizontal position. Air cooling is predicted to be augmented from the modules by shifting the cylinders closer to the heated modules up to a certain limiting distance, and beyond which the heat transfer decreases. Semicircular cylindrical shells prove more beneficial than any of the other two barriers for heat transfer enhancement from the modules. It is observed that the semicircular shells in cross flow result in lesser pressure drop when compared to semicircular cylinders, though the former produces maximum heat transfer from the modules.
{"title":"Air cooling augmentation in an array of heated modules by horizontal semicircular cylindrical shells as cross flow barriers","authors":"S. Bhatta, T. Seetharam","doi":"10.1109/IEMT.2008.5507879","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507879","url":null,"abstract":"A three dimensional study of air cooling from an array of heated blocks in a rectangular channel for a range of Reynolds number is presented. Heated blocks represent electronic modules mounted on horizontal circuit boards. Numerically obtained average heat transfer coefficients for the top surface of the heated modules are compared with experimentally obtained values, and it is found that there is a good agreement between the two at low Reynolds numbers. Further, circular cylinders, semi-circular cylinders, and semicircular cylindrical shells with length equal to the width of the channel are introduced as flow barriers in the domain separately to study the influence on heat transfer and pressure drop. These horizontal cylinders over each row of modules in cross flow augment heat transfer from the heated modules considerably. The heat transfer enhancement is found to be more dependent on the vertical position of the cylinders with respect to the modules than on the horizontal position. Air cooling is predicted to be augmented from the modules by shifting the cylinders closer to the heated modules up to a certain limiting distance, and beyond which the heat transfer decreases. Semicircular cylindrical shells prove more beneficial than any of the other two barriers for heat transfer enhancement from the modules. It is observed that the semicircular shells in cross flow result in lesser pressure drop when compared to semicircular cylinders, though the former produces maximum heat transfer from the modules.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131665031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507806
S. Das, A. Sharif
In this work, Ag micro-particles content in the range between 0-4.0 wt.% with Sn-Zn eutectic system, were examined in order to understand the effect of Ag addition on the microstructural and mechanical properties as well as the thermal behavior of the composite solders. The shear strengths and the interfacial reactions of Sn-Zn micro-composite eutectic solders with Au/Ni/Cu ball grid array (BGA) pad metallization were systematically investigated. The three distinct intermetallic compound (IMC) layers were formed at the solder interface of the Au/electrolytic Ni/Cu bond pad with Sn-Zn composite alloys. The more Ag particles added to the Sn-Zn solder, the more Ag-Zn compound formed to thicken the uppermost IMC layer. The dissoluted Ag-Zn IMCs formed in the bulk solder redeposited over the initially formed interfacial Au-Zn IMC layer, prevented the whole IMC layer lift-off from the pad surface. Cross-sectional studies of the interfaces were also conducted to correlate with the fracture surfaces.
{"title":"A study of Ag micro-particle reinforced Sn-Zn matrix composite solder","authors":"S. Das, A. Sharif","doi":"10.1109/IEMT.2008.5507806","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507806","url":null,"abstract":"In this work, Ag micro-particles content in the range between 0-4.0 wt.% with Sn-Zn eutectic system, were examined in order to understand the effect of Ag addition on the microstructural and mechanical properties as well as the thermal behavior of the composite solders. The shear strengths and the interfacial reactions of Sn-Zn micro-composite eutectic solders with Au/Ni/Cu ball grid array (BGA) pad metallization were systematically investigated. The three distinct intermetallic compound (IMC) layers were formed at the solder interface of the Au/electrolytic Ni/Cu bond pad with Sn-Zn composite alloys. The more Ag particles added to the Sn-Zn solder, the more Ag-Zn compound formed to thicken the uppermost IMC layer. The dissoluted Ag-Zn IMCs formed in the bulk solder redeposited over the initially formed interfacial Au-Zn IMC layer, prevented the whole IMC layer lift-off from the pad surface. Cross-sectional studies of the interfaces were also conducted to correlate with the fracture surfaces.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134398131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507853
A. Torbati-Sarraf, R. Mahmudi, A. Geranmayeh, A. Baradaran-Goorani
Creep behavior of the tin-based lead-free Sn-3.8Ag and Sn-3.8Ag-0.7Cu alloys together with Sn-37Pb, as the material for comparison, was studied by impression and indentation creep testing at room temperature. Stress exponent values in the range 5.1 to 9.7, obtained by the two methods, were in good agreement with each other and with those determined by room-temperature creep testing of the same materials reported in the literature. Among all tested materials, as indicated by their steady-state creep rates, Sn-3.8Ag-0.7Cu showed the highest creep resistance followed by Sn-3.8Ag and Sn-Pb. The formation of Ag3Sn and Cu6Sn5 intermetallics in Sn-3.8Ag-0.7Cu, and Ag3Sn in Sn-3.8Ag are the main cause of improved creep resistance of the alloys over the eutectic Sn-Pb alloy.
{"title":"Creep of lead-free Sn-3.8Ag and Sn-3.8Ag-0.7Cu solder alloy as replacements of Sn-Pb solder used in microelectronic packaging","authors":"A. Torbati-Sarraf, R. Mahmudi, A. Geranmayeh, A. Baradaran-Goorani","doi":"10.1109/IEMT.2008.5507853","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507853","url":null,"abstract":"Creep behavior of the tin-based lead-free Sn-3.8Ag and Sn-3.8Ag-0.7Cu alloys together with Sn-37Pb, as the material for comparison, was studied by impression and indentation creep testing at room temperature. Stress exponent values in the range 5.1 to 9.7, obtained by the two methods, were in good agreement with each other and with those determined by room-temperature creep testing of the same materials reported in the literature. Among all tested materials, as indicated by their steady-state creep rates, Sn-3.8Ag-0.7Cu showed the highest creep resistance followed by Sn-3.8Ag and Sn-Pb. The formation of Ag3Sn and Cu6Sn5 intermetallics in Sn-3.8Ag-0.7Cu, and Ag3Sn in Sn-3.8Ag are the main cause of improved creep resistance of the alloys over the eutectic Sn-Pb alloy.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132141370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507778
T. Chai, J. Tan, M. Sivakumar, J. Premkumar, James Song, Y. Wong
The quest to replace wire material from gold (Au) to Copper (Cu) in wire bonding interconnect has been in the industry since few decades. As the Cu wire bonding manufacturing process matures, the idea of substituting Al wedge bond with Cu ball bond is mooted. Such substitution could potentially reap benefits of lower machine cost of ownership and better utilization of silicon real estate. It also comes with better conductivity, slower intermetallic growth and possibly cheaper material price. However, the associated challenges such as hardness and oxidation could be overwhelming and requires a careful assessment. The objective of this study is to provide insight of the 6.0 mils Cu wire bonding process. 6.0 mils Cu wire is the key candidate in this Al - Cu wire substitution idea. Bonding interaction of Cu wire, chip & lead are studied experimentally.
{"title":"Super heavy 6.0 mils Cu wire ball bonding","authors":"T. Chai, J. Tan, M. Sivakumar, J. Premkumar, James Song, Y. Wong","doi":"10.1109/IEMT.2008.5507778","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507778","url":null,"abstract":"The quest to replace wire material from gold (Au) to Copper (Cu) in wire bonding interconnect has been in the industry since few decades. As the Cu wire bonding manufacturing process matures, the idea of substituting Al wedge bond with Cu ball bond is mooted. Such substitution could potentially reap benefits of lower machine cost of ownership and better utilization of silicon real estate. It also comes with better conductivity, slower intermetallic growth and possibly cheaper material price. However, the associated challenges such as hardness and oxidation could be overwhelming and requires a careful assessment. The objective of this study is to provide insight of the 6.0 mils Cu wire bonding process. 6.0 mils Cu wire is the key candidate in this Al - Cu wire substitution idea. Bonding interaction of Cu wire, chip & lead are studied experimentally.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116209270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507893
I. H. A. Razak, S. Kamaruddin, I. Azid
Sophisticated and advanced technologies adopted in recent semiconductor industries have grown rapidly to some degree. The complex hardware and software embedded with automation control system and other technological advancement require the need for higher levels of maintenance system. In such technological advancements, one must consider that innovations also require humans in the maintenance system to acquire new skills and knowledge. This however may induce additional probable for human error; which is known as a primary contributor to equipment and plant failures. This paper reviewed several general approaches to the study of human error and the characteristics of work in various industries as a foundation for describing the nature, incidence, and consequences of human error in the maintenance area. The Human Reliability Model (HRrM) which integrates qualitative and quantitative assessments is proposed as a methodology to quantify maintenance worker's reliability; or probability the worker successfully accomplishes a maintenance task without performing any erroneous activities. A set of individual factors which may influence to error occurrence is considered as the model variables in evaluating individual maintenance workers. The HRrM model is then been verified and applied in a case study conducted in an electronic packaging industry. The intention of this model is to assist the organization in evaluating and monitoring the maintenance worker's performance in terms of their reliability and thus improving the effectiveness of organization's maintenance system.
{"title":"Development of Human Reliability Model for Evaluating Maintenance Workforce Reliability: A Case Study in Electronic Packaging Industry","authors":"I. H. A. Razak, S. Kamaruddin, I. Azid","doi":"10.1109/IEMT.2008.5507893","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507893","url":null,"abstract":"Sophisticated and advanced technologies adopted in recent semiconductor industries have grown rapidly to some degree. The complex hardware and software embedded with automation control system and other technological advancement require the need for higher levels of maintenance system. In such technological advancements, one must consider that innovations also require humans in the maintenance system to acquire new skills and knowledge. This however may induce additional probable for human error; which is known as a primary contributor to equipment and plant failures. This paper reviewed several general approaches to the study of human error and the characteristics of work in various industries as a foundation for describing the nature, incidence, and consequences of human error in the maintenance area. The Human Reliability Model (HRrM) which integrates qualitative and quantitative assessments is proposed as a methodology to quantify maintenance worker's reliability; or probability the worker successfully accomplishes a maintenance task without performing any erroneous activities. A set of individual factors which may influence to error occurrence is considered as the model variables in evaluating individual maintenance workers. The HRrM model is then been verified and applied in a case study conducted in an electronic packaging industry. The intention of this model is to assist the organization in evaluating and monitoring the maintenance worker's performance in terms of their reliability and thus improving the effectiveness of organization's maintenance system.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"51 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507781
S. H. Kim, H. Park, J. Moon
Recently Gold price is increased much higher. So Copper wire as low cost solution, is highlighted in various package groups. And some packages having low-pin count of thick size wire, have already been succeeded in mass production using Copper wire. If high Gold price is being kept continuously, speed of conversion for Copper wire will be accelerated.
{"title":"Optimized conditions to make stable free air ball(FAB) for copper bonding wire","authors":"S. H. Kim, H. Park, J. Moon","doi":"10.1109/IEMT.2008.5507781","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507781","url":null,"abstract":"Recently Gold price is increased much higher. So Copper wire as low cost solution, is highlighted in various package groups. And some packages having low-pin count of thick size wire, have already been succeeded in mass production using Copper wire. If high Gold price is being kept continuously, speed of conversion for Copper wire will be accelerated.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133569963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507849
J. Lee, Jungwon Lee, Y. Chung, Seogmoon Choi, Jongin Ryu, B. Jang
Work on the Pulse Laser Deposition (PLD) equipment is purely for research and development at Samsung Electro-Mechanics when it takes 30 minutes to complete the experiment to grow a dielectric thin film on Cu plated pieces of Si wafer. At SEMCO, low temperatures around 180°C is essential for thin film growth on CCL since CCL melts around 200°C. High dielectric thin film performance is also paramount in terms of reducing costs, eliminating SMT passive components and decreasing CCL thickness. It is why CCTO is being investigated since it has very high dielectric performance without any parasitic ferroelectric hysteresis effect. As a result, our investigation shows it is possible to have a dielectric constant of 128 with a loss tangent of 0.15 at a measuring frequency of 1 MHz. PLD conditions require a temperature of 180°C, O2 pressure of 40mTorr, pulsing frequency of 10Hz, and power density of 18mJ/mm2.
{"title":"“CCTO thin film growth on a Cu plated Si wafer by pulse laser deposition at low temperatures”","authors":"J. Lee, Jungwon Lee, Y. Chung, Seogmoon Choi, Jongin Ryu, B. Jang","doi":"10.1109/IEMT.2008.5507849","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507849","url":null,"abstract":"Work on the Pulse Laser Deposition (PLD) equipment is purely for research and development at Samsung Electro-Mechanics when it takes 30 minutes to complete the experiment to grow a dielectric thin film on Cu plated pieces of Si wafer. At SEMCO, low temperatures around 180°C is essential for thin film growth on CCL since CCL melts around 200°C. High dielectric thin film performance is also paramount in terms of reducing costs, eliminating SMT passive components and decreasing CCL thickness. It is why CCTO is being investigated since it has very high dielectric performance without any parasitic ferroelectric hysteresis effect. As a result, our investigation shows it is possible to have a dielectric constant of 128 with a loss tangent of 0.15 at a measuring frequency of 1 MHz. PLD conditions require a temperature of 180°C, O2 pressure of 40mTorr, pulsing frequency of 10Hz, and power density of 18mJ/mm2.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507848
H. T. Wang, Y. Poh
Silver filled epoxy is widely used as interconnect of chip to leadframe. This paper introduces material analysis method to study effect of epoxy glue properties to delamination and wire bondability in Dual Flat Non Leaded (DFN) package. Five epoxy glues were characterized using TMA, DMA, TGA. DSC, Moisture Absorption Test and Die Shear Test. Epoxy glues were assembled into 5 × 6 × 1mm DFN package and subjected to Moisture Sensitivity Level 3. thermal cycling and autoclave test. Material analysis result is reflected into experimental verification. CTE mismatch between epoxy glue with molding compound, chip, and leadframe is identified as the primary factor causing epoxy glue delamination. High elastic modulus 1034MPa at 260°C is preferred to resist solder reflow stress. Interfacial adhesion degradation at high temperature is another key factor; investigation revealed with chip size 2mm2 high shear strength as 1.98 kg and cohesive mode with 40% epoxy remnants able to prevent epoxy glue delamination. Result showed that at wire bond temperature of 220°C, minimum elastic modulus required for consistent wire bondability is 101MPa base on chip size of 2mm2.
{"title":"An analysis on the properties of epoxy based die attach material and the effect to delamination and wire bondability","authors":"H. T. Wang, Y. Poh","doi":"10.1109/IEMT.2008.5507848","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507848","url":null,"abstract":"Silver filled epoxy is widely used as interconnect of chip to leadframe. This paper introduces material analysis method to study effect of epoxy glue properties to delamination and wire bondability in Dual Flat Non Leaded (DFN) package. Five epoxy glues were characterized using TMA, DMA, TGA. DSC, Moisture Absorption Test and Die Shear Test. Epoxy glues were assembled into 5 × 6 × 1mm DFN package and subjected to Moisture Sensitivity Level 3. thermal cycling and autoclave test. Material analysis result is reflected into experimental verification. CTE mismatch between epoxy glue with molding compound, chip, and leadframe is identified as the primary factor causing epoxy glue delamination. High elastic modulus 1034MPa at 260°C is preferred to resist solder reflow stress. Interfacial adhesion degradation at high temperature is another key factor; investigation revealed with chip size 2mm2 high shear strength as 1.98 kg and cohesive mode with 40% epoxy remnants able to prevent epoxy glue delamination. Result showed that at wire bond temperature of 220°C, minimum elastic modulus required for consistent wire bondability is 101MPa base on chip size of 2mm2.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124982448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/iemt.2008.5507807
W. Y. Huang, E. Chen, J. Lai, Yu Po Wang
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump. In this study a 15mm×15mm Face-to-Face Stacked-die Thin and Fine-pitch BGA (F2F-STFBGA) package was adopted for Finite Element Method (FEM) analysis. The evaluations focused on low-k stress, bump stress and pad peeling stress of different Micro Bump structures. Firstly two different face to face interconnection levels of chip to chip and chip to substrate (EHS-FCBGA) were investigated. Secondly four different interconnection bump structures of common bump structure (solder bump), Cu pillar for both top and bottom bump, Cu pillar for both top bump and Au for bottom bump, Au for top bump and Cu pillar for bottom bump were compared. In conclusion a design guideline of F2F-S2TFBGA package was recommended with considerations of Micro Bump structure, material, and package geometry.
{"title":"Stress evaluations in Micro Bump structures of FCBGA","authors":"W. Y. Huang, E. Chen, J. Lai, Yu Po Wang","doi":"10.1109/iemt.2008.5507807","DOIUrl":"https://doi.org/10.1109/iemt.2008.5507807","url":null,"abstract":"System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump. In this study a 15mm×15mm Face-to-Face Stacked-die Thin and Fine-pitch BGA (F2F-STFBGA) package was adopted for Finite Element Method (FEM) analysis. The evaluations focused on low-k stress, bump stress and pad peeling stress of different Micro Bump structures. Firstly two different face to face interconnection levels of chip to chip and chip to substrate (EHS-FCBGA) were investigated. Secondly four different interconnection bump structures of common bump structure (solder bump), Cu pillar for both top and bottom bump, Cu pillar for both top bump and Au for bottom bump, Au for top bump and Cu pillar for bottom bump were compared. In conclusion a design guideline of F2F-S2TFBGA package was recommended with considerations of Micro Bump structure, material, and package geometry.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125141426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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