Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507826
Chee Kan Lee, R. Derek, W. K. Loh, Hui Ping Ng, K. W. Lau
In High Volume Manufacturing (HVM) environment, maintaining assembly process stability is the outmost priority to meet quality and reliability requirement. In recent years of transitioning to Lead Free (LF) solder alloy, tighter ball pitch and increasing hostile use condition, thus the expectation of better and tighter control in Solder Joint Reliability (SJR) is increasing. The SJR concern is not a new phenomenon, numerous research works are published to share the learning and options to resolve SJR issues including introduction of new solder alloy, Stress Compensation Layer (SCL), alternate surface finish and etc. The implementations of LF solder alloy have been found to be more at risk to brittle failure in the intermetallic layers. In view of the Flip Chip (FC) design requirement expands and evolves, it is important that the test metrology should likewise continue to evolve. The High Speed Ball Shear (HSBS) and conventional Cold Ball Pull (CBP) results are compared and discussed in term of the ability to predict susceptibility to interfacial failures due to assembly process changes for Flip Chip Ball Grid Array (FCBGA) packages. Examples of assembly process studies are Ball Attach (BA) reflow profile, effect of multiple reflows on the growth of intermetallic that affects the strength of solder joint performance, substrate plating process skew and etc. In additional, detailed microscopic analysis on post HSBS was executed to study the distribution and thickness of Intermetallic compound (IMC) layer on solder pad for FCBGA packages. The result showed that a higher sensitivity was demonstrated by HSBS as compare to CBP in assembly process shifts detection. This paper also covers the course of the development of fracture energy metric and implementations of HSBS metrology into HVM environment as an in line BA process monitoring system. Lastly, a comparison of the facture energy between ENIG and improve surface plating is provided to show the margin gained by improve surface plating technologies.
{"title":"The next generation of quick turn method for interfacial strength testing: High Speed Ball Shear","authors":"Chee Kan Lee, R. Derek, W. K. Loh, Hui Ping Ng, K. W. Lau","doi":"10.1109/IEMT.2008.5507826","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507826","url":null,"abstract":"In High Volume Manufacturing (HVM) environment, maintaining assembly process stability is the outmost priority to meet quality and reliability requirement. In recent years of transitioning to Lead Free (LF) solder alloy, tighter ball pitch and increasing hostile use condition, thus the expectation of better and tighter control in Solder Joint Reliability (SJR) is increasing. The SJR concern is not a new phenomenon, numerous research works are published to share the learning and options to resolve SJR issues including introduction of new solder alloy, Stress Compensation Layer (SCL), alternate surface finish and etc. The implementations of LF solder alloy have been found to be more at risk to brittle failure in the intermetallic layers. In view of the Flip Chip (FC) design requirement expands and evolves, it is important that the test metrology should likewise continue to evolve. The High Speed Ball Shear (HSBS) and conventional Cold Ball Pull (CBP) results are compared and discussed in term of the ability to predict susceptibility to interfacial failures due to assembly process changes for Flip Chip Ball Grid Array (FCBGA) packages. Examples of assembly process studies are Ball Attach (BA) reflow profile, effect of multiple reflows on the growth of intermetallic that affects the strength of solder joint performance, substrate plating process skew and etc. In additional, detailed microscopic analysis on post HSBS was executed to study the distribution and thickness of Intermetallic compound (IMC) layer on solder pad for FCBGA packages. The result showed that a higher sensitivity was demonstrated by HSBS as compare to CBP in assembly process shifts detection. This paper also covers the course of the development of fracture energy metric and implementations of HSBS metrology into HVM environment as an in line BA process monitoring system. Lastly, a comparison of the facture energy between ENIG and improve surface plating is provided to show the margin gained by improve surface plating technologies.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507818
T. Hsu, K. Chiang, J. Lai, Yu-Po Wang
In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection. The propagation delay, insertion loss and return loss results will be compared among these three types interconnection. TSV interconnection shows the best performance among the three types due to its shortest interconnection path between die to die. We also study electrical characteristics of different TSV structure, like TSV size, TSV height, TSV pitch and the number of TSV stacked. Based on the analysis results, we will provide the design guideline for designer reference.
{"title":"Electrical characterization of through silicon via (TSV) for high-speed memory application","authors":"T. Hsu, K. Chiang, J. Lai, Yu-Po Wang","doi":"10.1109/IEMT.2008.5507818","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507818","url":null,"abstract":"In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection. The propagation delay, insertion loss and return loss results will be compared among these three types interconnection. TSV interconnection shows the best performance among the three types due to its shortest interconnection path between die to die. We also study electrical characteristics of different TSV structure, like TSV size, TSV height, TSV pitch and the number of TSV stacked. Based on the analysis results, we will provide the design guideline for designer reference.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115627698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507793
Siew Han Looe, Soon Wei Wang
The drive for package thickness thinning and package size reduction has created new challenges for current wafer fabrication and assembly technology which lias led to the smaller die and thinner wafer thickness trend. Thus, the conventional wafer thickness of 8 mils decreases to 4 mils is more challenging for the new innovation package of Micro Leadless Land Grid Array (μLLGA) with only 0.4 mm package thickness. The uniqueness of μLLGA package construction is that it has no die paddle for die attach and the die backside is exposed to customer view, thus no indentation or sign of ejector pin is allowed visible. The level of difficult also increased by the inclusion of 14×14 mil die size and challenge in pick up the micro thin die without having a concern of die back cracking, and dies rotation. Die back cracking is one of the major quality issues for die attach with major contributor due to improper ejector pin selection (made up of tungsten carbide). The gross die back crack can be detected during in process monitoring but the micro crack die back will be difficult to detect and it usually will only be detected through customer application or reliability stress test. Another aspect this paper will cover is the conventional epoxy dispensing no longer viable for thin die attach as critical control is required in order not to have epoxy overflow with 4 mils die thickness die. In replacing this, a new approach known as epoxy screen print on wafer back is introduced to enable a more robust die attach process. This paper explains in details the challenges and solutions of die attach process for the μthin die into this unique μLLGA package. The challenges include: (i). Micro die size of 14 × 14 mils (near to minimum machine capability of 10 mils in die size) (ii). Thin die of 4 mils thickness with epoxy screen printon wafer back, (iii). μLLGA package construction with expose die back (with no die paddle). Design of Experiments (DOE) were carried out to enablea an optimize die attach process which consists key deliverablea as below: (i). Selection of appropriate ejector needle tip size in order not to induce epoxy on die back from cracking or indentation mark during die pick up. (ii). The optimization of die bond critical input parameter in order to achieve optimized process with no issue on die rotation, die unpick and die crack.
{"title":"Challenges & solutions in the die attach process for micro thin die","authors":"Siew Han Looe, Soon Wei Wang","doi":"10.1109/IEMT.2008.5507793","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507793","url":null,"abstract":"The drive for package thickness thinning and package size reduction has created new challenges for current wafer fabrication and assembly technology which lias led to the smaller die and thinner wafer thickness trend. Thus, the conventional wafer thickness of 8 mils decreases to 4 mils is more challenging for the new innovation package of Micro Leadless Land Grid Array (μLLGA) with only 0.4 mm package thickness. The uniqueness of μLLGA package construction is that it has no die paddle for die attach and the die backside is exposed to customer view, thus no indentation or sign of ejector pin is allowed visible. The level of difficult also increased by the inclusion of 14×14 mil die size and challenge in pick up the micro thin die without having a concern of die back cracking, and dies rotation. Die back cracking is one of the major quality issues for die attach with major contributor due to improper ejector pin selection (made up of tungsten carbide). The gross die back crack can be detected during in process monitoring but the micro crack die back will be difficult to detect and it usually will only be detected through customer application or reliability stress test. Another aspect this paper will cover is the conventional epoxy dispensing no longer viable for thin die attach as critical control is required in order not to have epoxy overflow with 4 mils die thickness die. In replacing this, a new approach known as epoxy screen print on wafer back is introduced to enable a more robust die attach process. This paper explains in details the challenges and solutions of die attach process for the μthin die into this unique μLLGA package. The challenges include: (i). Micro die size of 14 × 14 mils (near to minimum machine capability of 10 mils in die size) (ii). Thin die of 4 mils thickness with epoxy screen printon wafer back, (iii). μLLGA package construction with expose die back (with no die paddle). Design of Experiments (DOE) were carried out to enablea an optimize die attach process which consists key deliverablea as below: (i). Selection of appropriate ejector needle tip size in order not to induce epoxy on die back from cracking or indentation mark during die pick up. (ii). The optimization of die bond critical input parameter in order to achieve optimized process with no issue on die rotation, die unpick and die crack.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"T151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125649395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507822
Y. Seng
The green initiative has driven semiconductor manufacturers to eliminate the use of environmentally unfriendly substances such as antimony oxide, flame retardant and halogenated compounds in their microelectronics packages. Nevertheless, there may be concern that the new chemistries in green package may alter the properties of semiconductor devices. We have evaluated the performance of power transistors encapsulated with green and non-green epoxy mold compound (EMC) via autoclave stress. We have proven that green device indeed possesses superior electrical and physical properties than non-green device. Our research result reveals that device with non-green EMC exhibits relatively higher gate-to-source leakage current (IGSS) and drain-to-source on-resistance (RDS[on]) as compared to device with green EMC. The non-steady electrical characteristic of non-green device is attributed to its higher level content of bromide ions released from flame retardant. Under moist environment, bromide ions form electrolytic solutions and trigger the corrosion process. We found that copper ball bonds in non-green device are extremely susceptible to electrolytic corrosion. The corrosion begins from the ball periphery and gradually extends toward the ball base. The corrosive ions accelerate dissolution of aluminum pad underneath copper ball, leading to separation gap formation between intermetallic and bond pad, thus isolating the pad away from the intermetallic layer. Moreover, the gap size is gradually enlarged when the autoclave stress period is extended, resulting in the rise of RDS[on] over time. In contrast, green device is more impervious to corrosion induced bond damage. As a result, green device demonstrates more stable RDS[on] and lesser leakage current of IGSS even operating under high humidity, pressure, and temperature conditions.
{"title":"The performance of power MOSFET devices encapsulated with green and non-green mold compounds","authors":"Y. Seng","doi":"10.1109/IEMT.2008.5507822","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507822","url":null,"abstract":"The green initiative has driven semiconductor manufacturers to eliminate the use of environmentally unfriendly substances such as antimony oxide, flame retardant and halogenated compounds in their microelectronics packages. Nevertheless, there may be concern that the new chemistries in green package may alter the properties of semiconductor devices. We have evaluated the performance of power transistors encapsulated with green and non-green epoxy mold compound (EMC) via autoclave stress. We have proven that green device indeed possesses superior electrical and physical properties than non-green device. Our research result reveals that device with non-green EMC exhibits relatively higher gate-to-source leakage current (IGSS) and drain-to-source on-resistance (RDS[on]) as compared to device with green EMC. The non-steady electrical characteristic of non-green device is attributed to its higher level content of bromide ions released from flame retardant. Under moist environment, bromide ions form electrolytic solutions and trigger the corrosion process. We found that copper ball bonds in non-green device are extremely susceptible to electrolytic corrosion. The corrosion begins from the ball periphery and gradually extends toward the ball base. The corrosive ions accelerate dissolution of aluminum pad underneath copper ball, leading to separation gap formation between intermetallic and bond pad, thus isolating the pad away from the intermetallic layer. Moreover, the gap size is gradually enlarged when the autoclave stress period is extended, resulting in the rise of RDS[on] over time. In contrast, green device is more impervious to corrosion induced bond damage. As a result, green device demonstrates more stable RDS[on] and lesser leakage current of IGSS even operating under high humidity, pressure, and temperature conditions.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131048749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507889
Sim Poh Ching, Yook Hyung Sun, C. Ping
With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting in device failure. Studies have been carried out to enhance device hot carrier immunity by reducing and departure the high electrical field from the drain area. The evaluations were focused on the implant energy and dose factors in order to achieve more graded device junction. The substantial result shows 10 times improvement in hot carrier injection (HCI) DC lifetime and reveals a good direction for suppression the hot carrier effects in 0.18 μm CMOS technology.
{"title":"Optimization of hot carrier resistance for 0.18µm CMOS technology","authors":"Sim Poh Ching, Yook Hyung Sun, C. Ping","doi":"10.1109/IEMT.2008.5507889","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507889","url":null,"abstract":"With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting in device failure. Studies have been carried out to enhance device hot carrier immunity by reducing and departure the high electrical field from the drain area. The evaluations were focused on the implant energy and dose factors in order to achieve more graded device junction. The substantial result shows 10 times improvement in hot carrier injection (HCI) DC lifetime and reveals a good direction for suppression the hot carrier effects in 0.18 μm CMOS technology.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131394995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507794
G. Henshall, R. Healey, R. Pandher, K. Sweatman, K. Howell, R. Coyle, T. Sack, P. Snugovsky, S. Tisdale, F. Hua, H. Fu
Recently, the industry has seen an increase in the number of Pb-free solder alloy choices beyond the common neareutectic Sn-Ag-Cu (SAC) alloys. The increasing number of Pb-free alloys provides opportunities to address important issues, such as the poor drop/shock performance, alloy cost, copper dissolution, and poor mechanical behavior in bend/flex. Most recently, investigations into new solder paste alloys for mass reflow have begun. At the same time, the increase in choice of alloys presents challenges in managing the supply chain and introduces a variety of risks. Poor solder joint formation when BGAs with low Ag alloy balls are soldered at the low end of the conventional Pb-free process window is one example. The full impact of these new alloys on overall printed circuit assembly (PC A) reliability has yet to be determined. This paper provides the results of an iNEMI study of the present state of industry knowledge on Sn-Ag-Cu alloy "alternatives," including an assessment of existing knowledge and critical gaps. Based on this assessment, focus areas have been identified for closing key gaps. Plans and progress in addressing the gaps are described, including efforts to update industry standards to account for the new alloys and to better manage supply chain complexity and risk.
{"title":"Addressing industry knowledge gaps regarding new Pb-free solder alloy alternatives","authors":"G. Henshall, R. Healey, R. Pandher, K. Sweatman, K. Howell, R. Coyle, T. Sack, P. Snugovsky, S. Tisdale, F. Hua, H. Fu","doi":"10.1109/IEMT.2008.5507794","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507794","url":null,"abstract":"Recently, the industry has seen an increase in the number of Pb-free solder alloy choices beyond the common neareutectic Sn-Ag-Cu (SAC) alloys. The increasing number of Pb-free alloys provides opportunities to address important issues, such as the poor drop/shock performance, alloy cost, copper dissolution, and poor mechanical behavior in bend/flex. Most recently, investigations into new solder paste alloys for mass reflow have begun. At the same time, the increase in choice of alloys presents challenges in managing the supply chain and introduces a variety of risks. Poor solder joint formation when BGAs with low Ag alloy balls are soldered at the low end of the conventional Pb-free process window is one example. The full impact of these new alloys on overall printed circuit assembly (PC A) reliability has yet to be determined. This paper provides the results of an iNEMI study of the present state of industry knowledge on Sn-Ag-Cu alloy \"alternatives,\" including an assessment of existing knowledge and critical gaps. Based on this assessment, focus areas have been identified for closing key gaps. Plans and progress in addressing the gaps are described, including efforts to update industry standards to account for the new alloys and to better manage supply chain complexity and risk.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131630064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507857
Zhang Jingyuan, Ruan Jianhua
With a drive of leading lower cost and higher productivity of Small Outline Surface Mounting (SOSM) packages, high density leadframe introduction was launched in the market since 21st century. But almost all factories use more expensive spot silver (Ag) plated and less than 60mm width leadframe. This paper presents the challenges faced and success in the development of unique high density copper (Cu) plated leadframe at more than 70 mm width and less than 0.11mm thicknesses for SOT23 packages. Due to the unique leadframe design, some considerations and solutions were developed: (1) Thermo-mechanical die stress simulation per package assembly process, reflow and temperature cycling for verifying the leadframe designs; (2) Bonder Equipment and process optimization though DOE experiments for eliminating leadframe oxidation and assuring the copper plated leadframe be workable; (3) Special through-gate design for increasing mold compound usage or yield; (4) Development of modeling and special de-gate tool design for broken the sub-gate to remove the leadframe warpage and coilset; (5) Special air blowing device design which was patented in China to stabilize thinner leadframe for passing through plating cells smoothly without leadframe jamming and damaging. The results show high density copper plated leadframe at more than 70mm width and less than 0.11mm thicknesses are applicable for mass production based on special assembly process design and development. It benefits with lower capital investment, leadframe cost saving, mold compound saving and lower production floor spacing.
{"title":"Unique high density leadframe development for SOT23","authors":"Zhang Jingyuan, Ruan Jianhua","doi":"10.1109/IEMT.2008.5507857","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507857","url":null,"abstract":"With a drive of leading lower cost and higher productivity of Small Outline Surface Mounting (SOSM) packages, high density leadframe introduction was launched in the market since 21st century. But almost all factories use more expensive spot silver (Ag) plated and less than 60mm width leadframe. This paper presents the challenges faced and success in the development of unique high density copper (Cu) plated leadframe at more than 70 mm width and less than 0.11mm thicknesses for SOT23 packages. Due to the unique leadframe design, some considerations and solutions were developed: (1) Thermo-mechanical die stress simulation per package assembly process, reflow and temperature cycling for verifying the leadframe designs; (2) Bonder Equipment and process optimization though DOE experiments for eliminating leadframe oxidation and assuring the copper plated leadframe be workable; (3) Special through-gate design for increasing mold compound usage or yield; (4) Development of modeling and special de-gate tool design for broken the sub-gate to remove the leadframe warpage and coilset; (5) Special air blowing device design which was patented in China to stabilize thinner leadframe for passing through plating cells smoothly without leadframe jamming and damaging. The results show high density copper plated leadframe at more than 70mm width and less than 0.11mm thicknesses are applicable for mass production based on special assembly process design and development. It benefits with lower capital investment, leadframe cost saving, mold compound saving and lower production floor spacing.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130431653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507815
S. Ong, J. Ismail, M. Bakar, I. A. Rahman, C. S. Sipaut, C. Chee
Nano composites are a promising development but the challenge of homogenous and discrete dispersion of the nano fillers are barriers that must be overcome before they can be effectively implemented. Although the common dispersion methods such as particle surface modification, comprehensive milling metrologies and the usage of solvents bear results, these are time consuming and not cost effective. In this paper, we explore the efficiency of coupling the usage of ball-media and heat on the dispersion of nano silica in epoxy. No solvents are involved. The effects of milling speed and duration are also studied albeit under a fixed ball media : silica-epoxy volume ratio of 3:5. The experiment set-up involves a simple 3-blade mixer, round bottom flask and 60 ? m zirconia ball. At nano silica loading of 10 wt % the nano silica clusters are systematically reduced from 1.5 - 2 ? m to 100 - 200 nm with the usage of ball media and application of heat. At the optimum milling speed and duration of 500 rpm for 5 hours, the aggregate sizes were further reduced to 30 - 70 nm, which is almost a discrete dispersion.
{"title":"Nano silica dispersion in epoxy : the investigation of heat, milling speed and duration effect","authors":"S. Ong, J. Ismail, M. Bakar, I. A. Rahman, C. S. Sipaut, C. Chee","doi":"10.1109/IEMT.2008.5507815","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507815","url":null,"abstract":"Nano composites are a promising development but the challenge of homogenous and discrete dispersion of the nano fillers are barriers that must be overcome before they can be effectively implemented. Although the common dispersion methods such as particle surface modification, comprehensive milling metrologies and the usage of solvents bear results, these are time consuming and not cost effective. In this paper, we explore the efficiency of coupling the usage of ball-media and heat on the dispersion of nano silica in epoxy. No solvents are involved. The effects of milling speed and duration are also studied albeit under a fixed ball media : silica-epoxy volume ratio of 3:5. The experiment set-up involves a simple 3-blade mixer, round bottom flask and 60 ? m zirconia ball. At nano silica loading of 10 wt % the nano silica clusters are systematically reduced from 1.5 - 2 ? m to 100 - 200 nm with the usage of ball media and application of heat. At the optimum milling speed and duration of 500 rpm for 5 hours, the aggregate sizes were further reduced to 30 - 70 nm, which is almost a discrete dispersion.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129971657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507825
D. Chong, L. Y. Lim
With the advent of ultra portable consumer products, the challenge to attach a die as close to the package size as possible is becoming a major challenge. The current die-attach nozzle dispensing method requires a real estate around the die to be sufficiently large to ensure good epoxy coverage, epoxy fillet height and to prevent the epoxy from overflowing the edges of the DAP. Moreover, a thinner package will require a thinner die which, with epoxy dispensing, could result in die overflowing to the die surface. Such constraints takes time to set-up and a dedicated nozzle will be required to fit every die size combination which would end up with high nozzle inventory and maintenance. A solution is needed at die-attach to meet the new challenge where the die size is almost as big as the DAP and where the die thickness is thinner in order to achieve a lower electrical resistance and package height and, where current epoxy dispensing method is no longer viable. And the alternative now available in the market is highly electrically conductive epoxy wafer back coating. This process does away with epoxy dispensing and is printed directly over the back of the wafer and b-staged cured prior to wafer mounting and sawing. The epoxy thickness is directly controlled by the thickness of the electroformed stencil and mesh. Unlike non-conductive paste or lower electrically conductive epoxies, the epoxy does not “sag” after wafer back coating, hence, roughness of the printed epoxy is through squeegee type and the printing parameters. This study covers the feasibility of assembly from wafer preparation to test by using wafer back coating epoxy, its challenges and issues as well as comparing the electrical performance of the package to that of conventional die attach dispense epoxy.
{"title":"Feasibility study on replacing conventional epoxy dispensing with wafer back coating epoxy for QFN packages for discrete product","authors":"D. Chong, L. Y. Lim","doi":"10.1109/IEMT.2008.5507825","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507825","url":null,"abstract":"With the advent of ultra portable consumer products, the challenge to attach a die as close to the package size as possible is becoming a major challenge. The current die-attach nozzle dispensing method requires a real estate around the die to be sufficiently large to ensure good epoxy coverage, epoxy fillet height and to prevent the epoxy from overflowing the edges of the DAP. Moreover, a thinner package will require a thinner die which, with epoxy dispensing, could result in die overflowing to the die surface. Such constraints takes time to set-up and a dedicated nozzle will be required to fit every die size combination which would end up with high nozzle inventory and maintenance. A solution is needed at die-attach to meet the new challenge where the die size is almost as big as the DAP and where the die thickness is thinner in order to achieve a lower electrical resistance and package height and, where current epoxy dispensing method is no longer viable. And the alternative now available in the market is highly electrically conductive epoxy wafer back coating. This process does away with epoxy dispensing and is printed directly over the back of the wafer and b-staged cured prior to wafer mounting and sawing. The epoxy thickness is directly controlled by the thickness of the electroformed stencil and mesh. Unlike non-conductive paste or lower electrically conductive epoxies, the epoxy does not “sag” after wafer back coating, hence, roughness of the printed epoxy is through squeegee type and the printing parameters. This study covers the feasibility of assembly from wafer preparation to test by using wafer back coating epoxy, its challenges and issues as well as comparing the electrical performance of the package to that of conventional die attach dispense epoxy.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126403052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507817
W. S. Ooi, Azlina Nayan, D. Ding, R. Newman, X. Zhao, S. Parthasarathy
This paper describes the improvement on coined solder surface of organic substrate to reduce flip chip assembly defects namely chip misalignment and contact non-wet. Roughening of the eutectic solder surface of the substrate helped to reduce bump misalignment for all packages especially for the tight bump pitch package. Additional pin reflow process for land grid array (LGA) substrates had proven to eliminate contact non wet issue. The surface morphology of the eutectic Sn/Pb bumps in the evaluations is characterized by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The condition of the solder joint is confirmed by chip pull test, x-ray and electrical test, using open/short test program.
{"title":"Improvement on coined solder surface on organic substrate for flip chip attach yield improvement","authors":"W. S. Ooi, Azlina Nayan, D. Ding, R. Newman, X. Zhao, S. Parthasarathy","doi":"10.1109/IEMT.2008.5507817","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507817","url":null,"abstract":"This paper describes the improvement on coined solder surface of organic substrate to reduce flip chip assembly defects namely chip misalignment and contact non-wet. Roughening of the eutectic solder surface of the substrate helped to reduce bump misalignment for all packages especially for the tight bump pitch package. Additional pin reflow process for land grid array (LGA) substrates had proven to eliminate contact non wet issue. The surface morphology of the eutectic Sn/Pb bumps in the evaluations is characterized by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The condition of the solder joint is confirmed by chip pull test, x-ray and electrical test, using open/short test program.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114322996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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