Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507822
Y. Seng
The green initiative has driven semiconductor manufacturers to eliminate the use of environmentally unfriendly substances such as antimony oxide, flame retardant and halogenated compounds in their microelectronics packages. Nevertheless, there may be concern that the new chemistries in green package may alter the properties of semiconductor devices. We have evaluated the performance of power transistors encapsulated with green and non-green epoxy mold compound (EMC) via autoclave stress. We have proven that green device indeed possesses superior electrical and physical properties than non-green device. Our research result reveals that device with non-green EMC exhibits relatively higher gate-to-source leakage current (IGSS) and drain-to-source on-resistance (RDS[on]) as compared to device with green EMC. The non-steady electrical characteristic of non-green device is attributed to its higher level content of bromide ions released from flame retardant. Under moist environment, bromide ions form electrolytic solutions and trigger the corrosion process. We found that copper ball bonds in non-green device are extremely susceptible to electrolytic corrosion. The corrosion begins from the ball periphery and gradually extends toward the ball base. The corrosive ions accelerate dissolution of aluminum pad underneath copper ball, leading to separation gap formation between intermetallic and bond pad, thus isolating the pad away from the intermetallic layer. Moreover, the gap size is gradually enlarged when the autoclave stress period is extended, resulting in the rise of RDS[on] over time. In contrast, green device is more impervious to corrosion induced bond damage. As a result, green device demonstrates more stable RDS[on] and lesser leakage current of IGSS even operating under high humidity, pressure, and temperature conditions.
{"title":"The performance of power MOSFET devices encapsulated with green and non-green mold compounds","authors":"Y. Seng","doi":"10.1109/IEMT.2008.5507822","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507822","url":null,"abstract":"The green initiative has driven semiconductor manufacturers to eliminate the use of environmentally unfriendly substances such as antimony oxide, flame retardant and halogenated compounds in their microelectronics packages. Nevertheless, there may be concern that the new chemistries in green package may alter the properties of semiconductor devices. We have evaluated the performance of power transistors encapsulated with green and non-green epoxy mold compound (EMC) via autoclave stress. We have proven that green device indeed possesses superior electrical and physical properties than non-green device. Our research result reveals that device with non-green EMC exhibits relatively higher gate-to-source leakage current (IGSS) and drain-to-source on-resistance (RDS[on]) as compared to device with green EMC. The non-steady electrical characteristic of non-green device is attributed to its higher level content of bromide ions released from flame retardant. Under moist environment, bromide ions form electrolytic solutions and trigger the corrosion process. We found that copper ball bonds in non-green device are extremely susceptible to electrolytic corrosion. The corrosion begins from the ball periphery and gradually extends toward the ball base. The corrosive ions accelerate dissolution of aluminum pad underneath copper ball, leading to separation gap formation between intermetallic and bond pad, thus isolating the pad away from the intermetallic layer. Moreover, the gap size is gradually enlarged when the autoclave stress period is extended, resulting in the rise of RDS[on] over time. In contrast, green device is more impervious to corrosion induced bond damage. As a result, green device demonstrates more stable RDS[on] and lesser leakage current of IGSS even operating under high humidity, pressure, and temperature conditions.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131048749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507775
L. Chan, Kwan Yiu Fai, Y. C. Ho
Improvement of electronic device packaging reliability, more specifically moisture attack resistance (commonly known as moisture sensitivity level or MSL), has been a hot topic in recent years due to the increase in solder reflow temperature for lead-free solder. In preceding failure mode analysis, delamination between lead frame and encapsulation molding compound (EMC) interface plays an important role. Thus a modified brown oxide treatment was developed and applied onto the copper lead frame surface, which is field proven an effective way to elevate package MSL performance. Comparing with typical brown oxide treatment developed in older days for use in printed circuit board (PCB), this modified treatment was specially for use in copper lead frame so that it not only enhances the adhesion with die-attach epoxy glue and EMC, but also leaving a clean silver plating surface for wire bonding.
{"title":"Modified brown oxide treatment as an adhesion promoter for copper lead frame in plastic integrated-circuit packages","authors":"L. Chan, Kwan Yiu Fai, Y. C. Ho","doi":"10.1109/IEMT.2008.5507775","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507775","url":null,"abstract":"Improvement of electronic device packaging reliability, more specifically moisture attack resistance (commonly known as moisture sensitivity level or MSL), has been a hot topic in recent years due to the increase in solder reflow temperature for lead-free solder. In preceding failure mode analysis, delamination between lead frame and encapsulation molding compound (EMC) interface plays an important role. Thus a modified brown oxide treatment was developed and applied onto the copper lead frame surface, which is field proven an effective way to elevate package MSL performance. Comparing with typical brown oxide treatment developed in older days for use in printed circuit board (PCB), this modified treatment was specially for use in copper lead frame so that it not only enhances the adhesion with die-attach epoxy glue and EMC, but also leaving a clean silver plating surface for wire bonding.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122756731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507809
K. Kanlayasiri
This research was aimed to study effects of indium (In) addition on solidus and liquidus temperatures, wetting time, wetting force, and microhardness of Sn-0.3Ag-0.7Cu lead-free solder alloy. It was found that In had a strong influence on these properties of Sn-0.3Ag-0.7Cu. Solidus and liquidus temperatures of the solder alloys was lowered as the In content was increased. However, In addition increased the melting range between solidus and liquidus temperatures. Wetting time of the solder alloy was reduced by the addition of In while the wetting force was increased with the increase of In content. Microhardness of Sn-0.3Ag-0.7Cu was increased by adding In into the solder alloy. With the addition of In, the Sn-rich phase was smaller in size, and the intermetallic compounds were more uniformly distributed.
{"title":"Effects of in addition on solidus and liquidus temperatures, microhardness, and wettability of Sn-0.3Ag-0.7Cu solder alloy","authors":"K. Kanlayasiri","doi":"10.1109/IEMT.2008.5507809","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507809","url":null,"abstract":"This research was aimed to study effects of indium (In) addition on solidus and liquidus temperatures, wetting time, wetting force, and microhardness of Sn-0.3Ag-0.7Cu lead-free solder alloy. It was found that In had a strong influence on these properties of Sn-0.3Ag-0.7Cu. Solidus and liquidus temperatures of the solder alloys was lowered as the In content was increased. However, In addition increased the melting range between solidus and liquidus temperatures. Wetting time of the solder alloy was reduced by the addition of In while the wetting force was increased with the increase of In content. Microhardness of Sn-0.3Ag-0.7Cu was increased by adding In into the solder alloy. With the addition of In, the Sn-rich phase was smaller in size, and the intermetallic compounds were more uniformly distributed.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123167517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507864
Lai Zheng Bo, N. Kamsah, L. W. Keat, M. Tamin
A thorough understanding of the mechanics of lead-free solder joint in a ball grid array (BGA) assembly under expected operating conditions is essential in developing reliable life prediction models. In this respect, accurate deformation response of Sn-4Ag-0.5Cu (SAC405) solder under varying temperature cycles and straining rates is established using unified inelastic strain theory. The mechanics of the solder joint is then quantified through finite element modeling of a typical BGA assembly. The 3D quarter-model of the test assembly consists of silicon die, FR-4 substrate and printed circuit board (PCB), copper traces, intermetallics layer (IMC) and SAC405 solder joints in an area array. Reflow temperature profile consists of cooling from the assumed stress-free temperature of 220 to 25°C. Temperature cycles in the range between 125 and -40°C with dwell time at peak temperature levels are simulated. Results show that residual von Mises stress of 48.7 MPa and the corresponding inelastic strain of 0.031 are predicted in the critical solder joint at 25°C following solder reflow cooling. Additional inelastic strains accumulates continuously in the solder throughout the temperature cycles. Solder stress relaxation with accompanying inelastic strain occurs during dwell-time periods at both -40 and 125°C due viscoplastic and creep effects, respectively. In the critical solder joint, both high stress and strain gradients are localized in a small edge region at the solder-IMC interface near the component (SMD) side of the assembly. A new fatigue life model with unified inelastic strain theory defined for SAC405 solder joints is proposed based on accumulated inelastic strains and plastic work density of the critical solder joint.
{"title":"Mechanics of Sn-4Ag-0.5Cu solder joints in a ball grid array assembly during reflow and temperature cycles","authors":"Lai Zheng Bo, N. Kamsah, L. W. Keat, M. Tamin","doi":"10.1109/IEMT.2008.5507864","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507864","url":null,"abstract":"A thorough understanding of the mechanics of lead-free solder joint in a ball grid array (BGA) assembly under expected operating conditions is essential in developing reliable life prediction models. In this respect, accurate deformation response of Sn-4Ag-0.5Cu (SAC405) solder under varying temperature cycles and straining rates is established using unified inelastic strain theory. The mechanics of the solder joint is then quantified through finite element modeling of a typical BGA assembly. The 3D quarter-model of the test assembly consists of silicon die, FR-4 substrate and printed circuit board (PCB), copper traces, intermetallics layer (IMC) and SAC405 solder joints in an area array. Reflow temperature profile consists of cooling from the assumed stress-free temperature of 220 to 25°C. Temperature cycles in the range between 125 and -40°C with dwell time at peak temperature levels are simulated. Results show that residual von Mises stress of 48.7 MPa and the corresponding inelastic strain of 0.031 are predicted in the critical solder joint at 25°C following solder reflow cooling. Additional inelastic strains accumulates continuously in the solder throughout the temperature cycles. Solder stress relaxation with accompanying inelastic strain occurs during dwell-time periods at both -40 and 125°C due viscoplastic and creep effects, respectively. In the critical solder joint, both high stress and strain gradients are localized in a small edge region at the solder-IMC interface near the component (SMD) side of the assembly. A new fatigue life model with unified inelastic strain theory defined for SAC405 solder joints is proposed based on accumulated inelastic strains and plastic work density of the critical solder joint.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123329362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507884
N. Annamalai, Narendra Kumar Patel, Subramaniam Muthukarapan
Preventive maintenance (PM) is a crucial activity to ensure the stability and performance of a tool. It has lead to long hour and tedious activity on SHBI (Self Heat Burn-In). SHBI is a tool used to support the Burn-In process. SHBI carries several long hour PM task which also requires some conversion activities. This has been leading to a total >15% weekly capacity loss. This paper will discuss on how both the unproductive long hour activities have been analyzed through theory of innovative problem solving (TRIZ) methodology.
{"title":"Radical breakthrough innovative solution in SHBI PM optimization using TRIZ","authors":"N. Annamalai, Narendra Kumar Patel, Subramaniam Muthukarapan","doi":"10.1109/IEMT.2008.5507884","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507884","url":null,"abstract":"Preventive maintenance (PM) is a crucial activity to ensure the stability and performance of a tool. It has lead to long hour and tedious activity on SHBI (Self Heat Burn-In). SHBI is a tool used to support the Burn-In process. SHBI carries several long hour PM task which also requires some conversion activities. This has been leading to a total >15% weekly capacity loss. This paper will discuss on how both the unproductive long hour activities have been analyzed through theory of innovative problem solving (TRIZ) methodology.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124239551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507825
D. Chong, L. Y. Lim
With the advent of ultra portable consumer products, the challenge to attach a die as close to the package size as possible is becoming a major challenge. The current die-attach nozzle dispensing method requires a real estate around the die to be sufficiently large to ensure good epoxy coverage, epoxy fillet height and to prevent the epoxy from overflowing the edges of the DAP. Moreover, a thinner package will require a thinner die which, with epoxy dispensing, could result in die overflowing to the die surface. Such constraints takes time to set-up and a dedicated nozzle will be required to fit every die size combination which would end up with high nozzle inventory and maintenance. A solution is needed at die-attach to meet the new challenge where the die size is almost as big as the DAP and where the die thickness is thinner in order to achieve a lower electrical resistance and package height and, where current epoxy dispensing method is no longer viable. And the alternative now available in the market is highly electrically conductive epoxy wafer back coating. This process does away with epoxy dispensing and is printed directly over the back of the wafer and b-staged cured prior to wafer mounting and sawing. The epoxy thickness is directly controlled by the thickness of the electroformed stencil and mesh. Unlike non-conductive paste or lower electrically conductive epoxies, the epoxy does not “sag” after wafer back coating, hence, roughness of the printed epoxy is through squeegee type and the printing parameters. This study covers the feasibility of assembly from wafer preparation to test by using wafer back coating epoxy, its challenges and issues as well as comparing the electrical performance of the package to that of conventional die attach dispense epoxy.
{"title":"Feasibility study on replacing conventional epoxy dispensing with wafer back coating epoxy for QFN packages for discrete product","authors":"D. Chong, L. Y. Lim","doi":"10.1109/IEMT.2008.5507825","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507825","url":null,"abstract":"With the advent of ultra portable consumer products, the challenge to attach a die as close to the package size as possible is becoming a major challenge. The current die-attach nozzle dispensing method requires a real estate around the die to be sufficiently large to ensure good epoxy coverage, epoxy fillet height and to prevent the epoxy from overflowing the edges of the DAP. Moreover, a thinner package will require a thinner die which, with epoxy dispensing, could result in die overflowing to the die surface. Such constraints takes time to set-up and a dedicated nozzle will be required to fit every die size combination which would end up with high nozzle inventory and maintenance. A solution is needed at die-attach to meet the new challenge where the die size is almost as big as the DAP and where the die thickness is thinner in order to achieve a lower electrical resistance and package height and, where current epoxy dispensing method is no longer viable. And the alternative now available in the market is highly electrically conductive epoxy wafer back coating. This process does away with epoxy dispensing and is printed directly over the back of the wafer and b-staged cured prior to wafer mounting and sawing. The epoxy thickness is directly controlled by the thickness of the electroformed stencil and mesh. Unlike non-conductive paste or lower electrically conductive epoxies, the epoxy does not “sag” after wafer back coating, hence, roughness of the printed epoxy is through squeegee type and the printing parameters. This study covers the feasibility of assembly from wafer preparation to test by using wafer back coating epoxy, its challenges and issues as well as comparing the electrical performance of the package to that of conventional die attach dispense epoxy.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126403052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507793
Siew Han Looe, Soon Wei Wang
The drive for package thickness thinning and package size reduction has created new challenges for current wafer fabrication and assembly technology which lias led to the smaller die and thinner wafer thickness trend. Thus, the conventional wafer thickness of 8 mils decreases to 4 mils is more challenging for the new innovation package of Micro Leadless Land Grid Array (μLLGA) with only 0.4 mm package thickness. The uniqueness of μLLGA package construction is that it has no die paddle for die attach and the die backside is exposed to customer view, thus no indentation or sign of ejector pin is allowed visible. The level of difficult also increased by the inclusion of 14×14 mil die size and challenge in pick up the micro thin die without having a concern of die back cracking, and dies rotation. Die back cracking is one of the major quality issues for die attach with major contributor due to improper ejector pin selection (made up of tungsten carbide). The gross die back crack can be detected during in process monitoring but the micro crack die back will be difficult to detect and it usually will only be detected through customer application or reliability stress test. Another aspect this paper will cover is the conventional epoxy dispensing no longer viable for thin die attach as critical control is required in order not to have epoxy overflow with 4 mils die thickness die. In replacing this, a new approach known as epoxy screen print on wafer back is introduced to enable a more robust die attach process. This paper explains in details the challenges and solutions of die attach process for the μthin die into this unique μLLGA package. The challenges include: (i). Micro die size of 14 × 14 mils (near to minimum machine capability of 10 mils in die size) (ii). Thin die of 4 mils thickness with epoxy screen printon wafer back, (iii). μLLGA package construction with expose die back (with no die paddle). Design of Experiments (DOE) were carried out to enablea an optimize die attach process which consists key deliverablea as below: (i). Selection of appropriate ejector needle tip size in order not to induce epoxy on die back from cracking or indentation mark during die pick up. (ii). The optimization of die bond critical input parameter in order to achieve optimized process with no issue on die rotation, die unpick and die crack.
{"title":"Challenges & solutions in the die attach process for micro thin die","authors":"Siew Han Looe, Soon Wei Wang","doi":"10.1109/IEMT.2008.5507793","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507793","url":null,"abstract":"The drive for package thickness thinning and package size reduction has created new challenges for current wafer fabrication and assembly technology which lias led to the smaller die and thinner wafer thickness trend. Thus, the conventional wafer thickness of 8 mils decreases to 4 mils is more challenging for the new innovation package of Micro Leadless Land Grid Array (μLLGA) with only 0.4 mm package thickness. The uniqueness of μLLGA package construction is that it has no die paddle for die attach and the die backside is exposed to customer view, thus no indentation or sign of ejector pin is allowed visible. The level of difficult also increased by the inclusion of 14×14 mil die size and challenge in pick up the micro thin die without having a concern of die back cracking, and dies rotation. Die back cracking is one of the major quality issues for die attach with major contributor due to improper ejector pin selection (made up of tungsten carbide). The gross die back crack can be detected during in process monitoring but the micro crack die back will be difficult to detect and it usually will only be detected through customer application or reliability stress test. Another aspect this paper will cover is the conventional epoxy dispensing no longer viable for thin die attach as critical control is required in order not to have epoxy overflow with 4 mils die thickness die. In replacing this, a new approach known as epoxy screen print on wafer back is introduced to enable a more robust die attach process. This paper explains in details the challenges and solutions of die attach process for the μthin die into this unique μLLGA package. The challenges include: (i). Micro die size of 14 × 14 mils (near to minimum machine capability of 10 mils in die size) (ii). Thin die of 4 mils thickness with epoxy screen printon wafer back, (iii). μLLGA package construction with expose die back (with no die paddle). Design of Experiments (DOE) were carried out to enablea an optimize die attach process which consists key deliverablea as below: (i). Selection of appropriate ejector needle tip size in order not to induce epoxy on die back from cracking or indentation mark during die pick up. (ii). The optimization of die bond critical input parameter in order to achieve optimized process with no issue on die rotation, die unpick and die crack.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"T151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125649395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507857
Zhang Jingyuan, Ruan Jianhua
With a drive of leading lower cost and higher productivity of Small Outline Surface Mounting (SOSM) packages, high density leadframe introduction was launched in the market since 21st century. But almost all factories use more expensive spot silver (Ag) plated and less than 60mm width leadframe. This paper presents the challenges faced and success in the development of unique high density copper (Cu) plated leadframe at more than 70 mm width and less than 0.11mm thicknesses for SOT23 packages. Due to the unique leadframe design, some considerations and solutions were developed: (1) Thermo-mechanical die stress simulation per package assembly process, reflow and temperature cycling for verifying the leadframe designs; (2) Bonder Equipment and process optimization though DOE experiments for eliminating leadframe oxidation and assuring the copper plated leadframe be workable; (3) Special through-gate design for increasing mold compound usage or yield; (4) Development of modeling and special de-gate tool design for broken the sub-gate to remove the leadframe warpage and coilset; (5) Special air blowing device design which was patented in China to stabilize thinner leadframe for passing through plating cells smoothly without leadframe jamming and damaging. The results show high density copper plated leadframe at more than 70mm width and less than 0.11mm thicknesses are applicable for mass production based on special assembly process design and development. It benefits with lower capital investment, leadframe cost saving, mold compound saving and lower production floor spacing.
{"title":"Unique high density leadframe development for SOT23","authors":"Zhang Jingyuan, Ruan Jianhua","doi":"10.1109/IEMT.2008.5507857","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507857","url":null,"abstract":"With a drive of leading lower cost and higher productivity of Small Outline Surface Mounting (SOSM) packages, high density leadframe introduction was launched in the market since 21st century. But almost all factories use more expensive spot silver (Ag) plated and less than 60mm width leadframe. This paper presents the challenges faced and success in the development of unique high density copper (Cu) plated leadframe at more than 70 mm width and less than 0.11mm thicknesses for SOT23 packages. Due to the unique leadframe design, some considerations and solutions were developed: (1) Thermo-mechanical die stress simulation per package assembly process, reflow and temperature cycling for verifying the leadframe designs; (2) Bonder Equipment and process optimization though DOE experiments for eliminating leadframe oxidation and assuring the copper plated leadframe be workable; (3) Special through-gate design for increasing mold compound usage or yield; (4) Development of modeling and special de-gate tool design for broken the sub-gate to remove the leadframe warpage and coilset; (5) Special air blowing device design which was patented in China to stabilize thinner leadframe for passing through plating cells smoothly without leadframe jamming and damaging. The results show high density copper plated leadframe at more than 70mm width and less than 0.11mm thicknesses are applicable for mass production based on special assembly process design and development. It benefits with lower capital investment, leadframe cost saving, mold compound saving and lower production floor spacing.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130431653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507889
Sim Poh Ching, Yook Hyung Sun, C. Ping
With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting in device failure. Studies have been carried out to enhance device hot carrier immunity by reducing and departure the high electrical field from the drain area. The evaluations were focused on the implant energy and dose factors in order to achieve more graded device junction. The substantial result shows 10 times improvement in hot carrier injection (HCI) DC lifetime and reveals a good direction for suppression the hot carrier effects in 0.18 μm CMOS technology.
{"title":"Optimization of hot carrier resistance for 0.18µm CMOS technology","authors":"Sim Poh Ching, Yook Hyung Sun, C. Ping","doi":"10.1109/IEMT.2008.5507889","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507889","url":null,"abstract":"With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting in device failure. Studies have been carried out to enhance device hot carrier immunity by reducing and departure the high electrical field from the drain area. The evaluations were focused on the implant energy and dose factors in order to achieve more graded device junction. The substantial result shows 10 times improvement in hot carrier injection (HCI) DC lifetime and reveals a good direction for suppression the hot carrier effects in 0.18 μm CMOS technology.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131394995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507794
G. Henshall, R. Healey, R. Pandher, K. Sweatman, K. Howell, R. Coyle, T. Sack, P. Snugovsky, S. Tisdale, F. Hua, H. Fu
Recently, the industry has seen an increase in the number of Pb-free solder alloy choices beyond the common neareutectic Sn-Ag-Cu (SAC) alloys. The increasing number of Pb-free alloys provides opportunities to address important issues, such as the poor drop/shock performance, alloy cost, copper dissolution, and poor mechanical behavior in bend/flex. Most recently, investigations into new solder paste alloys for mass reflow have begun. At the same time, the increase in choice of alloys presents challenges in managing the supply chain and introduces a variety of risks. Poor solder joint formation when BGAs with low Ag alloy balls are soldered at the low end of the conventional Pb-free process window is one example. The full impact of these new alloys on overall printed circuit assembly (PC A) reliability has yet to be determined. This paper provides the results of an iNEMI study of the present state of industry knowledge on Sn-Ag-Cu alloy "alternatives," including an assessment of existing knowledge and critical gaps. Based on this assessment, focus areas have been identified for closing key gaps. Plans and progress in addressing the gaps are described, including efforts to update industry standards to account for the new alloys and to better manage supply chain complexity and risk.
{"title":"Addressing industry knowledge gaps regarding new Pb-free solder alloy alternatives","authors":"G. Henshall, R. Healey, R. Pandher, K. Sweatman, K. Howell, R. Coyle, T. Sack, P. Snugovsky, S. Tisdale, F. Hua, H. Fu","doi":"10.1109/IEMT.2008.5507794","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507794","url":null,"abstract":"Recently, the industry has seen an increase in the number of Pb-free solder alloy choices beyond the common neareutectic Sn-Ag-Cu (SAC) alloys. The increasing number of Pb-free alloys provides opportunities to address important issues, such as the poor drop/shock performance, alloy cost, copper dissolution, and poor mechanical behavior in bend/flex. Most recently, investigations into new solder paste alloys for mass reflow have begun. At the same time, the increase in choice of alloys presents challenges in managing the supply chain and introduces a variety of risks. Poor solder joint formation when BGAs with low Ag alloy balls are soldered at the low end of the conventional Pb-free process window is one example. The full impact of these new alloys on overall printed circuit assembly (PC A) reliability has yet to be determined. This paper provides the results of an iNEMI study of the present state of industry knowledge on Sn-Ag-Cu alloy \"alternatives,\" including an assessment of existing knowledge and critical gaps. Based on this assessment, focus areas have been identified for closing key gaps. Plans and progress in addressing the gaps are described, including efforts to update industry standards to account for the new alloys and to better manage supply chain complexity and risk.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131630064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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