Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507896
K. H. Ang, K. Cheong, Azmi Abdul Malik, Siew Lang Lee, G. Omar, S. Lim, C. L. Lim, Danny Tan, Michael B C Khoo
Polyimides are used extensively in the semiconductor industry as passivation layers, interlayers and dielectrics because of their excellent properties. These properties include thermal stability, superior chemical resistance, high mechanical strength and low dielectric constant. Most polyimide used in the semiconductor industry is the negative-type photosensitive polyimide due to its direct patternability. The purpose of this paper is to study the effect of process time delay during the polyamic ester formation to the final imidized polyimide. Post Coat Delay (PCD) is the delay time after coating before undergoing exposing while Post Expose Delay (PED) is the delay time after exposing before undergoing development. Samples of imide coated on bare wafers with after cure thickness of 6 Em are used. The image from Microscope inspection shows that the sample that is processed immediately is different from those other samples. The results of the after cure thickness of polyimides show that all the samples are within specification limit. Fourier Transform Infra Red (FTIR) is used to check for the chemical bonding. All the samples are fully imidized without peaks indicating the existence of PAE precursor. The imidization rate is lower as the delay time increase for both PCD and PED. Further investigation need to be done to verified the results.
{"title":"A study of the process time effect to photosensitive polyimides","authors":"K. H. Ang, K. Cheong, Azmi Abdul Malik, Siew Lang Lee, G. Omar, S. Lim, C. L. Lim, Danny Tan, Michael B C Khoo","doi":"10.1109/IEMT.2008.5507896","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507896","url":null,"abstract":"Polyimides are used extensively in the semiconductor industry as passivation layers, interlayers and dielectrics because of their excellent properties. These properties include thermal stability, superior chemical resistance, high mechanical strength and low dielectric constant. Most polyimide used in the semiconductor industry is the negative-type photosensitive polyimide due to its direct patternability. The purpose of this paper is to study the effect of process time delay during the polyamic ester formation to the final imidized polyimide. Post Coat Delay (PCD) is the delay time after coating before undergoing exposing while Post Expose Delay (PED) is the delay time after exposing before undergoing development. Samples of imide coated on bare wafers with after cure thickness of 6 Em are used. The image from Microscope inspection shows that the sample that is processed immediately is different from those other samples. The results of the after cure thickness of polyimides show that all the samples are within specification limit. Fourier Transform Infra Red (FTIR) is used to check for the chemical bonding. All the samples are fully imidized without peaks indicating the existence of PAE precursor. The imidization rate is lower as the delay time increase for both PCD and PED. Further investigation need to be done to verified the results.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129175789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507774
A. Strandjord, T. Teutsch, A. Scheffler, T. Oppert, G. Azdasht, E. Zakel
WLCSP bumps have traditionally been produced by dropping preformed solder spheres through a metal template onto silicon wafers using modified surface mount stencil printers. The squeegee blades associated with these printers have been retrofitted with a special fixture in which spheres are gravity feed down through a narrow slot. This same stencil printer is often used to apply the flux to the wafer just prior to sphere dropping. This technique is applicable for many applications but there are several issues are associated with this technology that limit its widespread use in high volume and high yield applications. These limitations include: 1) there is a practical lower limit to the size of sphere that can be dropped, 2) the seal between the slotted fixturing and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and 3) the yields are statistically low. Flip Chip bumps have traditionally been produced by electroplating or paste printing processes. Both technologies have been implemented in high volumes for PdSn bumping at many facility across the world. The electroplating technique is somewhat limited for use in smaller facilities due to the high capital and operation costs. In addition, ternary alloys, like SnAgCu are difficult to plate with consistent results. There is also a practical upper limit to the size of the bump that can be produced, and most applications rare for fine pitch bumping.. The paste printing technologies are very versatile with respect to the alloy composition that can be use, but is limited to pitches around 200μm for 100μm tall bumps. One new WLCSP technology that is showing high promise toward eliminating these limitations for both WLCSp and Flip Chip, is Wafer Level Solder Sphere Transfer (also called Gang Ball Placement). This technology uses a patterned vacuum plate to simultaneous pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them over to the wafer. This paper will discuss this technology and the process parameters for producing WLCSP bumps. Throughput levels of 25 to 30 wafers per hour were measured. Yield losses of less than 10ppm were realized for placing 300μm spheres onto 200mm wafers with ~80,000 I/Os. Similar yields have been observed for placing 60μm flip chip sized spheres onto semiconductor wafers.
{"title":"WLCSP and Flip Chip bumping technologies","authors":"A. Strandjord, T. Teutsch, A. Scheffler, T. Oppert, G. Azdasht, E. Zakel","doi":"10.1109/IEMT.2008.5507774","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507774","url":null,"abstract":"WLCSP bumps have traditionally been produced by dropping preformed solder spheres through a metal template onto silicon wafers using modified surface mount stencil printers. The squeegee blades associated with these printers have been retrofitted with a special fixture in which spheres are gravity feed down through a narrow slot. This same stencil printer is often used to apply the flux to the wafer just prior to sphere dropping. This technique is applicable for many applications but there are several issues are associated with this technology that limit its widespread use in high volume and high yield applications. These limitations include: 1) there is a practical lower limit to the size of sphere that can be dropped, 2) the seal between the slotted fixturing and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and 3) the yields are statistically low. Flip Chip bumps have traditionally been produced by electroplating or paste printing processes. Both technologies have been implemented in high volumes for PdSn bumping at many facility across the world. The electroplating technique is somewhat limited for use in smaller facilities due to the high capital and operation costs. In addition, ternary alloys, like SnAgCu are difficult to plate with consistent results. There is also a practical upper limit to the size of the bump that can be produced, and most applications rare for fine pitch bumping.. The paste printing technologies are very versatile with respect to the alloy composition that can be use, but is limited to pitches around 200μm for 100μm tall bumps. One new WLCSP technology that is showing high promise toward eliminating these limitations for both WLCSp and Flip Chip, is Wafer Level Solder Sphere Transfer (also called Gang Ball Placement). This technology uses a patterned vacuum plate to simultaneous pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them over to the wafer. This paper will discuss this technology and the process parameters for producing WLCSP bumps. Throughput levels of 25 to 30 wafers per hour were measured. Yield losses of less than 10ppm were realized for placing 300μm spheres onto 200mm wafers with ~80,000 I/Os. Similar yields have been observed for placing 60μm flip chip sized spheres onto semiconductor wafers.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"37 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507788
I. Abdullah, I. Ahmad, M. Talib, M. N. Kamarudin
Warpage is greatly affected by package geometries, such as dimension of matrix array, pad, die and passive components as well as molding compound properties. It is also related to thermal mismatch i.e. coefficient of thermal expansion (CTE) and reliability of passive components in the package. So in order to reduce warpage occurrence in all packages, it is proposed that the combination of CTE properties of QFN packages layer need to be optimized. This study used finite element method (FEM) to perform extensive structural analysis of QFN package designs with respect to different combination of thermal properties and the possible occurrence of warpage. The results obtained were then verified with experimental data. The FEA method was able to simulate the warpage occurrence and the statistical method was able to identify the optimal combination of thermal properties of the layers. It was also found that the optimum combination of CTE properties will reduce the probability of the warpage occurrence.
{"title":"Reduction of warpage occurrence on stack-die QFN using FEA and statistical method","authors":"I. Abdullah, I. Ahmad, M. Talib, M. N. Kamarudin","doi":"10.1109/IEMT.2008.5507788","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507788","url":null,"abstract":"Warpage is greatly affected by package geometries, such as dimension of matrix array, pad, die and passive components as well as molding compound properties. It is also related to thermal mismatch i.e. coefficient of thermal expansion (CTE) and reliability of passive components in the package. So in order to reduce warpage occurrence in all packages, it is proposed that the combination of CTE properties of QFN packages layer need to be optimized. This study used finite element method (FEM) to perform extensive structural analysis of QFN package designs with respect to different combination of thermal properties and the possible occurrence of warpage. The results obtained were then verified with experimental data. The FEA method was able to simulate the warpage occurrence and the statistical method was able to identify the optimal combination of thermal properties of the layers. It was also found that the optimum combination of CTE properties will reduce the probability of the warpage occurrence.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507872
Hasnida Abdul Samat, S. Kamaruddin, Ishak Abd Azid
In fast changing and very competitive industry like semiconductor manufacturing, reliability or probability of failure always has been a crucial part in any processes and operation involving machine and equipment. One of many electronic manufacturing technologies is Wire Bond process, which entails a flexible and an accurate technology because of fast changing market demand for smaller electronic gadgets. Nature of wire bond process which is very delicate, usually makes any failures happen during this type of operation goes unnoticed for sometimes and this situation will cost the company a fortune. This paper aims to discuss equipment reliability based on failure occurrences in wire bond process using copper wire. Copper bonding has received attention because of its low cost, high electrical conductivity and resistance to wire sweep during plastic encapsulation. However, copper have hard properties thus more care is required during bonding as to avoid cratering problem. With the situation, this paper was written to find and analyze machine failure using Failure Mode and Effect Analysis (FMEA) technique to verify machine capability and problems faced when operating using Copper wire. Furthermore, general approach for improvement plan based on type of failure and failure causes are presented as conducted in a semiconductor company in Malaysia. The finding of the study provides evidence that failure analysis is an important task to be done in order to understand machine capability and reliability.
在像半导体制造业这样快速变化和竞争激烈的行业中，可靠性或故障概率一直是涉及机器和设备的任何过程和操作的关键部分。电线键合工艺是众多电子制造技术之一，由于市场对小型电子产品的需求快速变化，因此需要灵活而精确的技术。钢丝粘合过程的性质非常微妙，通常在这种类型的操作中发生的任何故障有时都不会被注意到，这种情况会使公司损失一大笔钱。本文的目的是根据铜线焊线过程中出现的故障来讨论设备的可靠性。铜键合因其成本低、电导率高、耐塑料封装过程中的导线扫线等优点而受到人们的关注。然而，铜具有较硬的性质，因此在连接过程中需要更加小心，以避免出现凹坑问题。针对这种情况，本文采用故障模式与影响分析(failure Mode and Effect Analysis, FMEA)技术对机器故障进行发现和分析，验证机器在使用铜线操作时的能力和面临的问题。此外，提出了在马来西亚一家半导体公司进行的基于故障类型和故障原因的改进计划的一般方法。研究结果表明，故障分析是了解机械性能和可靠性的一项重要工作。
{"title":"Failure analysis for Copper Wire Bonding process from machine perspective","authors":"Hasnida Abdul Samat, S. Kamaruddin, Ishak Abd Azid","doi":"10.1109/IEMT.2008.5507872","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507872","url":null,"abstract":"In fast changing and very competitive industry like semiconductor manufacturing, reliability or probability of failure always has been a crucial part in any processes and operation involving machine and equipment. One of many electronic manufacturing technologies is Wire Bond process, which entails a flexible and an accurate technology because of fast changing market demand for smaller electronic gadgets. Nature of wire bond process which is very delicate, usually makes any failures happen during this type of operation goes unnoticed for sometimes and this situation will cost the company a fortune. This paper aims to discuss equipment reliability based on failure occurrences in wire bond process using copper wire. Copper bonding has received attention because of its low cost, high electrical conductivity and resistance to wire sweep during plastic encapsulation. However, copper have hard properties thus more care is required during bonding as to avoid cratering problem. With the situation, this paper was written to find and analyze machine failure using Failure Mode and Effect Analysis (FMEA) technique to verify machine capability and problems faced when operating using Copper wire. Furthermore, general approach for improvement plan based on type of failure and failure causes are presented as conducted in a semiconductor company in Malaysia. The finding of the study provides evidence that failure analysis is an important task to be done in order to understand machine capability and reliability.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133366272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507773
A. Ourdjini, M. A. Azmah Hanim, I. Aisha, Y. T. Chin
Solder joint reliability is dependent on both thickness and morphology of the intermetallics that form and grow at the solder joint interface during soldering and subsequent thermal ageing and examining the morphology of these intermetallics is of great importance. The focus of this paper is to present experimental results of a comprehensive study of the interfacial reactions during soldering of Sn-Ag-Cu lead-free solders on copper (Cu), immersion silver (ImAg), electroless nickel/ immersion gold (ENIG) and electroless nickel/ electroless palladium/ immersion gold (ENEPIG) surface finishes. Using scanning electron microscopy detailed a study of the 3-D morphology and grain size of the intermetallics was conducted. The results showed that when soldering on ENIG and ENEPIG finishes several morphologies of intermetallics with different grain sizes form at the solder joint interface compared to a single intermetallic morphology that forms when soldering on copper and immersion silver. An attempt was made to discuss the effect of several factors that may have an influence on the type of morphology the intermetallics may grow into. The results obtained in the present investigation also revealed that the technique of removing the solder by deep etching to examine the morphology of intermetallics is a convenient and efficient method to investigate the intermetallics formed at the solder joints.
{"title":"Effect of surface finish metallurgy on intermetallic compounds during soldering with tin-silver-copper solders","authors":"A. Ourdjini, M. A. Azmah Hanim, I. Aisha, Y. T. Chin","doi":"10.1109/IEMT.2008.5507773","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507773","url":null,"abstract":"Solder joint reliability is dependent on both thickness and morphology of the intermetallics that form and grow at the solder joint interface during soldering and subsequent thermal ageing and examining the morphology of these intermetallics is of great importance. The focus of this paper is to present experimental results of a comprehensive study of the interfacial reactions during soldering of Sn-Ag-Cu lead-free solders on copper (Cu), immersion silver (ImAg), electroless nickel/ immersion gold (ENIG) and electroless nickel/ electroless palladium/ immersion gold (ENEPIG) surface finishes. Using scanning electron microscopy detailed a study of the 3-D morphology and grain size of the intermetallics was conducted. The results showed that when soldering on ENIG and ENEPIG finishes several morphologies of intermetallics with different grain sizes form at the solder joint interface compared to a single intermetallic morphology that forms when soldering on copper and immersion silver. An attempt was made to discuss the effect of several factors that may have an influence on the type of morphology the intermetallics may grow into. The results obtained in the present investigation also revealed that the technique of removing the solder by deep etching to examine the morphology of intermetallics is a convenient and efficient method to investigate the intermetallics formed at the solder joints.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129824232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507865
Ervina Efzan Mhd Noor, A. B. Ismail, N. M. Sharif, T. Ariga, Zuhailawati Hussain
Due to the increase in the use of electronics devices within the industry, the usage of solder connections has increased. These is a concern that lead within the electronic products is considered toxic because lead has potential for leaching from landfills onto water sources and becoming a hazard to human health and surrounding environment. For this reason, replacing Sn-37Pb to free solder with low melting temperature is one of the most important issues in electronic industry. This is due to a demand on low temperature for interconnection and polymer based part component such as LCD display functionality availability at low temperature apply. In this paper, Bi-In-Sn system alloy was investigated as a potential candidate replacing Sn-37Pb. This study covers on solder characteristic such as melting temperature, thermal expansion and microstructure. Bi-In-Sn was prepared and melted in crucible. Solder was cleaned mechanical and chemical before characterized. DSC shows that, Bi-In-Sn system alloy give low melting temperature in range of 65-100°C. The addition of In to Bi-Sn system alloy lowered the melting temperature compared than Sn-37Pb. Lowest melting temperature ensures that the solder melts, forms a joint with the substrates, and re-solidifies within the shortest possible process time. From thermal expansion analysis, it was found that Bi-In-Sn gives good expansion properties to avoid mismatch between Cu pads and solder itself. EDX analysis indicated that, there are two obvious regions in Bi-In-Sn system alloy microstructure. Bright colour refers to BiIn rich phase region and dark colour refers to Sn rich phase region. BiIn rich phase region is higher compared to Sn rich phase in solder give good properties in terms of ductility.
{"title":"Characteristic of low temperature of Bi-In-Sn solder alloy","authors":"Ervina Efzan Mhd Noor, A. B. Ismail, N. M. Sharif, T. Ariga, Zuhailawati Hussain","doi":"10.1109/IEMT.2008.5507865","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507865","url":null,"abstract":"Due to the increase in the use of electronics devices within the industry, the usage of solder connections has increased. These is a concern that lead within the electronic products is considered toxic because lead has potential for leaching from landfills onto water sources and becoming a hazard to human health and surrounding environment. For this reason, replacing Sn-37Pb to free solder with low melting temperature is one of the most important issues in electronic industry. This is due to a demand on low temperature for interconnection and polymer based part component such as LCD display functionality availability at low temperature apply. In this paper, Bi-In-Sn system alloy was investigated as a potential candidate replacing Sn-37Pb. This study covers on solder characteristic such as melting temperature, thermal expansion and microstructure. Bi-In-Sn was prepared and melted in crucible. Solder was cleaned mechanical and chemical before characterized. DSC shows that, Bi-In-Sn system alloy give low melting temperature in range of 65-100°C. The addition of In to Bi-Sn system alloy lowered the melting temperature compared than Sn-37Pb. Lowest melting temperature ensures that the solder melts, forms a joint with the substrates, and re-solidifies within the shortest possible process time. From thermal expansion analysis, it was found that Bi-In-Sn gives good expansion properties to avoid mismatch between Cu pads and solder itself. EDX analysis indicated that, there are two obvious regions in Bi-In-Sn system alloy microstructure. Bright colour refers to BiIn rich phase region and dark colour refers to Sn rich phase region. BiIn rich phase region is higher compared to Sn rich phase in solder give good properties in terms of ductility.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132037366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507817
W. S. Ooi, Azlina Nayan, D. Ding, R. Newman, X. Zhao, S. Parthasarathy
This paper describes the improvement on coined solder surface of organic substrate to reduce flip chip assembly defects namely chip misalignment and contact non-wet. Roughening of the eutectic solder surface of the substrate helped to reduce bump misalignment for all packages especially for the tight bump pitch package. Additional pin reflow process for land grid array (LGA) substrates had proven to eliminate contact non wet issue. The surface morphology of the eutectic Sn/Pb bumps in the evaluations is characterized by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The condition of the solder joint is confirmed by chip pull test, x-ray and electrical test, using open/short test program.
{"title":"Improvement on coined solder surface on organic substrate for flip chip attach yield improvement","authors":"W. S. Ooi, Azlina Nayan, D. Ding, R. Newman, X. Zhao, S. Parthasarathy","doi":"10.1109/IEMT.2008.5507817","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507817","url":null,"abstract":"This paper describes the improvement on coined solder surface of organic substrate to reduce flip chip assembly defects namely chip misalignment and contact non-wet. Roughening of the eutectic solder surface of the substrate helped to reduce bump misalignment for all packages especially for the tight bump pitch package. Additional pin reflow process for land grid array (LGA) substrates had proven to eliminate contact non wet issue. The surface morphology of the eutectic Sn/Pb bumps in the evaluations is characterized by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The condition of the solder joint is confirmed by chip pull test, x-ray and electrical test, using open/short test program.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114322996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507826
Chee Kan Lee, R. Derek, W. K. Loh, Hui Ping Ng, K. W. Lau
In High Volume Manufacturing (HVM) environment, maintaining assembly process stability is the outmost priority to meet quality and reliability requirement. In recent years of transitioning to Lead Free (LF) solder alloy, tighter ball pitch and increasing hostile use condition, thus the expectation of better and tighter control in Solder Joint Reliability (SJR) is increasing. The SJR concern is not a new phenomenon, numerous research works are published to share the learning and options to resolve SJR issues including introduction of new solder alloy, Stress Compensation Layer (SCL), alternate surface finish and etc. The implementations of LF solder alloy have been found to be more at risk to brittle failure in the intermetallic layers. In view of the Flip Chip (FC) design requirement expands and evolves, it is important that the test metrology should likewise continue to evolve. The High Speed Ball Shear (HSBS) and conventional Cold Ball Pull (CBP) results are compared and discussed in term of the ability to predict susceptibility to interfacial failures due to assembly process changes for Flip Chip Ball Grid Array (FCBGA) packages. Examples of assembly process studies are Ball Attach (BA) reflow profile, effect of multiple reflows on the growth of intermetallic that affects the strength of solder joint performance, substrate plating process skew and etc. In additional, detailed microscopic analysis on post HSBS was executed to study the distribution and thickness of Intermetallic compound (IMC) layer on solder pad for FCBGA packages. The result showed that a higher sensitivity was demonstrated by HSBS as compare to CBP in assembly process shifts detection. This paper also covers the course of the development of fracture energy metric and implementations of HSBS metrology into HVM environment as an in line BA process monitoring system. Lastly, a comparison of the facture energy between ENIG and improve surface plating is provided to show the margin gained by improve surface plating technologies.
{"title":"The next generation of quick turn method for interfacial strength testing: High Speed Ball Shear","authors":"Chee Kan Lee, R. Derek, W. K. Loh, Hui Ping Ng, K. W. Lau","doi":"10.1109/IEMT.2008.5507826","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507826","url":null,"abstract":"In High Volume Manufacturing (HVM) environment, maintaining assembly process stability is the outmost priority to meet quality and reliability requirement. In recent years of transitioning to Lead Free (LF) solder alloy, tighter ball pitch and increasing hostile use condition, thus the expectation of better and tighter control in Solder Joint Reliability (SJR) is increasing. The SJR concern is not a new phenomenon, numerous research works are published to share the learning and options to resolve SJR issues including introduction of new solder alloy, Stress Compensation Layer (SCL), alternate surface finish and etc. The implementations of LF solder alloy have been found to be more at risk to brittle failure in the intermetallic layers. In view of the Flip Chip (FC) design requirement expands and evolves, it is important that the test metrology should likewise continue to evolve. The High Speed Ball Shear (HSBS) and conventional Cold Ball Pull (CBP) results are compared and discussed in term of the ability to predict susceptibility to interfacial failures due to assembly process changes for Flip Chip Ball Grid Array (FCBGA) packages. Examples of assembly process studies are Ball Attach (BA) reflow profile, effect of multiple reflows on the growth of intermetallic that affects the strength of solder joint performance, substrate plating process skew and etc. In additional, detailed microscopic analysis on post HSBS was executed to study the distribution and thickness of Intermetallic compound (IMC) layer on solder pad for FCBGA packages. The result showed that a higher sensitivity was demonstrated by HSBS as compare to CBP in assembly process shifts detection. This paper also covers the course of the development of fracture energy metric and implementations of HSBS metrology into HVM environment as an in line BA process monitoring system. Lastly, a comparison of the facture energy between ENIG and improve surface plating is provided to show the margin gained by improve surface plating technologies.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507818
T. Hsu, K. Chiang, J. Lai, Yu-Po Wang
In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection. The propagation delay, insertion loss and return loss results will be compared among these three types interconnection. TSV interconnection shows the best performance among the three types due to its shortest interconnection path between die to die. We also study electrical characteristics of different TSV structure, like TSV size, TSV height, TSV pitch and the number of TSV stacked. Based on the analysis results, we will provide the design guideline for designer reference.
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Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507815
S. Ong, J. Ismail, M. Bakar, I. A. Rahman, C. S. Sipaut, C. Chee
Nano composites are a promising development but the challenge of homogenous and discrete dispersion of the nano fillers are barriers that must be overcome before they can be effectively implemented. Although the common dispersion methods such as particle surface modification, comprehensive milling metrologies and the usage of solvents bear results, these are time consuming and not cost effective. In this paper, we explore the efficiency of coupling the usage of ball-media and heat on the dispersion of nano silica in epoxy. No solvents are involved. The effects of milling speed and duration are also studied albeit under a fixed ball media : silica-epoxy volume ratio of 3:5. The experiment set-up involves a simple 3-blade mixer, round bottom flask and 60 ? m zirconia ball. At nano silica loading of 10 wt % the nano silica clusters are systematically reduced from 1.5 - 2 ? m to 100 - 200 nm with the usage of ball media and application of heat. At the optimum milling speed and duration of 500 rpm for 5 hours, the aggregate sizes were further reduced to 30 - 70 nm, which is almost a discrete dispersion.
{"title":"Nano silica dispersion in epoxy : the investigation of heat, milling speed and duration effect","authors":"S. Ong, J. Ismail, M. Bakar, I. A. Rahman, C. S. Sipaut, C. Chee","doi":"10.1109/IEMT.2008.5507815","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507815","url":null,"abstract":"Nano composites are a promising development but the challenge of homogenous and discrete dispersion of the nano fillers are barriers that must be overcome before they can be effectively implemented. Although the common dispersion methods such as particle surface modification, comprehensive milling metrologies and the usage of solvents bear results, these are time consuming and not cost effective. In this paper, we explore the efficiency of coupling the usage of ball-media and heat on the dispersion of nano silica in epoxy. No solvents are involved. The effects of milling speed and duration are also studied albeit under a fixed ball media : silica-epoxy volume ratio of 3:5. The experiment set-up involves a simple 3-blade mixer, round bottom flask and 60 ? m zirconia ball. At nano silica loading of 10 wt % the nano silica clusters are systematically reduced from 1.5 - 2 ? m to 100 - 200 nm with the usage of ball media and application of heat. At the optimum milling speed and duration of 500 rpm for 5 hours, the aggregate sizes were further reduced to 30 - 70 nm, which is almost a discrete dispersion.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129971657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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