Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507872
Hasnida Abdul Samat, S. Kamaruddin, Ishak Abd Azid
In fast changing and very competitive industry like semiconductor manufacturing, reliability or probability of failure always has been a crucial part in any processes and operation involving machine and equipment. One of many electronic manufacturing technologies is Wire Bond process, which entails a flexible and an accurate technology because of fast changing market demand for smaller electronic gadgets. Nature of wire bond process which is very delicate, usually makes any failures happen during this type of operation goes unnoticed for sometimes and this situation will cost the company a fortune. This paper aims to discuss equipment reliability based on failure occurrences in wire bond process using copper wire. Copper bonding has received attention because of its low cost, high electrical conductivity and resistance to wire sweep during plastic encapsulation. However, copper have hard properties thus more care is required during bonding as to avoid cratering problem. With the situation, this paper was written to find and analyze machine failure using Failure Mode and Effect Analysis (FMEA) technique to verify machine capability and problems faced when operating using Copper wire. Furthermore, general approach for improvement plan based on type of failure and failure causes are presented as conducted in a semiconductor company in Malaysia. The finding of the study provides evidence that failure analysis is an important task to be done in order to understand machine capability and reliability.
在像半导体制造业这样快速变化和竞争激烈的行业中，可靠性或故障概率一直是涉及机器和设备的任何过程和操作的关键部分。电线键合工艺是众多电子制造技术之一，由于市场对小型电子产品的需求快速变化，因此需要灵活而精确的技术。钢丝粘合过程的性质非常微妙，通常在这种类型的操作中发生的任何故障有时都不会被注意到，这种情况会使公司损失一大笔钱。本文的目的是根据铜线焊线过程中出现的故障来讨论设备的可靠性。铜键合因其成本低、电导率高、耐塑料封装过程中的导线扫线等优点而受到人们的关注。然而，铜具有较硬的性质，因此在连接过程中需要更加小心，以避免出现凹坑问题。针对这种情况，本文采用故障模式与影响分析(failure Mode and Effect Analysis, FMEA)技术对机器故障进行发现和分析，验证机器在使用铜线操作时的能力和面临的问题。此外，提出了在马来西亚一家半导体公司进行的基于故障类型和故障原因的改进计划的一般方法。研究结果表明，故障分析是了解机械性能和可靠性的一项重要工作。
{"title":"Failure analysis for Copper Wire Bonding process from machine perspective","authors":"Hasnida Abdul Samat, S. Kamaruddin, Ishak Abd Azid","doi":"10.1109/IEMT.2008.5507872","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507872","url":null,"abstract":"In fast changing and very competitive industry like semiconductor manufacturing, reliability or probability of failure always has been a crucial part in any processes and operation involving machine and equipment. One of many electronic manufacturing technologies is Wire Bond process, which entails a flexible and an accurate technology because of fast changing market demand for smaller electronic gadgets. Nature of wire bond process which is very delicate, usually makes any failures happen during this type of operation goes unnoticed for sometimes and this situation will cost the company a fortune. This paper aims to discuss equipment reliability based on failure occurrences in wire bond process using copper wire. Copper bonding has received attention because of its low cost, high electrical conductivity and resistance to wire sweep during plastic encapsulation. However, copper have hard properties thus more care is required during bonding as to avoid cratering problem. With the situation, this paper was written to find and analyze machine failure using Failure Mode and Effect Analysis (FMEA) technique to verify machine capability and problems faced when operating using Copper wire. Furthermore, general approach for improvement plan based on type of failure and failure causes are presented as conducted in a semiconductor company in Malaysia. The finding of the study provides evidence that failure analysis is an important task to be done in order to understand machine capability and reliability.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133366272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507896
K. H. Ang, K. Cheong, Azmi Abdul Malik, Siew Lang Lee, G. Omar, S. Lim, C. L. Lim, Danny Tan, Michael B C Khoo
Polyimides are used extensively in the semiconductor industry as passivation layers, interlayers and dielectrics because of their excellent properties. These properties include thermal stability, superior chemical resistance, high mechanical strength and low dielectric constant. Most polyimide used in the semiconductor industry is the negative-type photosensitive polyimide due to its direct patternability. The purpose of this paper is to study the effect of process time delay during the polyamic ester formation to the final imidized polyimide. Post Coat Delay (PCD) is the delay time after coating before undergoing exposing while Post Expose Delay (PED) is the delay time after exposing before undergoing development. Samples of imide coated on bare wafers with after cure thickness of 6 Em are used. The image from Microscope inspection shows that the sample that is processed immediately is different from those other samples. The results of the after cure thickness of polyimides show that all the samples are within specification limit. Fourier Transform Infra Red (FTIR) is used to check for the chemical bonding. All the samples are fully imidized without peaks indicating the existence of PAE precursor. The imidization rate is lower as the delay time increase for both PCD and PED. Further investigation need to be done to verified the results.
{"title":"A study of the process time effect to photosensitive polyimides","authors":"K. H. Ang, K. Cheong, Azmi Abdul Malik, Siew Lang Lee, G. Omar, S. Lim, C. L. Lim, Danny Tan, Michael B C Khoo","doi":"10.1109/IEMT.2008.5507896","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507896","url":null,"abstract":"Polyimides are used extensively in the semiconductor industry as passivation layers, interlayers and dielectrics because of their excellent properties. These properties include thermal stability, superior chemical resistance, high mechanical strength and low dielectric constant. Most polyimide used in the semiconductor industry is the negative-type photosensitive polyimide due to its direct patternability. The purpose of this paper is to study the effect of process time delay during the polyamic ester formation to the final imidized polyimide. Post Coat Delay (PCD) is the delay time after coating before undergoing exposing while Post Expose Delay (PED) is the delay time after exposing before undergoing development. Samples of imide coated on bare wafers with after cure thickness of 6 Em are used. The image from Microscope inspection shows that the sample that is processed immediately is different from those other samples. The results of the after cure thickness of polyimides show that all the samples are within specification limit. Fourier Transform Infra Red (FTIR) is used to check for the chemical bonding. All the samples are fully imidized without peaks indicating the existence of PAE precursor. The imidization rate is lower as the delay time increase for both PCD and PED. Further investigation need to be done to verified the results.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129175789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507865
Ervina Efzan Mhd Noor, A. B. Ismail, N. M. Sharif, T. Ariga, Zuhailawati Hussain
Due to the increase in the use of electronics devices within the industry, the usage of solder connections has increased. These is a concern that lead within the electronic products is considered toxic because lead has potential for leaching from landfills onto water sources and becoming a hazard to human health and surrounding environment. For this reason, replacing Sn-37Pb to free solder with low melting temperature is one of the most important issues in electronic industry. This is due to a demand on low temperature for interconnection and polymer based part component such as LCD display functionality availability at low temperature apply. In this paper, Bi-In-Sn system alloy was investigated as a potential candidate replacing Sn-37Pb. This study covers on solder characteristic such as melting temperature, thermal expansion and microstructure. Bi-In-Sn was prepared and melted in crucible. Solder was cleaned mechanical and chemical before characterized. DSC shows that, Bi-In-Sn system alloy give low melting temperature in range of 65-100°C. The addition of In to Bi-Sn system alloy lowered the melting temperature compared than Sn-37Pb. Lowest melting temperature ensures that the solder melts, forms a joint with the substrates, and re-solidifies within the shortest possible process time. From thermal expansion analysis, it was found that Bi-In-Sn gives good expansion properties to avoid mismatch between Cu pads and solder itself. EDX analysis indicated that, there are two obvious regions in Bi-In-Sn system alloy microstructure. Bright colour refers to BiIn rich phase region and dark colour refers to Sn rich phase region. BiIn rich phase region is higher compared to Sn rich phase in solder give good properties in terms of ductility.
{"title":"Characteristic of low temperature of Bi-In-Sn solder alloy","authors":"Ervina Efzan Mhd Noor, A. B. Ismail, N. M. Sharif, T. Ariga, Zuhailawati Hussain","doi":"10.1109/IEMT.2008.5507865","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507865","url":null,"abstract":"Due to the increase in the use of electronics devices within the industry, the usage of solder connections has increased. These is a concern that lead within the electronic products is considered toxic because lead has potential for leaching from landfills onto water sources and becoming a hazard to human health and surrounding environment. For this reason, replacing Sn-37Pb to free solder with low melting temperature is one of the most important issues in electronic industry. This is due to a demand on low temperature for interconnection and polymer based part component such as LCD display functionality availability at low temperature apply. In this paper, Bi-In-Sn system alloy was investigated as a potential candidate replacing Sn-37Pb. This study covers on solder characteristic such as melting temperature, thermal expansion and microstructure. Bi-In-Sn was prepared and melted in crucible. Solder was cleaned mechanical and chemical before characterized. DSC shows that, Bi-In-Sn system alloy give low melting temperature in range of 65-100°C. The addition of In to Bi-Sn system alloy lowered the melting temperature compared than Sn-37Pb. Lowest melting temperature ensures that the solder melts, forms a joint with the substrates, and re-solidifies within the shortest possible process time. From thermal expansion analysis, it was found that Bi-In-Sn gives good expansion properties to avoid mismatch between Cu pads and solder itself. EDX analysis indicated that, there are two obvious regions in Bi-In-Sn system alloy microstructure. Bright colour refers to BiIn rich phase region and dark colour refers to Sn rich phase region. BiIn rich phase region is higher compared to Sn rich phase in solder give good properties in terms of ductility.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132037366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507858
Deng Bin, Shao Peng, Wang Yue
This paper describes a new build-in-vision (BIV) and vertical laser cutting method to improve capacity of laser deflash system with maintaining 3 mils lead flash remains in miniature package such as SOD923. This equipment is developed by Leshan-Phoenix Semiconductor Co. Ltd. (LPS) and supplier. The traditional laser deflash system is equipped with pre-vision for package positioning, post-vision for lead frame positioning and laser cutting per transferred data from vision system. In order to avoid more than 3 mils tiny lead mold flash which was induced by blocking or shading laser beam couple with units that locating at far end from laser center focus point. Therefore, lead frame was subjected to “Three Indexes” using slantwise cutting concept. However, it takes longer cycle time and becomes bottleneck. The new laser deflash system is equipped with new designed build-in-vision and special telecentric laser beam focus system. Build-in-vision is consists of vision camera, lighting and special designed coupling mirror which is capable of penetrating through both vision lighting and laser beam. This design assures vision positioning inspection and laser cutting simultaneously. A special tele-centric lens was designed to change the angle of laser beam for controlling the reflection of laser beam away from focus-centre point. This is to ensure laser beam vertically in the whole laser cutting field. The new system has the capability with build-in-vision and vertical laser cutting design shows significant improvement on mechanical transfer time and laser cutting time.
{"title":"Breakthrough of laser deflash system to improve productivity","authors":"Deng Bin, Shao Peng, Wang Yue","doi":"10.1109/IEMT.2008.5507858","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507858","url":null,"abstract":"This paper describes a new build-in-vision (BIV) and vertical laser cutting method to improve capacity of laser deflash system with maintaining 3 mils lead flash remains in miniature package such as SOD923. This equipment is developed by Leshan-Phoenix Semiconductor Co. Ltd. (LPS) and supplier. The traditional laser deflash system is equipped with pre-vision for package positioning, post-vision for lead frame positioning and laser cutting per transferred data from vision system. In order to avoid more than 3 mils tiny lead mold flash which was induced by blocking or shading laser beam couple with units that locating at far end from laser center focus point. Therefore, lead frame was subjected to “Three Indexes” using slantwise cutting concept. However, it takes longer cycle time and becomes bottleneck. The new laser deflash system is equipped with new designed build-in-vision and special telecentric laser beam focus system. Build-in-vision is consists of vision camera, lighting and special designed coupling mirror which is capable of penetrating through both vision lighting and laser beam. This design assures vision positioning inspection and laser cutting simultaneously. A special tele-centric lens was designed to change the angle of laser beam for controlling the reflection of laser beam away from focus-centre point. This is to ensure laser beam vertically in the whole laser cutting field. The new system has the capability with build-in-vision and vertical laser cutting design shows significant improvement on mechanical transfer time and laser cutting time.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128469524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507788
I. Abdullah, I. Ahmad, M. Talib, M. N. Kamarudin
Warpage is greatly affected by package geometries, such as dimension of matrix array, pad, die and passive components as well as molding compound properties. It is also related to thermal mismatch i.e. coefficient of thermal expansion (CTE) and reliability of passive components in the package. So in order to reduce warpage occurrence in all packages, it is proposed that the combination of CTE properties of QFN packages layer need to be optimized. This study used finite element method (FEM) to perform extensive structural analysis of QFN package designs with respect to different combination of thermal properties and the possible occurrence of warpage. The results obtained were then verified with experimental data. The FEA method was able to simulate the warpage occurrence and the statistical method was able to identify the optimal combination of thermal properties of the layers. It was also found that the optimum combination of CTE properties will reduce the probability of the warpage occurrence.
{"title":"Reduction of warpage occurrence on stack-die QFN using FEA and statistical method","authors":"I. Abdullah, I. Ahmad, M. Talib, M. N. Kamarudin","doi":"10.1109/IEMT.2008.5507788","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507788","url":null,"abstract":"Warpage is greatly affected by package geometries, such as dimension of matrix array, pad, die and passive components as well as molding compound properties. It is also related to thermal mismatch i.e. coefficient of thermal expansion (CTE) and reliability of passive components in the package. So in order to reduce warpage occurrence in all packages, it is proposed that the combination of CTE properties of QFN packages layer need to be optimized. This study used finite element method (FEM) to perform extensive structural analysis of QFN package designs with respect to different combination of thermal properties and the possible occurrence of warpage. The results obtained were then verified with experimental data. The FEA method was able to simulate the warpage occurrence and the statistical method was able to identify the optimal combination of thermal properties of the layers. It was also found that the optimum combination of CTE properties will reduce the probability of the warpage occurrence.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507773
A. Ourdjini, M. A. Azmah Hanim, I. Aisha, Y. T. Chin
Solder joint reliability is dependent on both thickness and morphology of the intermetallics that form and grow at the solder joint interface during soldering and subsequent thermal ageing and examining the morphology of these intermetallics is of great importance. The focus of this paper is to present experimental results of a comprehensive study of the interfacial reactions during soldering of Sn-Ag-Cu lead-free solders on copper (Cu), immersion silver (ImAg), electroless nickel/ immersion gold (ENIG) and electroless nickel/ electroless palladium/ immersion gold (ENEPIG) surface finishes. Using scanning electron microscopy detailed a study of the 3-D morphology and grain size of the intermetallics was conducted. The results showed that when soldering on ENIG and ENEPIG finishes several morphologies of intermetallics with different grain sizes form at the solder joint interface compared to a single intermetallic morphology that forms when soldering on copper and immersion silver. An attempt was made to discuss the effect of several factors that may have an influence on the type of morphology the intermetallics may grow into. The results obtained in the present investigation also revealed that the technique of removing the solder by deep etching to examine the morphology of intermetallics is a convenient and efficient method to investigate the intermetallics formed at the solder joints.
{"title":"Effect of surface finish metallurgy on intermetallic compounds during soldering with tin-silver-copper solders","authors":"A. Ourdjini, M. A. Azmah Hanim, I. Aisha, Y. T. Chin","doi":"10.1109/IEMT.2008.5507773","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507773","url":null,"abstract":"Solder joint reliability is dependent on both thickness and morphology of the intermetallics that form and grow at the solder joint interface during soldering and subsequent thermal ageing and examining the morphology of these intermetallics is of great importance. The focus of this paper is to present experimental results of a comprehensive study of the interfacial reactions during soldering of Sn-Ag-Cu lead-free solders on copper (Cu), immersion silver (ImAg), electroless nickel/ immersion gold (ENIG) and electroless nickel/ electroless palladium/ immersion gold (ENEPIG) surface finishes. Using scanning electron microscopy detailed a study of the 3-D morphology and grain size of the intermetallics was conducted. The results showed that when soldering on ENIG and ENEPIG finishes several morphologies of intermetallics with different grain sizes form at the solder joint interface compared to a single intermetallic morphology that forms when soldering on copper and immersion silver. An attempt was made to discuss the effect of several factors that may have an influence on the type of morphology the intermetallics may grow into. The results obtained in the present investigation also revealed that the technique of removing the solder by deep etching to examine the morphology of intermetallics is a convenient and efficient method to investigate the intermetallics formed at the solder joints.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129824232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507864
Lai Zheng Bo, N. Kamsah, L. W. Keat, M. Tamin
A thorough understanding of the mechanics of lead-free solder joint in a ball grid array (BGA) assembly under expected operating conditions is essential in developing reliable life prediction models. In this respect, accurate deformation response of Sn-4Ag-0.5Cu (SAC405) solder under varying temperature cycles and straining rates is established using unified inelastic strain theory. The mechanics of the solder joint is then quantified through finite element modeling of a typical BGA assembly. The 3D quarter-model of the test assembly consists of silicon die, FR-4 substrate and printed circuit board (PCB), copper traces, intermetallics layer (IMC) and SAC405 solder joints in an area array. Reflow temperature profile consists of cooling from the assumed stress-free temperature of 220 to 25°C. Temperature cycles in the range between 125 and -40°C with dwell time at peak temperature levels are simulated. Results show that residual von Mises stress of 48.7 MPa and the corresponding inelastic strain of 0.031 are predicted in the critical solder joint at 25°C following solder reflow cooling. Additional inelastic strains accumulates continuously in the solder throughout the temperature cycles. Solder stress relaxation with accompanying inelastic strain occurs during dwell-time periods at both -40 and 125°C due viscoplastic and creep effects, respectively. In the critical solder joint, both high stress and strain gradients are localized in a small edge region at the solder-IMC interface near the component (SMD) side of the assembly. A new fatigue life model with unified inelastic strain theory defined for SAC405 solder joints is proposed based on accumulated inelastic strains and plastic work density of the critical solder joint.
{"title":"Mechanics of Sn-4Ag-0.5Cu solder joints in a ball grid array assembly during reflow and temperature cycles","authors":"Lai Zheng Bo, N. Kamsah, L. W. Keat, M. Tamin","doi":"10.1109/IEMT.2008.5507864","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507864","url":null,"abstract":"A thorough understanding of the mechanics of lead-free solder joint in a ball grid array (BGA) assembly under expected operating conditions is essential in developing reliable life prediction models. In this respect, accurate deformation response of Sn-4Ag-0.5Cu (SAC405) solder under varying temperature cycles and straining rates is established using unified inelastic strain theory. The mechanics of the solder joint is then quantified through finite element modeling of a typical BGA assembly. The 3D quarter-model of the test assembly consists of silicon die, FR-4 substrate and printed circuit board (PCB), copper traces, intermetallics layer (IMC) and SAC405 solder joints in an area array. Reflow temperature profile consists of cooling from the assumed stress-free temperature of 220 to 25°C. Temperature cycles in the range between 125 and -40°C with dwell time at peak temperature levels are simulated. Results show that residual von Mises stress of 48.7 MPa and the corresponding inelastic strain of 0.031 are predicted in the critical solder joint at 25°C following solder reflow cooling. Additional inelastic strains accumulates continuously in the solder throughout the temperature cycles. Solder stress relaxation with accompanying inelastic strain occurs during dwell-time periods at both -40 and 125°C due viscoplastic and creep effects, respectively. In the critical solder joint, both high stress and strain gradients are localized in a small edge region at the solder-IMC interface near the component (SMD) side of the assembly. A new fatigue life model with unified inelastic strain theory defined for SAC405 solder joints is proposed based on accumulated inelastic strains and plastic work density of the critical solder joint.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123329362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507884
N. Annamalai, Narendra Kumar Patel, Subramaniam Muthukarapan
Preventive maintenance (PM) is a crucial activity to ensure the stability and performance of a tool. It has lead to long hour and tedious activity on SHBI (Self Heat Burn-In). SHBI is a tool used to support the Burn-In process. SHBI carries several long hour PM task which also requires some conversion activities. This has been leading to a total >15% weekly capacity loss. This paper will discuss on how both the unproductive long hour activities have been analyzed through theory of innovative problem solving (TRIZ) methodology.
{"title":"Radical breakthrough innovative solution in SHBI PM optimization using TRIZ","authors":"N. Annamalai, Narendra Kumar Patel, Subramaniam Muthukarapan","doi":"10.1109/IEMT.2008.5507884","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507884","url":null,"abstract":"Preventive maintenance (PM) is a crucial activity to ensure the stability and performance of a tool. It has lead to long hour and tedious activity on SHBI (Self Heat Burn-In). SHBI is a tool used to support the Burn-In process. SHBI carries several long hour PM task which also requires some conversion activities. This has been leading to a total >15% weekly capacity loss. This paper will discuss on how both the unproductive long hour activities have been analyzed through theory of innovative problem solving (TRIZ) methodology.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124239551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507775
L. Chan, Kwan Yiu Fai, Y. C. Ho
Improvement of electronic device packaging reliability, more specifically moisture attack resistance (commonly known as moisture sensitivity level or MSL), has been a hot topic in recent years due to the increase in solder reflow temperature for lead-free solder. In preceding failure mode analysis, delamination between lead frame and encapsulation molding compound (EMC) interface plays an important role. Thus a modified brown oxide treatment was developed and applied onto the copper lead frame surface, which is field proven an effective way to elevate package MSL performance. Comparing with typical brown oxide treatment developed in older days for use in printed circuit board (PCB), this modified treatment was specially for use in copper lead frame so that it not only enhances the adhesion with die-attach epoxy glue and EMC, but also leaving a clean silver plating surface for wire bonding.
{"title":"Modified brown oxide treatment as an adhesion promoter for copper lead frame in plastic integrated-circuit packages","authors":"L. Chan, Kwan Yiu Fai, Y. C. Ho","doi":"10.1109/IEMT.2008.5507775","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507775","url":null,"abstract":"Improvement of electronic device packaging reliability, more specifically moisture attack resistance (commonly known as moisture sensitivity level or MSL), has been a hot topic in recent years due to the increase in solder reflow temperature for lead-free solder. In preceding failure mode analysis, delamination between lead frame and encapsulation molding compound (EMC) interface plays an important role. Thus a modified brown oxide treatment was developed and applied onto the copper lead frame surface, which is field proven an effective way to elevate package MSL performance. Comparing with typical brown oxide treatment developed in older days for use in printed circuit board (PCB), this modified treatment was specially for use in copper lead frame so that it not only enhances the adhesion with die-attach epoxy glue and EMC, but also leaving a clean silver plating surface for wire bonding.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122756731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507809
K. Kanlayasiri
This research was aimed to study effects of indium (In) addition on solidus and liquidus temperatures, wetting time, wetting force, and microhardness of Sn-0.3Ag-0.7Cu lead-free solder alloy. It was found that In had a strong influence on these properties of Sn-0.3Ag-0.7Cu. Solidus and liquidus temperatures of the solder alloys was lowered as the In content was increased. However, In addition increased the melting range between solidus and liquidus temperatures. Wetting time of the solder alloy was reduced by the addition of In while the wetting force was increased with the increase of In content. Microhardness of Sn-0.3Ag-0.7Cu was increased by adding In into the solder alloy. With the addition of In, the Sn-rich phase was smaller in size, and the intermetallic compounds were more uniformly distributed.
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