Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614540
C. Liu, F. Liu, Q. Luo, P. Huang, X. X. Xu, H. Lv, Y. Zhao, X.Y. Liu, J. Kang
Based on the density functional theory (DFT) calculations, a new mechanism about the oxygen vacancies(Vo) in the HfO2-based ferroelectric devices is presented. In this mechanism, the Vo in m-phase HfO2 not only serve as the electron traps but also emerge ferroelectricity besides the known o-phase HfO2. And the increased remanent polarization during the “wake-up” process is mainly attributed to this part of Vo-m-phase HfO2 ferroelectric cells. Based on the new mechanism, a Kinetic Monte Carlo (KMC) simulator is developed to quantify the typical electric field cycling behaviors observed in the HfO2-based ferroelectric devices, including the wake-up, fatigue, split-up, and breakdown effects. This new understanding establishes relationship between the Vo and the cycling behaviors, and further shows the connection between the dopant and the wake-up characteristics of HfO2-based ferroelectric device.
{"title":"Role of Oxygen Vacancies in Electric Field Cycling Behaviors of Ferroelectric Hafnium Oxide","authors":"C. Liu, F. Liu, Q. Luo, P. Huang, X. X. Xu, H. Lv, Y. Zhao, X.Y. Liu, J. Kang","doi":"10.1109/IEDM.2018.8614540","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614540","url":null,"abstract":"Based on the density functional theory (DFT) calculations, a new mechanism about the oxygen vacancies(Vo) in the HfO2-based ferroelectric devices is presented. In this mechanism, the Vo in m-phase HfO2 not only serve as the electron traps but also emerge ferroelectricity besides the known o-phase HfO2. And the increased remanent polarization during the “wake-up” process is mainly attributed to this part of Vo-m-phase HfO2 ferroelectric cells. Based on the new mechanism, a Kinetic Monte Carlo (KMC) simulator is developed to quantify the typical electric field cycling behaviors observed in the HfO2-based ferroelectric devices, including the wake-up, fatigue, split-up, and breakdown effects. This new understanding establishes relationship between the Vo and the cycling behaviors, and further shows the connection between the dopant and the wake-up characteristics of HfO2-based ferroelectric device.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128406046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614702
Fei Mo, Yusaku Tagawa, T. Saraya, T. Hiramoto, M. Kobayashi
We have investigated scalability and design guideline of HfO2-bascd Ferroelectric Tunnel Junction (FTJ) memory by employing numerical simulation which is based on Non-Equilibrium Green Function (NEGF) method and self-consistent potential, and calibrated by our experimental FTJ data, for the first time. Metal-Ferroelectric-Insulator-semiconductor (MFIS) FTJ shows a higher TER than Metal-Ferroelectric-Insulator-Metal (MFIM) FTJ with almost the same read current because of the large asymmetry of dielectric screening property in top and bottom electrodes. High read current can be obtained by thinner layers while high TER and low depolarizing field are maintained by adjusting bottom semiconductor electrode property. Based on these results, a guideline for designing MFIS structure FTJ to achieve high read current and high TER has been proposed. We have shown a potential for scaling the FTJ down to sub-20 nm diameter.
{"title":"Scalability Study on Fcrroclcctric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method with Self-consistent Potential","authors":"Fei Mo, Yusaku Tagawa, T. Saraya, T. Hiramoto, M. Kobayashi","doi":"10.1109/IEDM.2018.8614702","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614702","url":null,"abstract":"We have investigated scalability and design guideline of HfO2-bascd Ferroelectric Tunnel Junction (FTJ) memory by employing numerical simulation which is based on Non-Equilibrium Green Function (NEGF) method and self-consistent potential, and calibrated by our experimental FTJ data, for the first time. Metal-Ferroelectric-Insulator-semiconductor (MFIS) FTJ shows a higher TER than Metal-Ferroelectric-Insulator-Metal (MFIM) FTJ with almost the same read current because of the large asymmetry of dielectric screening property in top and bottom electrodes. High read current can be obtained by thinner layers while high TER and low depolarizing field are maintained by adjusting bottom semiconductor electrode property. Based on these results, a guideline for designing MFIS structure FTJ to achieve high read current and high TER has been proposed. We have shown a potential for scaling the FTJ down to sub-20 nm diameter.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1976 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128189039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614696
M. A. Pourghaderi, A. Pham, S. Kim, Hyein Chung, Zhengping Jiang, H. Ilatikhameneh, Hong-hyun Park, Seonghoon Jin, Jongchol Kim, Won-Young Chung, U. Kwon, W. Choi, Dae Sin Kim, S. Maeda
Deterministic Boltzmann-transport solver has been integrated in performance analysis of logic cells. Employing universal-swing-factor (USF) approach, our setup accurately entails quasi-ballistic transport effects. The injection current and carrier mean free path (MFP) have been extracted for various channel dimensions and interface qualities. The resulting database is used to study candidate architecture for logic nodes. In particular, performance of ring oscillator (RO) with tapered FinFET is presented. For a given junction profile and contact-poly-pitch (CPP), the optimum gate-length (Lg), spacer thickness and contact-CD (CCD) are evaluated. The feasible gain by lowering the spacer k-value and contact resistance is also reported.
确定性玻尔兹曼输运求解器已被集成到逻辑单元的性能分析中。采用通用摆动因子(USF)方法，我们的设置准确地包含准弹道输运效应。提取了不同通道尺寸和界面质量的注入电流和载流子平均自由程(MFP)。得到的数据库用于研究逻辑节点的候选体系结构。重点介绍了锥形FinFET环形振荡器(RO)的性能。对于给定的结型和接触-多节距(CPP)，评估了最佳栅长(Lg)、间隔厚度和接触- cd (CCD)。本文还报道了降低间隔k值和接触电阻的可行增益。
{"title":"Universal Swing Factor Approach For Performance Analysis Of Logic Nodes","authors":"M. A. Pourghaderi, A. Pham, S. Kim, Hyein Chung, Zhengping Jiang, H. Ilatikhameneh, Hong-hyun Park, Seonghoon Jin, Jongchol Kim, Won-Young Chung, U. Kwon, W. Choi, Dae Sin Kim, S. Maeda","doi":"10.1109/IEDM.2018.8614696","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614696","url":null,"abstract":"Deterministic Boltzmann-transport solver has been integrated in performance analysis of logic cells. Employing universal-swing-factor (USF) approach, our setup accurately entails quasi-ballistic transport effects. The injection current and carrier mean free path (MFP) have been extracted for various channel dimensions and interface qualities. The resulting database is used to study candidate architecture for logic nodes. In particular, performance of ring oscillator (RO) with tapered FinFET is presented. For a given junction profile and contact-poly-pitch (CPP), the optimum gate-length (Lg), spacer thickness and contact-CD (CCD) are evaluated. The feasible gain by lowering the spacer k-value and contact resistance is also reported.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129785940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614708
Chih-Chao Yang, Tung-Ying Hsieh, Po-Tsang Huang, Kuan-Neng Chen, Wan-Chi Wu, Shih-Wei Chen, Chia-He Chang, C. Shen, J. Shieh, C. Hu, Meng-Chyi Wu, W. Yeh
A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO2. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 µA/µm and p-type: $385 mu mathrm{A}/mu mathrm{m}$), and high Ion/Ioff (>106). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.
本文介绍了一种位置控制晶粒技术，用于在二氧化硅上制造 BEOL 单片 3D FinFET 集成电路。由此制造出的无晶粒边界硅 FinFET 具有陡峭的次阈值摆幅（385 美元/mathrm{A}/mathrm{m}$）和高离子/离子关断（>106）。根据模拟，层间电介质的厚度起着重要作用，其厚度应大于 250nm，以便顺序脉冲激光结晶过程不会将底部器件和互连器件加热到 400 °C 以上。
{"title":"Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits","authors":"Chih-Chao Yang, Tung-Ying Hsieh, Po-Tsang Huang, Kuan-Neng Chen, Wan-Chi Wu, Shih-Wei Chen, Chia-He Chang, C. Shen, J. Shieh, C. Hu, Meng-Chyi Wu, W. Yeh","doi":"10.1109/IEDM.2018.8614708","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614708","url":null,"abstract":"A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO<inf>2</inf>. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 µA/µm and p-type: <tex>$385 mu mathrm{A}/mu mathrm{m}$</tex>), and high I<inf>on</inf>/I<inf>off</inf> (>10<sup>6</sup>). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129814424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614586
Z. Wang, Brian Crafton, Jorge Gomez, R. Xu, Aileen Luo, Z. Krivokapic, L. Martin, S. Datta, A. Raychowdhury, A. Khan
We report the first experimental demonstration of ferroelectric field-effect transistor (FEFET) based spiking neurons. A unique feature of the ferroelectric (FE) neuron demonstrated herein is the availability of both excitatory and inhibitory input connections in the compact 1T-1FEFET structure, which is also reported for the first time for any neuron implementations. Such dual neuron functionality is a key requirement for bio-mimetic neural networks and represents a breakthrough for implementation of the third generation spiking neural networks (SNNs)—also reported herein for unsupervised learning and clustering on real world data for the first time. The key to our demonstration is the careful design of two important device level features: (1) abrupt hysteretic transitions of the FEFET with no stable states therein, and (2) the dynamic tunability of the FEFET hysteresis by bias conditions which allows for the inhibition functionality. Experimentally calibrated, multi-domain Preisach based FEFET models were used to accurately simulate the FE neurons and project their performance at scaled nodes. We also implement an SNN for unsupervised clustering and benchmark the network performance across analog CMOS and emerging technologies and observe (1) unification of excitatory and inhibitory neural connections, (2) STDP based learning, (3) lowest reported power (3.6nW) during classification, and (4) a classification accuracy of 93%.
{"title":"Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering","authors":"Z. Wang, Brian Crafton, Jorge Gomez, R. Xu, Aileen Luo, Z. Krivokapic, L. Martin, S. Datta, A. Raychowdhury, A. Khan","doi":"10.1109/IEDM.2018.8614586","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614586","url":null,"abstract":"We report the first experimental demonstration of ferroelectric field-effect transistor (FEFET) based spiking neurons. A unique feature of the ferroelectric (FE) neuron demonstrated herein is the availability of both excitatory and inhibitory input connections in the compact 1T-1FEFET structure, which is also reported for the first time for any neuron implementations. Such dual neuron functionality is a key requirement for bio-mimetic neural networks and represents a breakthrough for implementation of the third generation spiking neural networks (SNNs)—also reported herein for unsupervised learning and clustering on real world data for the first time. The key to our demonstration is the careful design of two important device level features: (1) abrupt hysteretic transitions of the FEFET with no stable states therein, and (2) the dynamic tunability of the FEFET hysteresis by bias conditions which allows for the inhibition functionality. Experimentally calibrated, multi-domain Preisach based FEFET models were used to accurately simulate the FE neurons and project their performance at scaled nodes. We also implement an SNN for unsupervised clustering and benchmark the network performance across analog CMOS and emerging technologies and observe (1) unification of excitatory and inhibitory neural connections, (2) STDP based learning, (3) lowest reported power (3.6nW) during classification, and (4) a classification accuracy of 93%.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129933673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614642
Z. Zhou, P. Huang, Y. Xiang, W. Shen, Y. Zhao, Y. Feng, B. Gao, H. Wu, H. Qian, L. Liu, X. Zhang, X. Liu, J. Kang
For the first time, we propose a new hardware implementation approach which can utilize the non-linear synaptic cells to build a Binarized-Neural-Networks (BNNs) for online training. A 2T2R-based synaptic cell is designed and demonstrated by the fabricated RRAM array to achieve the basic functions of synapse in BNNs: binary weight (sign ($W$)) reading and analog weight updating $(W+Delta W)$. The performance of BNNs based on 2T2R synaptic cells is evaluated by MNIST, and the recognition accuracy of 97.4% can be achieved. A novel refresh operation is proposed to enhance the network performance.
{"title":"A new hardware implementation approach of BNNs based on nonlinear 2T2R synaptic cell","authors":"Z. Zhou, P. Huang, Y. Xiang, W. Shen, Y. Zhao, Y. Feng, B. Gao, H. Wu, H. Qian, L. Liu, X. Zhang, X. Liu, J. Kang","doi":"10.1109/IEDM.2018.8614642","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614642","url":null,"abstract":"For the first time, we propose a new hardware implementation approach which can utilize the non-linear synaptic cells to build a Binarized-Neural-Networks (BNNs) for online training. A 2T2R-based synaptic cell is designed and demonstrated by the fabricated RRAM array to achieve the basic functions of synapse in BNNs: binary weight (sign ($W$)) reading and analog weight updating $(W+Delta W)$. The performance of BNNs based on 2T2R synaptic cells is evaluated by MNIST, and the recognition accuracy of 97.4% can be achieved. A novel refresh operation is proposed to enhance the network performance.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130147903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614633
M. Ghatge, G. Walters, Toshikazu Nishida, R. Tabrizian
This paper reports, for the first time, on a 10nm hafnium-zirconium oxide (Hf0.5Zr0.5O2) (HZO) piezoelectric transducer for nano-electromechanical systems (NEMS). The super-thin HZO films are engineered through atomic-level stacking, capping with titanium nitride (TiN) electrodes, and proper thermo-mechanical treatment, to realize ferroelectric transducers with large piezoelectric properties. The developed 10nm transducer is used for excitation of a silicon-based multi-morph nano-mechanical resonator, with an overall thickness of ∼350nm, at ∼4MHz. The developed resonator, along with 120nm aluminum-nitride (AlN) transduced counterparts, are also used as test-vehicles to characterize ferroelectric and piezoelectric properties. Benefiting from large piezoelectric coefficient $(e_{31,HZO}approx 2.3e_{31AlN})$, fully conformal deposition, and CMOS-compatibility, ALD-deposited 10nm HZO transducer paves the way for realization of truly monolithic cm- and mm-wave RF front-ends for the emerging 5G wireless communication systems, and extreme / 3D integration of NEMS sensors and actuators.
{"title":"A Nano-Mechanical Resonator with 10nm Hafnium-Zirconium Oxide Ferroelectric Transducer","authors":"M. Ghatge, G. Walters, Toshikazu Nishida, R. Tabrizian","doi":"10.1109/IEDM.2018.8614633","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614633","url":null,"abstract":"This paper reports, for the first time, on a 10nm hafnium-zirconium oxide (Hf0.5Zr0.5O2) (HZO) piezoelectric transducer for nano-electromechanical systems (NEMS). The super-thin HZO films are engineered through atomic-level stacking, capping with titanium nitride (TiN) electrodes, and proper thermo-mechanical treatment, to realize ferroelectric transducers with large piezoelectric properties. The developed 10nm transducer is used for excitation of a silicon-based multi-morph nano-mechanical resonator, with an overall thickness of ∼350nm, at ∼4MHz. The developed resonator, along with 120nm aluminum-nitride (AlN) transduced counterparts, are also used as test-vehicles to characterize ferroelectric and piezoelectric properties. Benefiting from large piezoelectric coefficient $(e_{31,HZO}approx 2.3e_{31AlN})$, fully conformal deposition, and CMOS-compatibility, ALD-deposited 10nm HZO transducer paves the way for realization of truly monolithic cm- and mm-wave RF front-ends for the emerging 5G wireless communication systems, and extreme / 3D integration of NEMS sensors and actuators.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614545
G. Fettweis, K. Leo, B. Voit, U. Schneider, L. Scheuvens
Electronics is a huge driver for economic success of today's societies. cfaed, the German Cluster of Excellence located in Dresden (Germany), aims at pushing the boundaries of electronics into unknown grounds. This includes not only current electronics but also scientist's and engineer's projection of how the electronics landscape will look like in the future. We pursue an approach that connects all layers from new materials to new system design (vertical) as well as across our Research Routes (horizontal) and ensure coherence through adequate measures. cfaed is centered at one location which, combined with our unique approach, places it above the highly funded Competitive Landscape.
{"title":"Venturing Electronics into Unknown Grounds","authors":"G. Fettweis, K. Leo, B. Voit, U. Schneider, L. Scheuvens","doi":"10.1109/IEDM.2018.8614545","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614545","url":null,"abstract":"Electronics is a huge driver for economic success of today's societies. cfaed, the German Cluster of Excellence located in Dresden (Germany), aims at pushing the boundaries of electronics into unknown grounds. This includes not only current electronics but also scientist's and engineer's projection of how the electronics landscape will look like in the future. We pursue an approach that connects all layers from new materials to new system design (vertical) as well as across our Research Routes (horizontal) and ensure coherence through adequate measures. cfaed is centered at one location which, combined with our unique approach, places it above the highly funded Competitive Landscape.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132373903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614513
J.Y. Wu, Y.S. Chen, W. Khwa, S. Yu, T. Wang, J. Tseng, Y. Chih, Carlos H. Díaz
An embedded phase change memory technology in 40nm low-power logic platform is demonstrated with minimal added process complexity - two non-critical additional masks over standard logic. Specially designed hard mask and etching process was used to achieve 50% shrinkage of the memory cell bottom electrode dimension with same lithography tooling as the 40nm logic platform. Bottom electrode CD shrinkage along with optimization of the electrode materials in terms of electrical and thermal conductivity enabled significant (∼4x) write current reduction attaining competitive levels of $sim 300 mumathrm{A}$ at 40nm BE CD. Embedded PCM cells reported in this work demonstrated over 100x memory window - (RESET/SET resistance switching ratio), over 200k cycling endurance with extrapolated 10 year retention at 120 °C. In this work not only large switching resistance ratios but also highly-controllable resistance values that are almost independent of the PCM starting resistance state are presented along with the corresponding programing pulse requirements. The switching resistance ratio and resistance value controllability are key features for neural network and compute-in-memory applications. In this work, their benefits on design margins for energy efficient high-density binary neural network for inference applications aiming accuracy levels of well over 90% is asserted over an MNIST dataset.
在40nm低功耗逻辑平台上演示了一种嵌入式相变存储技术，其增加的工艺复杂性最小-在标准逻辑上增加了两个非关键掩模。采用特别设计的硬掩膜和蚀刻工艺，达到50% shrinkage of the memory cell bottom electrode dimension with same lithography tooling as the 40nm logic platform. Bottom electrode CD shrinkage along with optimization of the electrode materials in terms of electrical and thermal conductivity enabled significant (∼4x) write current reduction attaining competitive levels of $sim 300 mumathrm{A}$ at 40nm BE CD. Embedded PCM cells reported in this work demonstrated over 100x memory window - (RESET/SET resistance switching ratio), over 200k cycling endurance with extrapolated 10 year retention at 120 °C. In this work not only large switching resistance ratios but also highly-controllable resistance values that are almost independent of the PCM starting resistance state are presented along with the corresponding programing pulse requirements. The switching resistance ratio and resistance value controllability are key features for neural network and compute-in-memory applications. In this work, their benefits on design margins for energy efficient high-density binary neural network for inference applications aiming accuracy levels of well over 90% is asserted over an MNIST dataset.
{"title":"A 40nm Low-Power Logic Compatible Phase Change Memory Technology","authors":"J.Y. Wu, Y.S. Chen, W. Khwa, S. Yu, T. Wang, J. Tseng, Y. Chih, Carlos H. Díaz","doi":"10.1109/IEDM.2018.8614513","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614513","url":null,"abstract":"An embedded phase change memory technology in 40nm low-power logic platform is demonstrated with minimal added process complexity - two non-critical additional masks over standard logic. Specially designed hard mask and etching process was used to achieve 50% shrinkage of the memory cell bottom electrode dimension with same lithography tooling as the 40nm logic platform. Bottom electrode CD shrinkage along with optimization of the electrode materials in terms of electrical and thermal conductivity enabled significant (∼4x) write current reduction attaining competitive levels of $sim 300 mumathrm{A}$ at 40nm BE CD. Embedded PCM cells reported in this work demonstrated over 100x memory window - (RESET/SET resistance switching ratio), over 200k cycling endurance with extrapolated 10 year retention at 120 °C. In this work not only large switching resistance ratios but also highly-controllable resistance values that are almost independent of the PCM starting resistance state are presented along with the corresponding programing pulse requirements. The switching resistance ratio and resistance value controllability are key features for neural network and compute-in-memory applications. In this work, their benefits on design margins for energy efficient high-density binary neural network for inference applications aiming accuracy levels of well over 90% is asserted over an MNIST dataset.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132411876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/iedm.2018.8614592
L. Kouwenhoven
We present an overview of Majorana qubits based on one-dimensional semiconducting nanowires partially covered with a conventional superconductor. Majorana zero modes emerge at the wire ends when this hybrid system transitions from a conventional superconducting phase to a topological phase, in general occurring on increasing a magnetic field. For sufficiently long wires different Majoranas are fully independent and Majorana-based qubit states become topologically protected, which make them insensitive to local sources of noise. We present qubit designs, materials and device development and ongoing experimental efforts.
{"title":"Majorana Qubits","authors":"L. Kouwenhoven","doi":"10.1109/iedm.2018.8614592","DOIUrl":"https://doi.org/10.1109/iedm.2018.8614592","url":null,"abstract":"We present an overview of Majorana qubits based on one-dimensional semiconducting nanowires partially covered with a conventional superconductor. Majorana zero modes emerge at the wire ends when this hybrid system transitions from a conventional superconducting phase to a topological phase, in general occurring on increasing a magnetic field. For sufficiently long wires different Majoranas are fully independent and Majorana-based qubit states become topologically protected, which make them insensitive to local sources of noise. We present qubit designs, materials and device development and ongoing experimental efforts.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130947713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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