Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614675
M. Vinet, L. Hutin, B. Bertrand, S. Barraud, J. Hartmann, Y.-J. Kim, V. Mazzocchi, A. Amisse, H. Bohuslavskyi, L. Bourdet, A. Crippa, X. Jehl, R. Maurand, Y. Niquet, M. Sanquer, B. Venitucci, B. Jadot, E. Chanrion, P. Mortemousque, C. Spence, M. Urdampilleta, S. D. Franceschi, T. Meunier
We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.
{"title":"Towards scalable silicon quantum computing","authors":"M. Vinet, L. Hutin, B. Bertrand, S. Barraud, J. Hartmann, Y.-J. Kim, V. Mazzocchi, A. Amisse, H. Bohuslavskyi, L. Bourdet, A. Crippa, X. Jehl, R. Maurand, Y. Niquet, M. Sanquer, B. Venitucci, B. Jadot, E. Chanrion, P. Mortemousque, C. Spence, M. Urdampilleta, S. D. Franceschi, T. Meunier","doi":"10.1109/IEDM.2018.8614675","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614675","url":null,"abstract":"We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131417384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614520
Yi-Pei Tsai, J. Shih, Y. King, C. Lin
A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.
{"title":"7nm FinFET Plasma Charge Recording Device","authors":"Yi-Pei Tsai, J. Shih, Y. King, C. Lin","doi":"10.1109/IEDM.2018.8614520","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614520","url":null,"abstract":"A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132360156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614698
J. Shin, Yeonjoo Jeong, Mohammed Affan Zidan, Qiwen Wang, Wei D. Lu
Simulated annealing (SA) was successfully implemented and accelerated by in-memory computing hardware/software package using RRAM crossbar arrays to solve a spin glass problem. Ta2O5-based RRAM array and stochastic Cu-based CBRAM devices were utilized for calculation of the Hamiltonian and decision of spin-flip events, respectively. A parallel spin-flip strategy was demonstrated to further accelerate the SA algorithm.
{"title":"Hardware Acceleration of Simulated Annealing of Spin Glass by RRAM Crossbar Array","authors":"J. Shin, Yeonjoo Jeong, Mohammed Affan Zidan, Qiwen Wang, Wei D. Lu","doi":"10.1109/IEDM.2018.8614698","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614698","url":null,"abstract":"Simulated annealing (SA) was successfully implemented and accelerated by in-memory computing hardware/software package using RRAM crossbar arrays to solve a spin glass problem. Ta2O5-based RRAM array and stochastic Cu-based CBRAM devices were utilized for calculation of the Hamiltonian and decision of spin-flip events, respectively. A parallel spin-flip strategy was demonstrated to further accelerate the SA algorithm.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614574
A. Khan
We present a simple, physical explanation of underlying microscopic mechanisms that lead to the emergence of the negative phenomena in ferroelectric materials. The material presented herein is inspired by the pedagogical treatment of ferroelectricity by Feynman and Kittel. In a toy model consisting of a linear one-dimensional chain of polarizable units (i.e., atoms or unit cells of a crystal structure), we show how simple electrostatic interactions can create a microscopic, positive feedback action that leads to negative capacitance phenomena. We point out that the unstable negative capacitance effect has its origin in the so called “polarization catastrophe” phenomenon which is essential to explain displacement type ferroelectrics. Furthermore, the fact that even in the negative capacitance state, the individual dipole always aligns along the direction of the local electrical field not opposite is made clear through the toy model. Finally, how the “$S$”-shaped polarization vs. applied electric field curve emerges out of the electrostatic interactions in an ordered set of polarizable units is shown.
{"title":"On the Microscopic Origin of Negative Capacitance in Ferroelectric Materials: A Toy Model","authors":"A. Khan","doi":"10.1109/IEDM.2018.8614574","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614574","url":null,"abstract":"We present a simple, physical explanation of underlying microscopic mechanisms that lead to the emergence of the negative phenomena in ferroelectric materials. The material presented herein is inspired by the pedagogical treatment of ferroelectricity by Feynman and Kittel. In a toy model consisting of a linear one-dimensional chain of polarizable units (i.e., atoms or unit cells of a crystal structure), we show how simple electrostatic interactions can create a microscopic, positive feedback action that leads to negative capacitance phenomena. We point out that the unstable negative capacitance effect has its origin in the so called “polarization catastrophe” phenomenon which is essential to explain displacement type ferroelectrics. Furthermore, the fact that even in the negative capacitance state, the individual dipole always aligns along the direction of the local electrical field not opposite is made clear through the toy model. Finally, how the “$S$”-shaped polarization vs. applied electric field curve emerges out of the electrostatic interactions in an ordered set of polarizable units is shown.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132927696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614656
F. Kaklin, J. Raynor, R. Henderson
We demonstrate passive high voltage generation using photodiodes biased in the photovoltaic region of operation. The photodiodes are integrated in a 90nm back side illuminated (BSI) deep trench isolation (DTI) capable imaging process technology. Four equal area, DTI separated arrays of photodiodes are implemented on a single die and connected using on-chip transmission gates (TG). The TGs control interconnects between the four arrays, connecting them in series or in parallel. A series configuration successfully generates an open-circuit voltage of 1.98V at 1klux. The full array generates 423nW/mm2 at 1klux of white LED illumination in series mode and 425nW/mm2 in parallel mode. Peak conversion efficiency is estimated at 16.1%, at 5.7klux white LED illumination.
{"title":"High Voltage Generation Using Deep Trench Isolated Photodiodes in a Back Side Illuminated Process","authors":"F. Kaklin, J. Raynor, R. Henderson","doi":"10.1109/IEDM.2018.8614656","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614656","url":null,"abstract":"We demonstrate passive high voltage generation using photodiodes biased in the photovoltaic region of operation. The photodiodes are integrated in a 90nm back side illuminated (BSI) deep trench isolation (DTI) capable imaging process technology. Four equal area, DTI separated arrays of photodiodes are implemented on a single die and connected using on-chip transmission gates (TG). The TGs control interconnects between the four arrays, connecting them in series or in parallel. A series configuration successfully generates an open-circuit voltage of 1.98V at 1klux. The full array generates 423nW/mm2 at 1klux of white LED illumination in series mode and 425nW/mm2 in parallel mode. Peak conversion efficiency is estimated at 16.1%, at 5.7klux white LED illumination.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131756410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614657
Zhenyi Ni, Yue Wang, Lixiang Liu, Shuangyi Zhao, Yang Xu, X. Pi, Deren Yang
As one of the most important technologies in the coming “More than Moore” era, neuromorphic computing critically depends on the development of synaptic devices. Here we take advantage of the synergy of the strong broadband optical absorption of boron (B)-doped silicon nanocrystals (Si NCs) and the efficient charge transport of two-dimensional (2D) WSe2 to make synaptic devices based on the hybrid structure of Si NCs and 2D WSe2. The Si-NC/WSe2 synaptic devices can be optically stimulated in a broad spectral region from the ultraviolet (UV) to near-infrared (NIR), exhibiting important synaptic functionalities. The energy consumption of the Si-NC/WSe2 synaptic devices may be as low as ∼ 75 fJ. This work has important implication for the development of synaptic devices by exploiting the abundant library of semiconductor NCs and 2D materials.
{"title":"Hybrid Structure of Silicon Nanocrystals and 2D WSe2 for Broadband Optoelectronic Synaptic Devices","authors":"Zhenyi Ni, Yue Wang, Lixiang Liu, Shuangyi Zhao, Yang Xu, X. Pi, Deren Yang","doi":"10.1109/IEDM.2018.8614657","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614657","url":null,"abstract":"As one of the most important technologies in the coming “More than Moore” era, neuromorphic computing critically depends on the development of synaptic devices. Here we take advantage of the synergy of the strong broadband optical absorption of boron (B)-doped silicon nanocrystals (Si NCs) and the efficient charge transport of two-dimensional (2D) WSe2 to make synaptic devices based on the hybrid structure of Si NCs and 2D WSe2. The Si-NC/WSe2 synaptic devices can be optically stimulated in a broad spectral region from the ultraviolet (UV) to near-infrared (NIR), exhibiting important synaptic functionalities. The energy consumption of the Si-NC/WSe2 synaptic devices may be as low as ∼ 75 fJ. This work has important implication for the development of synaptic devices by exploiting the abundant library of semiconductor NCs and 2D materials.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122562786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614527
K. Ni, B. Grisafe, W. Chakraborty, A. Saha, S. Dutta, M. Jerry, J. Smith, S. Gupta, S. Datta
In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO2-based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{max}/G_{min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm LG); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.
{"title":"In-Memory Computing Primitive for Sensor Data Fusion in 28 nm HKMG FeFET Technology","authors":"K. Ni, B. Grisafe, W. Chakraborty, A. Saha, S. Dutta, M. Jerry, J. Smith, S. Gupta, S. Datta","doi":"10.1109/IEDM.2018.8614527","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614527","url":null,"abstract":"In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO2-based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{max}/G_{min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm LG); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122681726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614654
A. Vandooren, J. Franco, Z. Wu, B. Parvais, W. Li, L. Witters, A. Walke, L. Peng, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, G. Mannaert, B. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, D. Mocuta, J. Ryckaert, N. Collaert
3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(mathrm{T}leq 525^{circ}mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.
{"title":"First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers","authors":"A. Vandooren, J. Franco, Z. Wu, B. Parvais, W. Li, L. Witters, A. Walke, L. Peng, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, G. Mannaert, B. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, D. Mocuta, J. Ryckaert, N. Collaert","doi":"10.1109/IEDM.2018.8614654","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614654","url":null,"abstract":"3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(mathrm{T}leq 525^{circ}mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122961893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614543
S. Mochizuki, B. Colombeau, L. Yu, A. Dube, S. Choi, M. Stolfi, Z. Bi, F. Chang, R. Conti, P. Liu, K. Winstel, H. Jagannathan, H. Gossmann, N. Loubet, D. Canaperi, D. Guo, S. Sharma, S. Chu, J. Boland, Q. Jin, Z. Li, S. Lin, M. Cogorno, M. Chudzik, S. Natarajan, D. Mcherron, B. Haran
In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.
{"title":"Advanced Arsenic Doped Epitaxial Growth for Source Drain Extension Formation in Scaled FinFET Devices","authors":"S. Mochizuki, B. Colombeau, L. Yu, A. Dube, S. Choi, M. Stolfi, Z. Bi, F. Chang, R. Conti, P. Liu, K. Winstel, H. Jagannathan, H. Gossmann, N. Loubet, D. Canaperi, D. Guo, S. Sharma, S. Chu, J. Boland, Q. Jin, Z. Li, S. Lin, M. Cogorno, M. Chudzik, S. Natarajan, D. Mcherron, B. Haran","doi":"10.1109/IEDM.2018.8614543","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614543","url":null,"abstract":"In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614600
Y. Yonezawa, K. Nakayama, R. Kosugi, S. Harada, K. Koseki, K. Sakamoto, T. Kimoto, H. Okumura
The current developments in silicon carbide (SiC) device technology in various voltage ranges are introduced. These developments correspond to, in particular, next-generation high to ultrahigh-voltage devices, SiC super-junction metal oxide semiconductor field effect transistors, SiC insulated gate bipolar transistors, and the fundamental bipolar degradation suppression technology. We expect that these next generation devices will trigger a paradigm shift in power electronics.
{"title":"Progress in High and Ultrahigh Voltage Silicon Carbide Device Technology","authors":"Y. Yonezawa, K. Nakayama, R. Kosugi, S. Harada, K. Koseki, K. Sakamoto, T. Kimoto, H. Okumura","doi":"10.1109/IEDM.2018.8614600","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614600","url":null,"abstract":"The current developments in silicon carbide (SiC) device technology in various voltage ranges are introduced. These developments correspond to, in particular, next-generation high to ultrahigh-voltage devices, SiC super-junction metal oxide semiconductor field effect transistors, SiC insulated gate bipolar transistors, and the fundamental bipolar degradation suppression technology. We expect that these next generation devices will trigger a paradigm shift in power electronics.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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