Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614667
A. Subirats, A. Arreghini, R. Delhougne, E. Rosseel, A. Hikavyy, L. Breuil, S. V. Palayam, G. Van den bosch, D. Linten, A. Furnémont
We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices VT unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).
我们研究了HPAP对SCC 3D NAND器件的影响。我们表明该工艺可以降低陷阱密度，但陷阱对器件VT的影响不受影响。模拟和测量结果也表明，进一步的缩放可能导致单阱影响的增加。最后，我们测量到，尽管在很大程度上改善了设备的电气参数，但HPAP对内存性能(程序/擦除)没有影响，或者可能会略微降低内存性能(保留)。
{"title":"Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices","authors":"A. Subirats, A. Arreghini, R. Delhougne, E. Rosseel, A. Hikavyy, L. Breuil, S. V. Palayam, G. Van den bosch, D. Linten, A. Furnémont","doi":"10.1109/IEDM.2018.8614667","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614667","url":null,"abstract":"We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices VT unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614582
Arvind Kumar, Leland Chang, G. E. Tellez, H. ClevengerLeighAnne, J. L. Burns
System performance has shown many decades of continuous improvement. After first reviewing historical trends and the current outlook, in this paper we discuss the challenges and opportunities in future computing systems due to the disruptive confluence of stalled scaling and emerging AI workloads. Heterogeneous integration is highlighted as a key means to future systems performance growth.
{"title":"System Performance: From Enterprise to AI","authors":"Arvind Kumar, Leland Chang, G. E. Tellez, H. ClevengerLeighAnne, J. L. Burns","doi":"10.1109/IEDM.2018.8614582","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614582","url":null,"abstract":"System performance has shown many decades of continuous improvement. After first reviewing historical trends and the current outlook, in this paper we discuss the challenges and opportunities in future computing systems due to the disruptive confluence of stalled scaling and emerging AI workloads. Heterogeneous integration is highlighted as a key means to future systems performance growth.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127108650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614695
K. Croes, C. Adelmann, C. Wilson, H. Zahedmanesh, O. Pedreira, C. Wu, A. Lesniewska, H. Oprins, S. Beyne, I. Ciofi, D. Kocaay, M. Stucchi, Z. Tokei
Reliability challenges of candidate metal systems to replace traditional Cu wiring in future interconnects are discussed. From a reliability perspective, a key opportunity is electromigration improvement: due to their high melting point and slower self-diffusion kinetics, higher current carrying capabilities are possible. Also, the higher cohesive energy and better resistance to oxidation of some metals potentially allows for barrierless integration, although adhesion properties must be carefully optimized. Besides avoiding small grain pinning and enabling high aspect ratio trench fill, the main processing challenges are identified to be a) avoiding seam voids, b) adhesion, c) CMP and d) disruptive metal etch. Main reliability challenges are related to higher mechanical stresses and higher joule heating which could lead to delamination during further processing and packaging and to enhanced electromigration in nearby metal lines.
{"title":"Interconnect metals beyond copper: reliability challenges and opportunities","authors":"K. Croes, C. Adelmann, C. Wilson, H. Zahedmanesh, O. Pedreira, C. Wu, A. Lesniewska, H. Oprins, S. Beyne, I. Ciofi, D. Kocaay, M. Stucchi, Z. Tokei","doi":"10.1109/IEDM.2018.8614695","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614695","url":null,"abstract":"Reliability challenges of candidate metal systems to replace traditional Cu wiring in future interconnects are discussed. From a reliability perspective, a key opportunity is electromigration improvement: due to their high melting point and slower self-diffusion kinetics, higher current carrying capabilities are possible. Also, the higher cohesive energy and better resistance to oxidation of some metals potentially allows for barrierless integration, although adhesion properties must be carefully optimized. Besides avoiding small grain pinning and enabling high aspect ratio trench fill, the main processing challenges are identified to be a) avoiding seam voids, b) adhesion, c) CMP and d) disruptive metal etch. Main reliability challenges are related to higher mechanical stresses and higher joule heating which could lead to delamination during further processing and packaging and to enhanced electromigration in nearby metal lines.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130040754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614602
Ruijing Ge, Xiaohan Wu, Myungsoo Kim, P. Chen, Jianping Shi, Junho Choi, Xiaoqin Li, Yanfeng Zhang, M. Chiang, Jack C. Lee, D. Akinwande
Non-volatile resistive switching (NVRS) has been recently observed with synthesized monolayer molybdenum disulfide (MoS2) as the active layer and termed atomristors [1]. In this paper, we demonstrate the fastest switching speed (<15 ns) among all crystalline two-dimensional (2D) related NVRS devices to the best of our knowledge. For the first time, ab-initio simulation results of atomristors elucidate the mechanism revealing favorable substitution of specific metal ions into sulfur vacancies during switching. This insight combined with area-scaling experimental studies indicate a local conductive-bridge-like nature. The proposed mechanism is further supported by sulfur annealing recovery phenomenon. Moreover, exfoliated MoS2 monolayer is demonstrated to have memory effect for the first time, expanding the materials beyond synthesized films. State-of-the-art non-volatile RF switches based on MoS2 atomristors were prepared, featuring 0.25 dB insertion loss, 29 dB isolation (both at 67 GHz), and 70 THz cutoff frequency, a record performance compared to emerging RF switches. Our pioneering work suggests that memory effect maybe present in dozens or 100s of 2D monolayers similar to MoS2 paving the path for new scientific studies for understanding the rich physics, and engineering research towards diverse device applications.
{"title":"Atomristors: Memory Effect in Atomically-thin Sheets and Record RF Switches","authors":"Ruijing Ge, Xiaohan Wu, Myungsoo Kim, P. Chen, Jianping Shi, Junho Choi, Xiaoqin Li, Yanfeng Zhang, M. Chiang, Jack C. Lee, D. Akinwande","doi":"10.1109/IEDM.2018.8614602","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614602","url":null,"abstract":"Non-volatile resistive switching (NVRS) has been recently observed with synthesized monolayer molybdenum disulfide (MoS2) as the active layer and termed atomristors [1]. In this paper, we demonstrate the fastest switching speed (<15 ns) among all crystalline two-dimensional (2D) related NVRS devices to the best of our knowledge. For the first time, ab-initio simulation results of atomristors elucidate the mechanism revealing favorable substitution of specific metal ions into sulfur vacancies during switching. This insight combined with area-scaling experimental studies indicate a local conductive-bridge-like nature. The proposed mechanism is further supported by sulfur annealing recovery phenomenon. Moreover, exfoliated MoS2 monolayer is demonstrated to have memory effect for the first time, expanding the materials beyond synthesized films. State-of-the-art non-volatile RF switches based on MoS2 atomristors were prepared, featuring 0.25 dB insertion loss, 29 dB isolation (both at 67 GHz), and 70 THz cutoff frequency, a record performance compared to emerging RF switches. Our pioneering work suggests that memory effect maybe present in dozens or 100s of 2D monolayers similar to MoS2 paving the path for new scientific studies for understanding the rich physics, and engineering research towards diverse device applications.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127809512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614675
M. Vinet, L. Hutin, B. Bertrand, S. Barraud, J. Hartmann, Y.-J. Kim, V. Mazzocchi, A. Amisse, H. Bohuslavskyi, L. Bourdet, A. Crippa, X. Jehl, R. Maurand, Y. Niquet, M. Sanquer, B. Venitucci, B. Jadot, E. Chanrion, P. Mortemousque, C. Spence, M. Urdampilleta, S. D. Franceschi, T. Meunier
We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.
{"title":"Towards scalable silicon quantum computing","authors":"M. Vinet, L. Hutin, B. Bertrand, S. Barraud, J. Hartmann, Y.-J. Kim, V. Mazzocchi, A. Amisse, H. Bohuslavskyi, L. Bourdet, A. Crippa, X. Jehl, R. Maurand, Y. Niquet, M. Sanquer, B. Venitucci, B. Jadot, E. Chanrion, P. Mortemousque, C. Spence, M. Urdampilleta, S. D. Franceschi, T. Meunier","doi":"10.1109/IEDM.2018.8614675","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614675","url":null,"abstract":"We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131417384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614657
Zhenyi Ni, Yue Wang, Lixiang Liu, Shuangyi Zhao, Yang Xu, X. Pi, Deren Yang
As one of the most important technologies in the coming “More than Moore” era, neuromorphic computing critically depends on the development of synaptic devices. Here we take advantage of the synergy of the strong broadband optical absorption of boron (B)-doped silicon nanocrystals (Si NCs) and the efficient charge transport of two-dimensional (2D) WSe2 to make synaptic devices based on the hybrid structure of Si NCs and 2D WSe2. The Si-NC/WSe2 synaptic devices can be optically stimulated in a broad spectral region from the ultraviolet (UV) to near-infrared (NIR), exhibiting important synaptic functionalities. The energy consumption of the Si-NC/WSe2 synaptic devices may be as low as ∼ 75 fJ. This work has important implication for the development of synaptic devices by exploiting the abundant library of semiconductor NCs and 2D materials.
{"title":"Hybrid Structure of Silicon Nanocrystals and 2D WSe2 for Broadband Optoelectronic Synaptic Devices","authors":"Zhenyi Ni, Yue Wang, Lixiang Liu, Shuangyi Zhao, Yang Xu, X. Pi, Deren Yang","doi":"10.1109/IEDM.2018.8614657","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614657","url":null,"abstract":"As one of the most important technologies in the coming “More than Moore” era, neuromorphic computing critically depends on the development of synaptic devices. Here we take advantage of the synergy of the strong broadband optical absorption of boron (B)-doped silicon nanocrystals (Si NCs) and the efficient charge transport of two-dimensional (2D) WSe2 to make synaptic devices based on the hybrid structure of Si NCs and 2D WSe2. The Si-NC/WSe2 synaptic devices can be optically stimulated in a broad spectral region from the ultraviolet (UV) to near-infrared (NIR), exhibiting important synaptic functionalities. The energy consumption of the Si-NC/WSe2 synaptic devices may be as low as ∼ 75 fJ. This work has important implication for the development of synaptic devices by exploiting the abundant library of semiconductor NCs and 2D materials.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122562786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614527
K. Ni, B. Grisafe, W. Chakraborty, A. Saha, S. Dutta, M. Jerry, J. Smith, S. Gupta, S. Datta
In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO2-based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{max}/G_{min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm LG); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.
{"title":"In-Memory Computing Primitive for Sensor Data Fusion in 28 nm HKMG FeFET Technology","authors":"K. Ni, B. Grisafe, W. Chakraborty, A. Saha, S. Dutta, M. Jerry, J. Smith, S. Gupta, S. Datta","doi":"10.1109/IEDM.2018.8614527","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614527","url":null,"abstract":"In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO2-based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{max}/G_{min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm LG); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122681726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614654
A. Vandooren, J. Franco, Z. Wu, B. Parvais, W. Li, L. Witters, A. Walke, L. Peng, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, G. Mannaert, B. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, D. Mocuta, J. Ryckaert, N. Collaert
3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(mathrm{T}leq 525^{circ}mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.
{"title":"First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers","authors":"A. Vandooren, J. Franco, Z. Wu, B. Parvais, W. Li, L. Witters, A. Walke, L. Peng, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, G. Mannaert, B. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, D. Mocuta, J. Ryckaert, N. Collaert","doi":"10.1109/IEDM.2018.8614654","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614654","url":null,"abstract":"3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(mathrm{T}leq 525^{circ}mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiOx dipole improves device performance and brings the BTI reliability within specification at low temperature.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122961893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614543
S. Mochizuki, B. Colombeau, L. Yu, A. Dube, S. Choi, M. Stolfi, Z. Bi, F. Chang, R. Conti, P. Liu, K. Winstel, H. Jagannathan, H. Gossmann, N. Loubet, D. Canaperi, D. Guo, S. Sharma, S. Chu, J. Boland, Q. Jin, Z. Li, S. Lin, M. Cogorno, M. Chudzik, S. Natarajan, D. Mcherron, B. Haran
In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.
{"title":"Advanced Arsenic Doped Epitaxial Growth for Source Drain Extension Formation in Scaled FinFET Devices","authors":"S. Mochizuki, B. Colombeau, L. Yu, A. Dube, S. Choi, M. Stolfi, Z. Bi, F. Chang, R. Conti, P. Liu, K. Winstel, H. Jagannathan, H. Gossmann, N. Loubet, D. Canaperi, D. Guo, S. Sharma, S. Chu, J. Boland, Q. Jin, Z. Li, S. Lin, M. Cogorno, M. Chudzik, S. Natarajan, D. Mcherron, B. Haran","doi":"10.1109/IEDM.2018.8614543","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614543","url":null,"abstract":"In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614600
Y. Yonezawa, K. Nakayama, R. Kosugi, S. Harada, K. Koseki, K. Sakamoto, T. Kimoto, H. Okumura
The current developments in silicon carbide (SiC) device technology in various voltage ranges are introduced. These developments correspond to, in particular, next-generation high to ultrahigh-voltage devices, SiC super-junction metal oxide semiconductor field effect transistors, SiC insulated gate bipolar transistors, and the fundamental bipolar degradation suppression technology. We expect that these next generation devices will trigger a paradigm shift in power electronics.
{"title":"Progress in High and Ultrahigh Voltage Silicon Carbide Device Technology","authors":"Y. Yonezawa, K. Nakayama, R. Kosugi, S. Harada, K. Koseki, K. Sakamoto, T. Kimoto, H. Okumura","doi":"10.1109/IEDM.2018.8614600","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614600","url":null,"abstract":"The current developments in silicon carbide (SiC) device technology in various voltage ranges are introduced. These developments correspond to, in particular, next-generation high to ultrahigh-voltage devices, SiC super-junction metal oxide semiconductor field effect transistors, SiC insulated gate bipolar transistors, and the fundamental bipolar degradation suppression technology. We expect that these next generation devices will trigger a paradigm shift in power electronics.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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