For the first time, Generative Adversarial Network (GAN) is experimentally demonstrated on 1kb analog RRAM array. After online training, the network can generate different patterns of digital numbers. The intrinsic random noises of analog RRAM device are utilized as the input of the neural network to improve the diversity of the generated numbers. The impacts of read and write noises on the performance of GAN are analyzed. Optimized methodology is developed to mitigate the excessive noise effect on RRAM based GAN. This work proves that RRAM is suitable for the application of GAN. It also paves a new way to take advantage of the non-ideal effects of RRAM devices.
{"title":"Demonstration of Generative Adversarial Network by Intrinsic Random Noises of Analog RRAM Devices","authors":"Yudeng Lin, Huaqiang Wu, B. Gao, Peng Yao, Wei Wu, Qingtian Zhang, Xiaodong Zhang, Xinyi Li, Fuhai Li, Jiwu Lu, Gezi Li, Shimeng Yu, H. Qian","doi":"10.1109/IEDM.2018.8614483","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614483","url":null,"abstract":"For the first time, Generative Adversarial Network (GAN) is experimentally demonstrated on 1kb analog RRAM array. After online training, the network can generate different patterns of digital numbers. The intrinsic random noises of analog RRAM device are utilized as the input of the neural network to improve the diversity of the generated numbers. The impacts of read and write noises on the performance of GAN are analyzed. Optimized methodology is developed to mitigate the excessive noise effect on RRAM based GAN. This work proves that RRAM is suitable for the application of GAN. It also paves a new way to take advantage of the non-ideal effects of RRAM devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"11 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614578
T. Nakasugi, T. Kono, K. Fukuhara, M. Hatano, H. Tokue, M. Komori, H. Tsuda, T. Komukai, K. Takahata, H. Kato, K. Kobayashi, A. Mitra, S. Kobayashi, S. Inoue, T. Higashiki, T. Motokawa, M. Saito, S. Kanamitsu, M. Itoh, T. Imamura, K. Matasunaga, K. Hashimoto, Y. Kim, J. Cho, W. Jung
We developed a nanoimprint lithography (NIL) technology including NIL system, template and resist process for half pitch (hp) 14 nm direct pattering. The latest NIL system NZ2C shows the mix and match overlay (MMO) of 3.4 nm ($3sigma$) and the template life around 125 lots. Throughput of 80 wafers per hour (wph) was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon (GP-SOC) and multi field dispense (MFD). The hp 14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer.
{"title":"Half pitch 14 nm direct pattering with Nanoimprint lithography","authors":"T. Nakasugi, T. Kono, K. Fukuhara, M. Hatano, H. Tokue, M. Komori, H. Tsuda, T. Komukai, K. Takahata, H. Kato, K. Kobayashi, A. Mitra, S. Kobayashi, S. Inoue, T. Higashiki, T. Motokawa, M. Saito, S. Kanamitsu, M. Itoh, T. Imamura, K. Matasunaga, K. Hashimoto, Y. Kim, J. Cho, W. Jung","doi":"10.1109/IEDM.2018.8614578","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614578","url":null,"abstract":"We developed a nanoimprint lithography (NIL) technology including NIL system, template and resist process for half pitch (hp) 14 nm direct pattering. The latest NIL system NZ2C shows the mix and match overlay (MMO) of 3.4 nm ($3sigma$) and the template life around 125 lots. Throughput of 80 wafers per hour (wph) was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon (GP-SOC) and multi field dispense (MFD). The hp 14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129450793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614514
T. Rollo, H. Wang, G. Han, D. Esseni
This paper presents new analytical and numerical models aiming at a better insight about the physics and design of ferroelectric NC-FETs. We argue that a design focused on the off-state and targeting steep slope with negligible hysteresis is unlikely to be successful. A design targeting an enhanced on-state capacitance is instead more feasible, and can improve both sub-threshold swing and on-current. Also, NC-FETs can reduce the temperature sensitivity compared to baseline FETs, but the sensitivity to dielectrics thickness is critical.
{"title":"A simulation based study of NC-FETs design: off-state versus on-state perspective","authors":"T. Rollo, H. Wang, G. Han, D. Esseni","doi":"10.1109/IEDM.2018.8614514","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614514","url":null,"abstract":"This paper presents new analytical and numerical models aiming at a better insight about the physics and design of ferroelectric NC-FETs. We argue that a design focused on the off-state and targeting steep slope with negligible hysteresis is unlikely to be successful. A design targeting an enhanced on-state capacitance is instead more feasible, and can improve both sub-threshold swing and on-current. Also, NC-FETs can reduce the temperature sensitivity compared to baseline FETs, but the sensitivity to dielectrics thickness is critical.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"49 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114012501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614563
T. Kachi
Currently, electrification of automobiles is an urgent task, and high-performance power devices are indispensable items for their electrification. Wide bandgap semiconductors are powerful candidates for power devices used in electric vehicles (EV) and fuel cell vehicles (FCV) in the near future, and recent advances in GaN power devices are prominent in particular. Lateral GaN power devices on Si substrates beGaN to be commercialized, and they are moving to system development. Research and development of vertical GaN power devices are also accelerating. Such high-performance devices are expected to greatly contribute to the electrification of automobiles, and interest in GaN power devices is increasing.
{"title":"GaN devices for automotive application and their challenges in adoption","authors":"T. Kachi","doi":"10.1109/IEDM.2018.8614563","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614563","url":null,"abstract":"Currently, electrification of automobiles is an urgent task, and high-performance power devices are indispensable items for their electrification. Wide bandgap semiconductors are powerful candidates for power devices used in electric vehicles (EV) and fuel cell vehicles (FCV) in the near future, and recent advances in GaN power devices are prominent in particular. Lateral GaN power devices on Si substrates beGaN to be commercialized, and they are moving to system development. Research and development of vertical GaN power devices are also accelerating. Such high-performance devices are expected to greatly contribute to the electrification of automobiles, and interest in GaN power devices is increasing.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130151930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614584
T. Muneshwar, G. Shoute, D. Barlage, K. Cadien
A scalable kinetic Monte-Carlo model (sKMC) of molecular transport for atomic layer deposition (ALD) for high aspect-ratio (AR) features is developed. Surface coverage is a critical parameter studied here in detail. The capabilities of the stochastic model provide insight into challenges in growing ALD films in high-AR via structures faced by the industry, including the effects of parasitic surface reactions resulting in poor coverage. Furthermore, we provide experimental results verifying the model's prediction by growing ALD SiNx, on high-AR via structures. By compensating for the processing errors corroborated by the model, we experimentally improved sidewall coverage from 70% to 92%.
{"title":"Parasitic Surface Reactions in High-Aspect Ratio Via Filling using ALD: A Stochastic Kinetic Model","authors":"T. Muneshwar, G. Shoute, D. Barlage, K. Cadien","doi":"10.1109/IEDM.2018.8614584","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614584","url":null,"abstract":"A scalable kinetic Monte-Carlo model (sKMC) of molecular transport for atomic layer deposition (ALD) for high aspect-ratio (AR) features is developed. Surface coverage is a critical parameter studied here in detail. The capabilities of the stochastic model provide insight into challenges in growing ALD films in high-AR via structures faced by the industry, including the effects of parasitic surface reactions resulting in poor coverage. Furthermore, we provide experimental results verifying the model's prediction by growing ALD SiNx, on high-AR via structures. By compensating for the processing errors corroborated by the model, we experimentally improved sidewall coverage from 70% to 92%.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124277734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614630
I. Jang, Hyoungsoo Ko, Alexander Schmidt, Sae-jin Kim, Moonhyun Cha, H. Ahn, Honglae Park, Dae Sin Kim, Hokyu Kang
For modern semiconductor devices, the level of details which we should investigate for predictive simulation is going extreme. Not only the atomistic simulation is required but equipment and transistor scale simulation is also needed to understand the formation of atomic scale feature. In this paper, practical applications of multi-domain simulations are introduced for advanced S/D process in logic, interface engineering in DRAM cell and cell stack ALD process of flash memory devices.
{"title":"Multi-domain process modeling for advanced logic and memory devices: from equimpments to materials","authors":"I. Jang, Hyoungsoo Ko, Alexander Schmidt, Sae-jin Kim, Moonhyun Cha, H. Ahn, Honglae Park, Dae Sin Kim, Hokyu Kang","doi":"10.1109/IEDM.2018.8614630","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614630","url":null,"abstract":"For modern semiconductor devices, the level of details which we should investigate for predictive simulation is going extreme. Not only the atomistic simulation is required but equipment and transistor scale simulation is also needed to understand the formation of atomic scale feature. In this paper, practical applications of multi-domain simulations are introduced for advanced S/D process in logic, interface engineering in DRAM cell and cell stack ALD process of flash memory devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614647
E. Jang
Ever since the physics of quantum dot (QD) was discovered, much research effort has been carried out for more than 30 years, and lots of applications adopting QDs have been proposed. Especially, wide color gamut displays using QDs as active light emitting materials have drawn much attention. And, the QD-based consumer displays such as LED TVs, tablets, and special monitors are now on the market. They provide best color gamut, reasonable power efficiency, and affordable price showing superior competitive edge to OLED technology. However, still there are issues and argues using Cadmium containing materials in practical consumer devices. In spite of the European RoHS Exemptions, we need to be aware the environmental risk of producing large quantity of Cd-containing materials and using them in the consumer electronics. And, this growing apprehension for environmental issues formed great limitation for QD's applications. Therefore, we have dedicated to develop more environmentally friendly InP based QDs that showed considerably high efficiency and saturated color spectrum compared to the Cd-containing materials. The structure of Cd-free QD was specially tailored for display applications and the synthetic process was optimized to produce reliable materials in commercial scales. In order to improve the efficiency and stability of the QDs in the devices operating under severe atmosphere, specific composite materials were designed and the fabrication process was optimized. From 2015, Samsung has released Cd-free QD adopted UHD TV for major product line-up which show the best color gamut among the current displays. Now we are trying to make additional breakthroughs in displays by using established QD material platform and broaden the technology to wider optoelectronic applications.
{"title":"Environmentally Friendly Quantum Dots for Display Applications","authors":"E. Jang","doi":"10.1109/IEDM.2018.8614647","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614647","url":null,"abstract":"Ever since the physics of quantum dot (QD) was discovered, much research effort has been carried out for more than 30 years, and lots of applications adopting QDs have been proposed. Especially, wide color gamut displays using QDs as active light emitting materials have drawn much attention. And, the QD-based consumer displays such as LED TVs, tablets, and special monitors are now on the market. They provide best color gamut, reasonable power efficiency, and affordable price showing superior competitive edge to OLED technology. However, still there are issues and argues using Cadmium containing materials in practical consumer devices. In spite of the European RoHS Exemptions, we need to be aware the environmental risk of producing large quantity of Cd-containing materials and using them in the consumer electronics. And, this growing apprehension for environmental issues formed great limitation for QD's applications. Therefore, we have dedicated to develop more environmentally friendly InP based QDs that showed considerably high efficiency and saturated color spectrum compared to the Cd-containing materials. The structure of Cd-free QD was specially tailored for display applications and the synthetic process was optimized to produce reliable materials in commercial scales. In order to improve the efficiency and stability of the QDs in the devices operating under severe atmosphere, specific composite materials were designed and the fabrication process was optimized. From 2015, Samsung has released Cd-free QD adopted UHD TV for major product line-up which show the best color gamut among the current displays. Now we are trying to make additional breakthroughs in displays by using established QD material platform and broaden the technology to wider optoelectronic applications.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124020094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614687
M. Hua, Xiangbin Cai, Song Yang, Zhaofu Zhang, Zheyang Zheng, Jin Wei, Ning Wang, K. J. Chen
Under reverse-bias stress with a high drain voltage, hole-induced gate dielectric degradation in the E-mode GaN MIS-FETs could lead to non-recoverable $V_{text{TH}}$ shifts and devastating time-dependent breakdown. Such a degradation can be effectively suppressed by converting the GaN channel into a crystalline $text{GaO}_{mathrm{x}}mathrm{N}_{1-mathrm{x}}$ channel in the gated region. The valence band offset between $text{GaO}_{mathrm{x}}mathrm{N}_{1-mathrm{x}}$ and the surrounding GaN creates a hole-blocking ring around the gate dielectric, preventing holes from flowing to the gate dielectric and therefore mitigating the hole-induced degradation.
{"title":"Suppressed Hole-Induced Degradation in E-mode GaN MIS-FETs with Crystalline $text{GaO}_{mathrm{x}}mathrm{N}_{1-mathrm{x}}$ Channel","authors":"M. Hua, Xiangbin Cai, Song Yang, Zhaofu Zhang, Zheyang Zheng, Jin Wei, Ning Wang, K. J. Chen","doi":"10.1109/IEDM.2018.8614687","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614687","url":null,"abstract":"Under reverse-bias stress with a high drain voltage, hole-induced gate dielectric degradation in the E-mode GaN MIS-FETs could lead to non-recoverable $V_{text{TH}}$ shifts and devastating time-dependent breakdown. Such a degradation can be effectively suppressed by converting the GaN channel into a crystalline $text{GaO}_{mathrm{x}}mathrm{N}_{1-mathrm{x}}$ channel in the gated region. The valence band offset between $text{GaO}_{mathrm{x}}mathrm{N}_{1-mathrm{x}}$ and the surrounding GaN creates a hole-blocking ring around the gate dielectric, preventing holes from flowing to the gate dielectric and therefore mitigating the hole-induced degradation.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"137 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125820542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614607
C. Alessandri, P. Pandey, A. Seabaugh
A physics-based, circuit-compatible Monte Carlo simulation framework, capable of predicting the dynamic response of a ferroelectric (FE) under any arbitrary input waveform, is developed by extending the nucleation-limited switching model. Measured polarization reversal data from fabricated FE W/Hf0.5Zr0.5O2 (HZO)/W capacitors is used to extract the statistical distribution of FE grains, which show negligible variation with film thickness. After parameter extraction, the model is able to predict the dynamics of HZO and bilayer HZO/HfO2 (FE-DE) thin films without further calibration. Unlike prior models, the proposed model is able to predict device-to-device variability, and quantify the resultant reduction in the memory window for highly scaled devices, revealing a significant reduction for FE capacitors having < 20 grains ($sim 40times 40 text{nm}^{2}$). The memory window is further reduced in FE-DE stacks for the same programming voltage and pulse duration due to the dielectric depolarizing field.
{"title":"Experimentally Validated, Predictive Monte Carlo Modeling of Ferroelectric Dynamics and Variability","authors":"C. Alessandri, P. Pandey, A. Seabaugh","doi":"10.1109/IEDM.2018.8614607","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614607","url":null,"abstract":"A physics-based, circuit-compatible Monte Carlo simulation framework, capable of predicting the dynamic response of a ferroelectric (FE) under any arbitrary input waveform, is developed by extending the nucleation-limited switching model. Measured polarization reversal data from fabricated FE W/Hf0.5Zr0.5O2 (HZO)/W capacitors is used to extract the statistical distribution of FE grains, which show negligible variation with film thickness. After parameter extraction, the model is able to predict the dynamics of HZO and bilayer HZO/HfO2 (FE-DE) thin films without further calibration. Unlike prior models, the proposed model is able to predict device-to-device variability, and quantify the resultant reduction in the memory window for highly scaled devices, revealing a significant reduction for FE capacitors having < 20 grains ($sim 40times 40 text{nm}^{2}$). The memory window is further reduced in FE-DE stacks for the same programming voltage and pulse duration due to the dielectric depolarizing field.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614612
Xin Zheng, Ryan Zarcone, Dylan M. Paiton, Joon Sohn, W. Wan, B. Olshausen, H. P. Wong
We demonstrate by experiment an image storage and compression task by directly storing analog image data onto an analog-valued RRAM array. A joint source-channel coding algorithm is developed with a neural network to encode and retrieve natural images. The encoder and decoder adapt jointly to the statistics of the images and the statistics of the RRAM array in order to minimize distortion. This adaptive joint source-channel coding method is resilient to RRAM array non-idealities such as cycle-to-cycle and device-to-device variations, time-dependent variability, and non-functional storage cells, while achieving a reasonable reconstruction performance of ∼ 20 dB using only 0.1 devices/pixel for the analog image.
{"title":"Error-Resilient Analog Image Storage and Compression with Analog-Valued RRAM Arrays: An Adaptive Joint Source-Channel Coding Approach","authors":"Xin Zheng, Ryan Zarcone, Dylan M. Paiton, Joon Sohn, W. Wan, B. Olshausen, H. P. Wong","doi":"10.1109/IEDM.2018.8614612","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614612","url":null,"abstract":"We demonstrate by experiment an image storage and compression task by directly storing analog image data onto an analog-valued RRAM array. A joint source-channel coding algorithm is developed with a neural network to encode and retrieve natural images. The encoder and decoder adapt jointly to the statistics of the images and the statistics of the RRAM array in order to minimize distortion. This adaptive joint source-channel coding method is resilient to RRAM array non-idealities such as cycle-to-cycle and device-to-device variations, time-dependent variability, and non-functional storage cells, while achieving a reasonable reconstruction performance of ∼ 20 dB using only 0.1 devices/pixel for the analog image.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124721852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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