Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614500
M. Brink, J. Chow, J. Hertzberg, E. Magesan, S. Rosenblatt
The outstanding progress in experimental quantum computing with superconducting Josephson-junction based qubits over the past few decades has pushed coherence times many orders of magnitude above that of the first measured. We are also in the midst of scaling towards complex architectures of multi-qubit processors where maintaining very low gate error rates at the limits supported by coherence times is extremely important. Here we will review some of the critical materials and device challenges for superconducting qubits from the perspective of improved coherence and improved error rates. In particular we will focus on the problem of frequency allocations in order to target multi-qubit lattices for fixed-frequency microwave-based gates.
{"title":"Device challenges for near term superconducting quantum processors: frequency collisions","authors":"M. Brink, J. Chow, J. Hertzberg, E. Magesan, S. Rosenblatt","doi":"10.1109/IEDM.2018.8614500","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614500","url":null,"abstract":"The outstanding progress in experimental quantum computing with superconducting Josephson-junction based qubits over the past few decades has pushed coherence times many orders of magnitude above that of the first measured. We are also in the midst of scaling towards complex architectures of multi-qubit processors where maintaining very low gate error rates at the limits supported by coherence times is extremely important. Here we will review some of the critical materials and device challenges for superconducting qubits from the perspective of improved coherence and improved error rates. In particular we will focus on the problem of frequency allocations in order to target multi-qubit lattices for fixed-frequency microwave-based gates.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"48 40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132367122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614546
D. Prasad, A. Naeemi
Interconnect parasitics severely limit the performance and power dissipation in modern circuits at the advanced process technology nodes. Hence, device-level advances must be complemented with appropriate interconnect technology and design innovations for effective enablement at the circuit and system levels. This paper highlights the impact of device technologies on the optimal interconnect design and circuit-level metrics. The FinFET and Tunnel-FETs are studied by building fully placed-and-routed physical designs. The impact of device and interconnect technology co-optimization on circuit performance, power, and variability is shown for a range of emerging devices.
{"title":"Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices: A Physical Design Perspective","authors":"D. Prasad, A. Naeemi","doi":"10.1109/IEDM.2018.8614546","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614546","url":null,"abstract":"Interconnect parasitics severely limit the performance and power dissipation in modern circuits at the advanced process technology nodes. Hence, device-level advances must be complemented with appropriate interconnect technology and design innovations for effective enablement at the circuit and system levels. This paper highlights the impact of device technologies on the optimal interconnect design and circuit-level metrics. The FinFET and Tunnel-FETs are studied by building fully placed-and-routed physical designs. The impact of device and interconnect technology co-optimization on circuit performance, power, and variability is shown for a range of emerging devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134468007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614496
Kai Ni, Jeffrey A. Smith, B. Grisafe, Titash Rakshit, Borna Obradovic, Jorge A. Kittl, Mark S. Rodder, S. Datta
We demonstrate an SoC logic compatible ferroelectric-metal field effect transistor (FeMFET) digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with the gate of a conventional Si HK/MG MOSFET. Through optimization of the area ratio between the FE capacitor and the MOSFET, we show: 1) program/erase write voltages can be scaled down to logic compatible level, ±1.8 V, simplifying write circuitry; 2) write speed of 100ns; 3) write endurance $> 10^{10}$ cycles without degradation due to elimination of charge trapping in FE; 4) 2 bits/cell achieving software levels of accuracy for inference on MNIST training database; 5) state retention approaching 104 s for a depolarization field of 0.3 MV/cm; 6) Multi-port (independent read and write) operations.
{"title":"SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications","authors":"Kai Ni, Jeffrey A. Smith, B. Grisafe, Titash Rakshit, Borna Obradovic, Jorge A. Kittl, Mark S. Rodder, S. Datta","doi":"10.1109/IEDM.2018.8614496","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614496","url":null,"abstract":"We demonstrate an SoC logic compatible ferroelectric-metal field effect transistor (FeMFET) digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with the gate of a conventional Si HK/MG MOSFET. Through optimization of the area ratio between the FE capacitor and the MOSFET, we show: 1) program/erase write voltages can be scaled down to logic compatible level, ±1.8 V, simplifying write circuitry; 2) write speed of 100ns; 3) write endurance $> 10^{10}$ cycles without degradation due to elimination of charge trapping in FE; 4) 2 bits/cell achieving software levels of accuracy for inference on MNIST training database; 5) state retention approaching 104 s for a depolarization field of 0.3 MV/cm; 6) Multi-port (independent read and write) operations.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116152606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614482
J. Welser, J. Pitera, C. Goldberg
Hardware has taken on a supporting role in the maturation and proliferation of narrow AI, but will take a leading role to enable the innovation and adoption of broad AI. The concurrent evolution of broad AI with purpose-built hardware will shift traditional balances between cloud and edge, structured and unstructured data, and training and inference. Heterogeneous system architectures are already being delivered where varied compute resources, including high-bandwidth CPUs, specialized AI accelerators, and high-performance networking are infused in each node to yield significant performance improvements. Looking to the future, we envision a roadmap of specialized technologies to accelerate AI, starting with heterogeneous digital von Neumann machines, exploring reduced-precision accelerator approaches, finding the limits of conventional device power-performance with analog AI devices, and finishing with quantum computing for AI.
{"title":"Future Computing Hardware for AI","authors":"J. Welser, J. Pitera, C. Goldberg","doi":"10.1109/IEDM.2018.8614482","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614482","url":null,"abstract":"Hardware has taken on a supporting role in the maturation and proliferation of narrow AI, but will take a leading role to enable the innovation and adoption of broad AI. The concurrent evolution of broad AI with purpose-built hardware will shift traditional balances between cloud and edge, structured and unstructured data, and training and inference. Heterogeneous system architectures are already being delivered where varied compute resources, including high-bandwidth CPUs, specialized AI accelerators, and high-performance networking are infused in each node to yield significant performance improvements. Looking to the future, we envision a roadmap of specialized technologies to accelerate AI, starting with heterogeneous digital von Neumann machines, exploring reduced-precision accelerator approaches, finding the limits of conventional device power-performance with analog AI devices, and finishing with quantum computing for AI.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116777184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614534
V. Issakov, S. Trotta
This paper addresses considerations on design of highly-integrated transceivers at mm-wave frequencies. Several aspects are discussed such as SiGe HBT scaling and co-design optimization. A highly-integrated chip operating at V-band for backhaul communication is shown as an example.
{"title":"Considerations on Design of Highly-Integrated Millimeter-Wave Transceivers in SiGe HBT","authors":"V. Issakov, S. Trotta","doi":"10.1109/IEDM.2018.8614534","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614534","url":null,"abstract":"This paper addresses considerations on design of highly-integrated transceivers at mm-wave frequencies. Several aspects are discussed such as SiGe HBT scaling and co-design optimization. A highly-integrated chip operating at V-band for backhaul communication is shown as an example.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121978310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614537
M. Rodwell, Y. Fang, J. Rode, J. Wu, B. Markman, S. S. Šuran Brunelli, J. Klamkin, M. Urteaga
We examine potential 100–340 GHz wireless applications in communications and imaging, and examine the prospects of developing the mm-wave transistors needed to support these applications.
{"title":"100-340GHz Systems: Transistors and Applications","authors":"M. Rodwell, Y. Fang, J. Rode, J. Wu, B. Markman, S. S. Šuran Brunelli, J. Klamkin, M. Urteaga","doi":"10.1109/IEDM.2018.8614537","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614537","url":null,"abstract":"We examine potential 100–340 GHz wireless applications in communications and imaging, and examine the prospects of developing the mm-wave transistors needed to support these applications.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121984789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614679
C. Huyghebaert, Tom Schram, Q. Smets, T. K. Agarwal, D. Verreck, S. Brems, Alain Phommahaxay, D. Chiappe, S. E. Kazzi, C. L. D. L. Rosa, G. Arutchelvan, D. Cott, Jonathan Ludwig, A. Gaur, S. Sutar, A. Leonhardt, D. Marinov, D. Lin, M. Caymax, I. Asselberghs, G. Pourtois, I. Radu
To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3rd dimension at reasonable cost. This paper highlights the obstacles and paths to a scaled 2D CMOS solution. The baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows us to identify the most promising 2D material and device design. For different key challenges, possible integrated solutions are benchmarked and discussed. Finally we report on the learning from our first lab to fab vehicle designed to bridge the lab and IMEC's 300mm pilot line.
{"title":"2D materials: roadmap to CMOS integration","authors":"C. Huyghebaert, Tom Schram, Q. Smets, T. K. Agarwal, D. Verreck, S. Brems, Alain Phommahaxay, D. Chiappe, S. E. Kazzi, C. L. D. L. Rosa, G. Arutchelvan, D. Cott, Jonathan Ludwig, A. Gaur, S. Sutar, A. Leonhardt, D. Marinov, D. Lin, M. Caymax, I. Asselberghs, G. Pourtois, I. Radu","doi":"10.1109/IEDM.2018.8614679","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614679","url":null,"abstract":"To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3rd dimension at reasonable cost. This paper highlights the obstacles and paths to a scaled 2D CMOS solution. The baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows us to identify the most promising 2D material and device design. For different key challenges, possible integrated solutions are benchmarked and discussed. Finally we report on the learning from our first lab to fab vehicle designed to bridge the lab and IMEC's 300mm pilot line.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127080732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614668
J.-R. Zhang, M. Rupakula, F. Bellando, E. G. Cordero, J. Longo, F. Wildhaber, G. Herment, H. Guérin, A. Ionescu
This paper reports for the first time, smart 3D-Extended-Metal-Gate Ion-Sensitive-Field-Effect-Transistors (3D-EMG-ISFETs), with unique figures of merit: (i) extremely-low-power (down to a record value of 2 pW per sensor under excellent linearity), (ii) all CMOS integrated, (iii) high performance pH and multi-ion (Na+, K+, Ca2+) sensing, and, (iv) uniquely low cross sensitivity experimentally proven. Detailed electrical DC and dynamic characterizations show excellent sensitivities (56.8 mV/pH, −58mV/dec for Na+, −49.5 mV/dec for K+, and −21.9 mV/dec for Ca2+) and high selectivity of each ion sensor against 4 different ions that usually coexist in biofluids, all achieved on same CMOS die. Furthermore, unprecedented results show that the threshold voltage (Vth) variability of such CMOS ISFET is reduced by 78 times. We report a Vth drift rate in liquid conditions of 0.67 mV/h, decreased by one order of magnitude compared to other state of the art CMOS ISFETs. Overall, the reported experimental achievements, supported by SPICE calibrated behavioral model simulations results shown in this paper, are expected to greatly enhance the predictability of high performance multi-analyte ISFETs, which is a big step towards ISFET sensor system mass production.
{"title":"All CMOS Integrated 3D-Extended Metal Gate ISFETs for pH and Multi-Ion (Na+, K+, Ca2+) sensing","authors":"J.-R. Zhang, M. Rupakula, F. Bellando, E. G. Cordero, J. Longo, F. Wildhaber, G. Herment, H. Guérin, A. Ionescu","doi":"10.1109/IEDM.2018.8614668","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614668","url":null,"abstract":"This paper reports for the first time, smart 3D-Extended-Metal-Gate Ion-Sensitive-Field-Effect-Transistors (3D-EMG-ISFETs), with unique figures of merit: (i) extremely-low-power (down to a record value of 2 pW per sensor under excellent linearity), (ii) all CMOS integrated, (iii) high performance pH and multi-ion (Na+, K+, Ca2+) sensing, and, (iv) uniquely low cross sensitivity experimentally proven. Detailed electrical DC and dynamic characterizations show excellent sensitivities (56.8 mV/pH, −58mV/dec for Na+, −49.5 mV/dec for K+, and −21.9 mV/dec for Ca2+) and high selectivity of each ion sensor against 4 different ions that usually coexist in biofluids, all achieved on same CMOS die. Furthermore, unprecedented results show that the threshold voltage (Vth) variability of such CMOS ISFET is reduced by 78 times. We report a Vth drift rate in liquid conditions of 0.67 mV/h, decreased by one order of magnitude compared to other state of the art CMOS ISFETs. Overall, the reported experimental achievements, supported by SPICE calibrated behavioral model simulations results shown in this paper, are expected to greatly enhance the predictability of high performance multi-analyte ISFETs, which is a big step towards ISFET sensor system mass production.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614665
T. Rosca, A. Saeidi, E. Memišević, L. Wernersson, A. Ionescu
In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus ∼36/45mV/dec in smaller arrays, once the trap-assisted tunneling is removed (from 150K down to 10K). In all NW arrays we observe improvement of the on-current and of maximum transconductance, gmax, at cryogenic temperatures, with very little dependence of temperature, from 150K to 10K. The paper reports that in the range 150K to 10K only band-to-band-tunneling dominates the analog figures of merit of Tunnel FETs; we measured transconductance efficiencincies higher than 60V−1 for small arrays (breaking the limit of CMOS at RT) and close to 42V−1 for large arrays, for supply volrages smaller than 100mV, offering the possibility to design future energy efficient readouts and analog-to-digital converters. In contrast with cryogenic MOSFETs, Tunnel FETs show almost no hysteresis (<24mV), steep transfer characteristics, are free of kinks in output characteristics, with a unique stability of the swing drift with T, and negligible threshold voltage drift in all arrays configurations.
{"title":"An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays: Digital and Analog Figures of Merit from 300K to 10K","authors":"T. Rosca, A. Saeidi, E. Memišević, L. Wernersson, A. Ionescu","doi":"10.1109/IEDM.2018.8614665","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614665","url":null,"abstract":"In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus ∼36/45mV/dec in smaller arrays, once the trap-assisted tunneling is removed (from 150K down to 10K). In all NW arrays we observe improvement of the on-current and of maximum transconductance, gmax, at cryogenic temperatures, with very little dependence of temperature, from 150K to 10K. The paper reports that in the range 150K to 10K only band-to-band-tunneling dominates the analog figures of merit of Tunnel FETs; we measured transconductance efficiencincies higher than 60V−1 for small arrays (breaking the limit of CMOS at RT) and close to 42V−1 for large arrays, for supply volrages smaller than 100mV, offering the possibility to design future energy efficient readouts and analog-to-digital converters. In contrast with cryogenic MOSFETs, Tunnel FETs show almost no hysteresis (<24mV), steep transfer characteristics, are free of kinks in output characteristics, with a unique stability of the swing drift with T, and negligible threshold voltage drift in all arrays configurations.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128785061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614649
Qingzhu Zhang, H. Tu, H. Yin, F. Wei, Hongbin Zhao, Chunling Xue, Qianhui Wei, Zhaohao Zhang, Xiao Zhang, Shaoming Zhang, Q. Han, Yudong Li, R. Zhao, Jiang Yan, Junfeng Li, Wenwu Wang
In this paper, a biocompatible biosensor based on horizontal Si nanowire (NW) array field-effect transistor (FET) has been fabricated by the feasible spacer image transfer (SIT) process. The Si NW FET as biosensor is proposed for the realtime cellular Ca2+ monitoring for mesenchymal stem cells (MSCs), which presents fast-responded and high-sensitive characteristics. Compared with the conventional sensing techniques, the Si NW biosensor exhibits non-invasive, biocompatible and reliable advantages. This will help us to further understand the mechanism of cellular ion activities and provides a promising method for the cell-level diagnose and therapy.
{"title":"Si Nanowire Biosensors Using a FinFET Fabrication Process for Real Time Monitoring Cellular Ion Actitivies","authors":"Qingzhu Zhang, H. Tu, H. Yin, F. Wei, Hongbin Zhao, Chunling Xue, Qianhui Wei, Zhaohao Zhang, Xiao Zhang, Shaoming Zhang, Q. Han, Yudong Li, R. Zhao, Jiang Yan, Junfeng Li, Wenwu Wang","doi":"10.1109/IEDM.2018.8614649","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614649","url":null,"abstract":"In this paper, a biocompatible biosensor based on horizontal Si nanowire (NW) array field-effect transistor (FET) has been fabricated by the feasible spacer image transfer (SIT) process. The Si NW FET as biosensor is proposed for the realtime cellular Ca2+ monitoring for mesenchymal stem cells (MSCs), which presents fast-responded and high-sensitive characteristics. Compared with the conventional sensing techniques, the Si NW biosensor exhibits non-invasive, biocompatible and reliable advantages. This will help us to further understand the mechanism of cellular ion activities and provides a promising method for the cell-level diagnose and therapy.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127764492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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