Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614518
R. Bao, Huimei Zhou, Miaomiao Wang, D. Guo, B. Haran, V. Narayanan, R. Divakaruni
We demonstrated more than 3 pairs of threshold voltage (Vt) devices by volume-less multiple Vt (multi-Vt) scheme plus dual work function metals (WFM) without performance and reliability degradation on 20nm gate length FinFET CMOS devices. Vt shifts over 200 mV were achieved for both nFET and pFET. The volume-less nature of this multi-Vt scheme relieves replacement metal gate (RMG) challenges and opens the path to offer multi-Vt solution for future highly scaled technologies.
我们在20nm栅极长度FinFET CMOS器件上，通过无体积多重Vt (multiple Vt)方案和双功功能金属(dual work function metals, WFM)，展示了超过3对阈值电压(Vt)器件的性能和可靠性没有下降。fet和fet均实现了200 mV以上的Vt位移。这种多电压门方案的无体积特性减轻了更换金属门(RMG)的挑战，并为未来高度规模化的技术提供多电压门解决方案开辟了道路。
{"title":"Extendable and Manufacturable Volume-less Multi-Vt Solution for 7nm Technology Node and Beyond","authors":"R. Bao, Huimei Zhou, Miaomiao Wang, D. Guo, B. Haran, V. Narayanan, R. Divakaruni","doi":"10.1109/IEDM.2018.8614518","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614518","url":null,"abstract":"We demonstrated more than 3 pairs of threshold voltage (Vt) devices by volume-less multiple Vt (multi-Vt) scheme plus dual work function metals (WFM) without performance and reliability degradation on 20nm gate length FinFET CMOS devices. Vt shifts over 200 mV were achieved for both nFET and pFET. The volume-less nature of this multi-Vt scheme relieves replacement metal gate (RMG) challenges and opens the path to offer multi-Vt solution for future highly scaled technologies.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"422 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123148189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614656
F. Kaklin, J. Raynor, R. Henderson
We demonstrate passive high voltage generation using photodiodes biased in the photovoltaic region of operation. The photodiodes are integrated in a 90nm back side illuminated (BSI) deep trench isolation (DTI) capable imaging process technology. Four equal area, DTI separated arrays of photodiodes are implemented on a single die and connected using on-chip transmission gates (TG). The TGs control interconnects between the four arrays, connecting them in series or in parallel. A series configuration successfully generates an open-circuit voltage of 1.98V at 1klux. The full array generates 423nW/mm2 at 1klux of white LED illumination in series mode and 425nW/mm2 in parallel mode. Peak conversion efficiency is estimated at 16.1%, at 5.7klux white LED illumination.
{"title":"High Voltage Generation Using Deep Trench Isolated Photodiodes in a Back Side Illuminated Process","authors":"F. Kaklin, J. Raynor, R. Henderson","doi":"10.1109/IEDM.2018.8614656","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614656","url":null,"abstract":"We demonstrate passive high voltage generation using photodiodes biased in the photovoltaic region of operation. The photodiodes are integrated in a 90nm back side illuminated (BSI) deep trench isolation (DTI) capable imaging process technology. Four equal area, DTI separated arrays of photodiodes are implemented on a single die and connected using on-chip transmission gates (TG). The TGs control interconnects between the four arrays, connecting them in series or in parallel. A series configuration successfully generates an open-circuit voltage of 1.98V at 1klux. The full array generates 423nW/mm2 at 1klux of white LED illumination in series mode and 425nW/mm2 in parallel mode. Peak conversion efficiency is estimated at 16.1%, at 5.7klux white LED illumination.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131756410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614520
Yi-Pei Tsai, J. Shih, Y. King, C. Lin
A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.
{"title":"7nm FinFET Plasma Charge Recording Device","authors":"Yi-Pei Tsai, J. Shih, Y. King, C. Lin","doi":"10.1109/IEDM.2018.8614520","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614520","url":null,"abstract":"A new wafer-level coupling plasma charge recorder fabricated with 7nm FinFET CMOS logic process is presented in this paper. This plasma ion charge recording device provides the historic and quantitative plasma ion charges of damascene metallization steps in advanced 7nm FinFET COMS logic processes. The high-resolution plasma ion recorder is formed by an accurate FinFET coupling structure to store the plasma ion level and distribution of the whole wafer. By a simple wafer-level WAT measurement, the promising plasma charge recording device can efficiently collect the accumulated ion charges, ion polarization, and tiny plasma fluctuation of each metallization process step in 7nm FinFET CMOS logic technologies, which definitely provides a superior device and method in developing a reliable and non-latent plasma damage process for 7nm FinFET technology and beyond.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132360156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614574
A. Khan
We present a simple, physical explanation of underlying microscopic mechanisms that lead to the emergence of the negative phenomena in ferroelectric materials. The material presented herein is inspired by the pedagogical treatment of ferroelectricity by Feynman and Kittel. In a toy model consisting of a linear one-dimensional chain of polarizable units (i.e., atoms or unit cells of a crystal structure), we show how simple electrostatic interactions can create a microscopic, positive feedback action that leads to negative capacitance phenomena. We point out that the unstable negative capacitance effect has its origin in the so called “polarization catastrophe” phenomenon which is essential to explain displacement type ferroelectrics. Furthermore, the fact that even in the negative capacitance state, the individual dipole always aligns along the direction of the local electrical field not opposite is made clear through the toy model. Finally, how the “$S$”-shaped polarization vs. applied electric field curve emerges out of the electrostatic interactions in an ordered set of polarizable units is shown.
{"title":"On the Microscopic Origin of Negative Capacitance in Ferroelectric Materials: A Toy Model","authors":"A. Khan","doi":"10.1109/IEDM.2018.8614574","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614574","url":null,"abstract":"We present a simple, physical explanation of underlying microscopic mechanisms that lead to the emergence of the negative phenomena in ferroelectric materials. The material presented herein is inspired by the pedagogical treatment of ferroelectricity by Feynman and Kittel. In a toy model consisting of a linear one-dimensional chain of polarizable units (i.e., atoms or unit cells of a crystal structure), we show how simple electrostatic interactions can create a microscopic, positive feedback action that leads to negative capacitance phenomena. We point out that the unstable negative capacitance effect has its origin in the so called “polarization catastrophe” phenomenon which is essential to explain displacement type ferroelectrics. Furthermore, the fact that even in the negative capacitance state, the individual dipole always aligns along the direction of the local electrical field not opposite is made clear through the toy model. Finally, how the “$S$”-shaped polarization vs. applied electric field curve emerges out of the electrostatic interactions in an ordered set of polarizable units is shown.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132927696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614587
E. Raymenants, D. Wan, S. Couet, O. Zografos, V. Nguyen, A. Vaysset, L. Souriau, A. Thiam, M. Manfrini, S. Brus, M. Heyns, D. Mocuta, D. Nikonov, S. Manipatruni, I. Young, T. Devolder, I. Radu
We present a scaled device based on magnetic domain wall (DW) transport for logic applications. The device consists of multiple magnetic tunnel junctions (MTJs) connected by the same magnetic free layer (FL). Magnetic domain walls are injected by spin-transfer torque (STT) at the input MTJs and are sensed by tunneling magnetoresistance (TMR) at the output MTJ after propagation through the FL. Logic functions can be built by merging several domain walls. By enabling real-time detection of long range DW transport, we demonstrate a spintronic component which can be used for either Boolean or non-Boolean logic.
{"title":"Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions","authors":"E. Raymenants, D. Wan, S. Couet, O. Zografos, V. Nguyen, A. Vaysset, L. Souriau, A. Thiam, M. Manfrini, S. Brus, M. Heyns, D. Mocuta, D. Nikonov, S. Manipatruni, I. Young, T. Devolder, I. Radu","doi":"10.1109/IEDM.2018.8614587","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614587","url":null,"abstract":"We present a scaled device based on magnetic domain wall (DW) transport for logic applications. The device consists of multiple magnetic tunnel junctions (MTJs) connected by the same magnetic free layer (FL). Magnetic domain walls are injected by spin-transfer torque (STT) at the input MTJs and are sensed by tunneling magnetoresistance (TMR) at the output MTJ after propagation through the FL. Logic functions can be built by merging several domain walls. By enabling real-time detection of long range DW transport, we demonstrate a spintronic component which can be used for either Boolean or non-Boolean logic.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132757226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614638
Huiming Chen, Shuai Zhang, N. Xu, Min Song, Xin Li, Ruofan Li, Yi Zeng, Jeongmin Hong, L. You
In this work, we have experimentally demonstrated the binary- and ternary-True Random Number Generators (B-TRNG and T-TRNG) based on the stochastic switching characteristics of the nano-scale Ta/CoFeB/MgO heterostructures with perpendicular magnetization anisotropy. For the first time, the random code generation utilizes the spin orbit torque (SOT) induced by current flowing in the heavy metal underneath the CoFeB layer. The 3-XOR post-processed random binary codes have passed the NIST SP800-22 test. Furthermore, the T-TRNG in the same ferromagnetic heterostructure with dual magnetic domains are also demonstrated, which provides a higher security level than its B-TRNG counterpart.
{"title":"Binary and Ternary True Random Number Generators Based on Spin Orbit Torque","authors":"Huiming Chen, Shuai Zhang, N. Xu, Min Song, Xin Li, Ruofan Li, Yi Zeng, Jeongmin Hong, L. You","doi":"10.1109/IEDM.2018.8614638","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614638","url":null,"abstract":"In this work, we have experimentally demonstrated the binary- and ternary-True Random Number Generators (B-TRNG and T-TRNG) based on the stochastic switching characteristics of the nano-scale Ta/CoFeB/MgO heterostructures with perpendicular magnetization anisotropy. For the first time, the random code generation utilizes the spin orbit torque (SOT) induced by current flowing in the heavy metal underneath the CoFeB layer. The 3-XOR post-processed random binary codes have passed the NIST SP800-22 test. Furthermore, the T-TRNG in the same ferromagnetic heterostructure with dual magnetic domains are also demonstrated, which provides a higher security level than its B-TRNG counterpart.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614682
T. Yamaguchi, T. Zhang, K. Omori, Y. Shimada, Y. Kunimune, T. Ide, M. Inoue, M. Matsuura
Highly reliable ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) film with Al nanoclusters embedded by sub-monolayer doping technique is demonstrated for the first time. Al nanoclusters increase the remnant polarization (Pr) and reduce the voltage necessary for polarization switching. Furthermore, the program and erase endurance at the cycle of more than 250k and the Pr retention at 85°C for 10 years are achieved. Al nanoclusters are formed by the partial oxidation of submonolayer metallic Al embedded in HZO films. Al nanoclusters enhance the large grain growth of orthorhombic-phase HZO during FE-HZO crystallization annealing. The reduction of grain boundaries caused by the large grain growth with Al nanoclusters effectively reduces the leakage current in the HZO film. As a result, reliability of the FE HZO film is significantly improved.
{"title":"Highly Reliable Ferroelectric Hf0.5Zr0.5O2 Film with Al Nanoclusters Embedded by Novel Sub-Monolayer Doping Technique","authors":"T. Yamaguchi, T. Zhang, K. Omori, Y. Shimada, Y. Kunimune, T. Ide, M. Inoue, M. Matsuura","doi":"10.1109/IEDM.2018.8614682","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614682","url":null,"abstract":"Highly reliable ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) film with Al nanoclusters embedded by sub-monolayer doping technique is demonstrated for the first time. Al nanoclusters increase the remnant polarization (Pr) and reduce the voltage necessary for polarization switching. Furthermore, the program and erase endurance at the cycle of more than 250k and the Pr retention at 85°C for 10 years are achieved. Al nanoclusters are formed by the partial oxidation of submonolayer metallic Al embedded in HZO films. Al nanoclusters enhance the large grain growth of orthorhombic-phase HZO during FE-HZO crystallization annealing. The reduction of grain boundaries caused by the large grain growth with Al nanoclusters effectively reduces the leakage current in the HZO film. As a result, reliability of the FE HZO film is significantly improved.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116624779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614499
Qiming Shao, Hao Wu, Quanjun Pan, Peng Zhang, L. Pan, Kin L. Wong, X. Che, Kang L. Wang
Spin-orbit torque (SOT)-MRAM is a promising candidate for future nonvolatile memory technology. Finding materials that have large SOT efficiency $(xi_{text{DL}})$ is critical for developing the SOT-MRAM. Topological insulators (TIs) have been shown to exhibit giant $xi_{text{DL}}$ (>1) at room temperature. However, integration of high $xi_{text{DL}}$ TIs with CoFeB with perpendicular magnetic anisotropy (PMA) at room temperature (RT) has not been achieved. In this work, we demonstrate a record-high $xi_{text{DL}}$ (∼2.66) in the (BiSb)2Te3 with PMA CoFeB and achieve magnetization switching with TI current density as low as $3times 10^{9}mathrm{A}/mathrm{m}^{2}$ at RT. For the first time, we propose to insert a light metal spacer between TI and CoFeB to achieve resistance matching and thus reduce write energy. We show that without insertion, TI/CoFeB show in-plane magnetic anisotropy but TIs show high $xi_{text{DL}}$, consistent with previous reports. We then insert a Mo spacer to achieve PMA at RT. We accurately determine the $xi_{text{DL}}$ using both second harmonic method and MOKE for the first time. We investigate the SOT-driven switching and discover a memristor-like behavior in the TI/Mo/CoFeB.
{"title":"Room Temperature Highly Efficient Topological Insulator/Mo/CoFeB Spin-Orbit Torque Memory with Perpendicular Magnetic Anisotropy","authors":"Qiming Shao, Hao Wu, Quanjun Pan, Peng Zhang, L. Pan, Kin L. Wong, X. Che, Kang L. Wang","doi":"10.1109/IEDM.2018.8614499","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614499","url":null,"abstract":"Spin-orbit torque (SOT)-MRAM is a promising candidate for future nonvolatile memory technology. Finding materials that have large SOT efficiency $(xi_{text{DL}})$ is critical for developing the SOT-MRAM. Topological insulators (TIs) have been shown to exhibit giant $xi_{text{DL}}$ (>1) at room temperature. However, integration of high $xi_{text{DL}}$ TIs with CoFeB with perpendicular magnetic anisotropy (PMA) at room temperature (RT) has not been achieved. In this work, we demonstrate a record-high $xi_{text{DL}}$ (∼2.66) in the (BiSb)2Te3 with PMA CoFeB and achieve magnetization switching with TI current density as low as $3times 10^{9}mathrm{A}/mathrm{m}^{2}$ at RT. For the first time, we propose to insert a light metal spacer between TI and CoFeB to achieve resistance matching and thus reduce write energy. We show that without insertion, TI/CoFeB show in-plane magnetic anisotropy but TIs show high $xi_{text{DL}}$, consistent with previous reports. We then insert a Mo spacer to achieve PMA at RT. We accurately determine the $xi_{text{DL}}$ using both second harmonic method and MOKE for the first time. We investigate the SOT-driven switching and discover a memristor-like behavior in the TI/Mo/CoFeB.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116764638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614711
Linsen Li, B. Magyari-Köpe, Ching-Hua Wang, S. Deshmukh, Zizhen Jiang, Haitong Li, Yi Yang, Huanglong Li, H. Tian, E. Pop, T. Ren, H. Wong
Two-dimensional (2D) tunnel heterojunctions with an H-shaped energy barrier could serve as ultrathin memory selectors with good symmetry, non-linearity, and high endurance. Atomically thin 2D layered materials can potentially deliver high on-state tunneling current density. We explore the design space for H-shaped memory selectors using heterojunctions of 2D layered materials, using physical modeling and first principles density functional theory (DFT) quantum transport simulations. The difference between simulations and the few existing experiments is also discussed. A selector must be designed to suit the resistive memory (1R) characteristics. We evaluate the H-shaped selector in the one-selector-one-resistor (1S1R) configuration and provide design guidelines for the heterojunction (metal/nL hBN/nL 2D material/nL hBN/metal) design to match with the 1R characteristics.
{"title":"First Principles Study of Memory Selectors using Heterojunctions of 2D Layered Materials","authors":"Linsen Li, B. Magyari-Köpe, Ching-Hua Wang, S. Deshmukh, Zizhen Jiang, Haitong Li, Yi Yang, Huanglong Li, H. Tian, E. Pop, T. Ren, H. Wong","doi":"10.1109/IEDM.2018.8614711","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614711","url":null,"abstract":"Two-dimensional (2D) tunnel heterojunctions with an H-shaped energy barrier could serve as ultrathin memory selectors with good symmetry, non-linearity, and high endurance. Atomically thin 2D layered materials can potentially deliver high on-state tunneling current density. We explore the design space for H-shaped memory selectors using heterojunctions of 2D layered materials, using physical modeling and first principles density functional theory (DFT) quantum transport simulations. The difference between simulations and the few existing experiments is also discussed. A selector must be designed to suit the resistive memory (1R) characteristics. We evaluate the H-shaped selector in the one-selector-one-resistor (1S1R) configuration and provide design guidelines for the heterojunction (metal/nL hBN/nL 2D material/nL hBN/metal) design to match with the 1R characteristics.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116894396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614498
A. Morello, G. Tosi, F. Mohiyaddin, V. Schmitt, V. Mourik, T. Botzem, A. Laucht, J. Pla, S. Tenberg, R. Savytskyy, M. Ma̧dzik, F. Hudson, A. Dzurak, K. Itoh, A. Jakob, B. C. Johnson, J. McCallum, D. Jamieson
We present a scalable strategy to manufacture quantum computer devices, by encoding quantum information in the combined electron-nuclear spin state of individual ion-implanted phosphorus dopant atoms in silicon. Our strategy allows a typical pitch between quantum bits of order 200 nm, and retains compatibility with the standard fabrication processes adopted in classical CMOS nanoelectronic devices. We theoretically predict fast and high-fidelity quantum logic operations, and present preliminary experimental progress towards the realization of a “flip-flop” qubit system.
{"title":"Scalable quantum computing with ion-implanted dopant atoms in silicon","authors":"A. Morello, G. Tosi, F. Mohiyaddin, V. Schmitt, V. Mourik, T. Botzem, A. Laucht, J. Pla, S. Tenberg, R. Savytskyy, M. Ma̧dzik, F. Hudson, A. Dzurak, K. Itoh, A. Jakob, B. C. Johnson, J. McCallum, D. Jamieson","doi":"10.1109/IEDM.2018.8614498","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614498","url":null,"abstract":"We present a scalable strategy to manufacture quantum computer devices, by encoding quantum information in the combined electron-nuclear spin state of individual ion-implanted phosphorus dopant atoms in silicon. Our strategy allows a typical pitch between quantum bits of order 200 nm, and retains compatibility with the standard fabrication processes adopted in classical CMOS nanoelectronic devices. We theoretically predict fast and high-fidelity quantum logic operations, and present preliminary experimental progress towards the realization of a “flip-flop” qubit system.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123566532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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