Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614499
Qiming Shao, Hao Wu, Quanjun Pan, Peng Zhang, L. Pan, Kin L. Wong, X. Che, Kang L. Wang
Spin-orbit torque (SOT)-MRAM is a promising candidate for future nonvolatile memory technology. Finding materials that have large SOT efficiency $(xi_{text{DL}})$ is critical for developing the SOT-MRAM. Topological insulators (TIs) have been shown to exhibit giant $xi_{text{DL}}$ (>1) at room temperature. However, integration of high $xi_{text{DL}}$ TIs with CoFeB with perpendicular magnetic anisotropy (PMA) at room temperature (RT) has not been achieved. In this work, we demonstrate a record-high $xi_{text{DL}}$ (∼2.66) in the (BiSb)2Te3 with PMA CoFeB and achieve magnetization switching with TI current density as low as $3times 10^{9}mathrm{A}/mathrm{m}^{2}$ at RT. For the first time, we propose to insert a light metal spacer between TI and CoFeB to achieve resistance matching and thus reduce write energy. We show that without insertion, TI/CoFeB show in-plane magnetic anisotropy but TIs show high $xi_{text{DL}}$, consistent with previous reports. We then insert a Mo spacer to achieve PMA at RT. We accurately determine the $xi_{text{DL}}$ using both second harmonic method and MOKE for the first time. We investigate the SOT-driven switching and discover a memristor-like behavior in the TI/Mo/CoFeB.
{"title":"Room Temperature Highly Efficient Topological Insulator/Mo/CoFeB Spin-Orbit Torque Memory with Perpendicular Magnetic Anisotropy","authors":"Qiming Shao, Hao Wu, Quanjun Pan, Peng Zhang, L. Pan, Kin L. Wong, X. Che, Kang L. Wang","doi":"10.1109/IEDM.2018.8614499","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614499","url":null,"abstract":"Spin-orbit torque (SOT)-MRAM is a promising candidate for future nonvolatile memory technology. Finding materials that have large SOT efficiency $(xi_{text{DL}})$ is critical for developing the SOT-MRAM. Topological insulators (TIs) have been shown to exhibit giant $xi_{text{DL}}$ (>1) at room temperature. However, integration of high $xi_{text{DL}}$ TIs with CoFeB with perpendicular magnetic anisotropy (PMA) at room temperature (RT) has not been achieved. In this work, we demonstrate a record-high $xi_{text{DL}}$ (∼2.66) in the (BiSb)2Te3 with PMA CoFeB and achieve magnetization switching with TI current density as low as $3times 10^{9}mathrm{A}/mathrm{m}^{2}$ at RT. For the first time, we propose to insert a light metal spacer between TI and CoFeB to achieve resistance matching and thus reduce write energy. We show that without insertion, TI/CoFeB show in-plane magnetic anisotropy but TIs show high $xi_{text{DL}}$, consistent with previous reports. We then insert a Mo spacer to achieve PMA at RT. We accurately determine the $xi_{text{DL}}$ using both second harmonic method and MOKE for the first time. We investigate the SOT-driven switching and discover a memristor-like behavior in the TI/Mo/CoFeB.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116764638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614518
R. Bao, Huimei Zhou, Miaomiao Wang, D. Guo, B. Haran, V. Narayanan, R. Divakaruni
We demonstrated more than 3 pairs of threshold voltage (Vt) devices by volume-less multiple Vt (multi-Vt) scheme plus dual work function metals (WFM) without performance and reliability degradation on 20nm gate length FinFET CMOS devices. Vt shifts over 200 mV were achieved for both nFET and pFET. The volume-less nature of this multi-Vt scheme relieves replacement metal gate (RMG) challenges and opens the path to offer multi-Vt solution for future highly scaled technologies.
我们在20nm栅极长度FinFET CMOS器件上，通过无体积多重Vt (multiple Vt)方案和双功功能金属(dual work function metals, WFM)，展示了超过3对阈值电压(Vt)器件的性能和可靠性没有下降。fet和fet均实现了200 mV以上的Vt位移。这种多电压门方案的无体积特性减轻了更换金属门(RMG)的挑战，并为未来高度规模化的技术提供多电压门解决方案开辟了道路。
{"title":"Extendable and Manufacturable Volume-less Multi-Vt Solution for 7nm Technology Node and Beyond","authors":"R. Bao, Huimei Zhou, Miaomiao Wang, D. Guo, B. Haran, V. Narayanan, R. Divakaruni","doi":"10.1109/IEDM.2018.8614518","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614518","url":null,"abstract":"We demonstrated more than 3 pairs of threshold voltage (Vt) devices by volume-less multiple Vt (multi-Vt) scheme plus dual work function metals (WFM) without performance and reliability degradation on 20nm gate length FinFET CMOS devices. Vt shifts over 200 mV were achieved for both nFET and pFET. The volume-less nature of this multi-Vt scheme relieves replacement metal gate (RMG) challenges and opens the path to offer multi-Vt solution for future highly scaled technologies.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"422 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123148189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614498
A. Morello, G. Tosi, F. Mohiyaddin, V. Schmitt, V. Mourik, T. Botzem, A. Laucht, J. Pla, S. Tenberg, R. Savytskyy, M. Ma̧dzik, F. Hudson, A. Dzurak, K. Itoh, A. Jakob, B. C. Johnson, J. McCallum, D. Jamieson
We present a scalable strategy to manufacture quantum computer devices, by encoding quantum information in the combined electron-nuclear spin state of individual ion-implanted phosphorus dopant atoms in silicon. Our strategy allows a typical pitch between quantum bits of order 200 nm, and retains compatibility with the standard fabrication processes adopted in classical CMOS nanoelectronic devices. We theoretically predict fast and high-fidelity quantum logic operations, and present preliminary experimental progress towards the realization of a “flip-flop” qubit system.
{"title":"Scalable quantum computing with ion-implanted dopant atoms in silicon","authors":"A. Morello, G. Tosi, F. Mohiyaddin, V. Schmitt, V. Mourik, T. Botzem, A. Laucht, J. Pla, S. Tenberg, R. Savytskyy, M. Ma̧dzik, F. Hudson, A. Dzurak, K. Itoh, A. Jakob, B. C. Johnson, J. McCallum, D. Jamieson","doi":"10.1109/IEDM.2018.8614498","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614498","url":null,"abstract":"We present a scalable strategy to manufacture quantum computer devices, by encoding quantum information in the combined electron-nuclear spin state of individual ion-implanted phosphorus dopant atoms in silicon. Our strategy allows a typical pitch between quantum bits of order 200 nm, and retains compatibility with the standard fabrication processes adopted in classical CMOS nanoelectronic devices. We theoretically predict fast and high-fidelity quantum logic operations, and present preliminary experimental progress towards the realization of a “flip-flop” qubit system.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123566532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614667
A. Subirats, A. Arreghini, R. Delhougne, E. Rosseel, A. Hikavyy, L. Breuil, S. V. Palayam, G. Van den bosch, D. Linten, A. Furnémont
We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices VT unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).
我们研究了HPAP对SCC 3D NAND器件的影响。我们表明该工艺可以降低陷阱密度，但陷阱对器件VT的影响不受影响。模拟和测量结果也表明，进一步的缩放可能导致单阱影响的增加。最后，我们测量到，尽管在很大程度上改善了设备的电气参数，但HPAP对内存性能(程序/擦除)没有影响，或者可能会略微降低内存性能(保留)。
{"title":"Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices","authors":"A. Subirats, A. Arreghini, R. Delhougne, E. Rosseel, A. Hikavyy, L. Breuil, S. V. Palayam, G. Van den bosch, D. Linten, A. Furnémont","doi":"10.1109/IEDM.2018.8614667","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614667","url":null,"abstract":"We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices VT unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614484
V. Venezia, Alan Chih-Wei Hsiung, Kelvin Ai, Xiang Zhao, Zhiqiang Lin, D. Mao, Armin Yazdani, E. Webster, L. Grant
A $1.5mu mathrm{m}$ pixel size, 8 mega pixel density, dual conversion gain (DCG), back side illuminated CMOS image sensor (CIS) is described having a linear full-well capacity (FWC) of 13ke- and total noise of 0.8e-RMS at 8x gain. The sensor adopts a world smallest $1.5mu mathrm{m}$ pitch, stacked pixel-level connection (SPLC) technology with greater than 8M connections, maximizing fill-factor of the photodiode and dimensions of the associated transistors to achieve a large FWC and low noise performance at the same time. In addition, by allocating transistors into two different layers, the DCG function can be realized with $1.5mu mathrm{m}$ pixel size.
{"title":"$1.5mu mathrm{m}$ Dual Conversion Gain, Backside Illuminated Image Sensor Using Stacked Pixel Level Connections with 13ke-Full-Well Capacitance and 0.8e-Noise","authors":"V. Venezia, Alan Chih-Wei Hsiung, Kelvin Ai, Xiang Zhao, Zhiqiang Lin, D. Mao, Armin Yazdani, E. Webster, L. Grant","doi":"10.1109/IEDM.2018.8614484","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614484","url":null,"abstract":"A $1.5mu mathrm{m}$ pixel size, 8 mega pixel density, dual conversion gain (DCG), back side illuminated CMOS image sensor (CIS) is described having a linear full-well capacity (FWC) of 13ke- and total noise of 0.8e-RMS at 8x gain. The sensor adopts a world smallest $1.5mu mathrm{m}$ pitch, stacked pixel-level connection (SPLC) technology with greater than 8M connections, maximizing fill-factor of the photodiode and dimensions of the associated transistors to achieve a large FWC and low noise performance at the same time. In addition, by allocating transistors into two different layers, the DCG function can be realized with $1.5mu mathrm{m}$ pixel size.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614695
K. Croes, C. Adelmann, C. Wilson, H. Zahedmanesh, O. Pedreira, C. Wu, A. Lesniewska, H. Oprins, S. Beyne, I. Ciofi, D. Kocaay, M. Stucchi, Z. Tokei
Reliability challenges of candidate metal systems to replace traditional Cu wiring in future interconnects are discussed. From a reliability perspective, a key opportunity is electromigration improvement: due to their high melting point and slower self-diffusion kinetics, higher current carrying capabilities are possible. Also, the higher cohesive energy and better resistance to oxidation of some metals potentially allows for barrierless integration, although adhesion properties must be carefully optimized. Besides avoiding small grain pinning and enabling high aspect ratio trench fill, the main processing challenges are identified to be a) avoiding seam voids, b) adhesion, c) CMP and d) disruptive metal etch. Main reliability challenges are related to higher mechanical stresses and higher joule heating which could lead to delamination during further processing and packaging and to enhanced electromigration in nearby metal lines.
{"title":"Interconnect metals beyond copper: reliability challenges and opportunities","authors":"K. Croes, C. Adelmann, C. Wilson, H. Zahedmanesh, O. Pedreira, C. Wu, A. Lesniewska, H. Oprins, S. Beyne, I. Ciofi, D. Kocaay, M. Stucchi, Z. Tokei","doi":"10.1109/IEDM.2018.8614695","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614695","url":null,"abstract":"Reliability challenges of candidate metal systems to replace traditional Cu wiring in future interconnects are discussed. From a reliability perspective, a key opportunity is electromigration improvement: due to their high melting point and slower self-diffusion kinetics, higher current carrying capabilities are possible. Also, the higher cohesive energy and better resistance to oxidation of some metals potentially allows for barrierless integration, although adhesion properties must be carefully optimized. Besides avoiding small grain pinning and enabling high aspect ratio trench fill, the main processing challenges are identified to be a) avoiding seam voids, b) adhesion, c) CMP and d) disruptive metal etch. Main reliability challenges are related to higher mechanical stresses and higher joule heating which could lead to delamination during further processing and packaging and to enhanced electromigration in nearby metal lines.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130040754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614588
S. Nakajima
Many challenges have been overcome in developing highly reliable, cost effective and excellent performance GaN HEMTs. We have focused on GaN HEMT on SiC, and have been shipping commercial GaN HEMTs for the base station market since 2005. The state of the art GaN HEMT has penetrated into the 4G/LTE base station. The efficiency advantage, based on its material properties will also attract 5G power amplifier designers. This paper explains our development history, and overviews the GaN HEMT power amplifiers in the 5G era.
{"title":"GaN HEMTs for 5G Base Station Applications","authors":"S. Nakajima","doi":"10.1109/IEDM.2018.8614588","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614588","url":null,"abstract":"Many challenges have been overcome in developing highly reliable, cost effective and excellent performance GaN HEMTs. We have focused on GaN HEMT on SiC, and have been shipping commercial GaN HEMTs for the base station market since 2005. The state of the art GaN HEMT has penetrated into the 4G/LTE base station. The efficiency advantage, based on its material properties will also attract 5G power amplifier designers. This paper explains our development history, and overviews the GaN HEMT power amplifiers in the 5G era.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128232464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614609
S. Miyamoto, K. Itoh
We present isotopically engineered Si-28/SiGe heterostructures for development of silicon-based quantum computers using a standard silicon CMOS integration technology. Our Si-28 quantum-wells are well-strained and demonstrate high electron mobility and large valley-splitting. These properties provide promising platforms for realization of highly integrated spin qubits working together with silicon CMOS circuits.
{"title":"Silicon Isotope Technology for Quantum Computing","authors":"S. Miyamoto, K. Itoh","doi":"10.1109/IEDM.2018.8614609","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614609","url":null,"abstract":"We present isotopically engineered Si-28/SiGe heterostructures for development of silicon-based quantum computers using a standard silicon CMOS integration technology. Our Si-28 quantum-wells are well-strained and demonstrate high electron mobility and large valley-splitting. These properties provide promising platforms for realization of highly integrated spin qubits working together with silicon CMOS circuits.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131114024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614495
Ching-Hua Wang, C. McClellan, Yuanyuan Shi, Xin Zheng, Victoria Chen, M. Lanza, E. Pop, H. Philip Wong
We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < $130 mumathrm{A}$ and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS2 transistor has low off-current due to the large band gap of monolayer MoS2$(mathrm{E}_{mathrm{g}} > 2 text{eV})$. We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.
{"title":"3D Monolithic Stacked 1T1R cells using Monolayer MoS2 FET and hBN RRAM Fabricated at Low (150°C) Temperature","authors":"Ching-Hua Wang, C. McClellan, Yuanyuan Shi, Xin Zheng, Victoria Chen, M. Lanza, E. Pop, H. Philip Wong","doi":"10.1109/IEDM.2018.8614495","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614495","url":null,"abstract":"We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < $130 mumathrm{A}$ and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS2 transistor has low off-current due to the large band gap of monolayer MoS2$(mathrm{E}_{mathrm{g}} > 2 text{eV})$. We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128913300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614497
Shengqiang Xu, Wei Wang, Yi-Chiau Huang, Yuan Dong, S. Masudy‐Panah, Hong Wang, X. Gong, Y. Yeo
High speed photo detection at two-micron-wavelength has been achieved with a GeSn/Ge multiple-quantum-well (MQW) photodiode (PD), demonstrating a 3-dB bandwidth $(f_{3-dB})$ above 10 GHz for the first time. The device layer stack was grown on a standard 300 mm (001) Si substrate using RPCVD, showing potential for large-scale integration. Radio frequency (RF) characterization was performed using $2- mumathrm{m}$ RF optical measurement setup. To our knowledge, this is also the first PDs on Si with direct RF measurement to quantitatively confirm the high speed functionality at $2 mu mathrm{m}$.
利用GeSn/Ge多量子阱(MQW)光电二极管(PD)实现了两微米波长的高速光检测，首次展示了10ghz以上的3db带宽$(f_{3-dB})$。利用RPCVD在标准300 mm (001) Si衬底上生长器件层堆栈，显示出大规模集成的潜力。使用$2- mu mathm {m}$ RF光学测量装置进行射频(RF)表征。据我们所知，这也是第一个具有直接射频测量的硅上pd，以定量确认在$2 mu mathm {m}$的高速功能。
{"title":"High Speed ($boldsymbol{f}_{3-boldsymbol{d}boldsymbol{B}}$ above 10 GHz) Photo Detection at Two-micron-wavelength Realized by GeSn/Ge Multiple-quantum-well Photodiode on a 300 mm Si Substrate","authors":"Shengqiang Xu, Wei Wang, Yi-Chiau Huang, Yuan Dong, S. Masudy‐Panah, Hong Wang, X. Gong, Y. Yeo","doi":"10.1109/IEDM.2018.8614497","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614497","url":null,"abstract":"High speed photo detection at two-micron-wavelength has been achieved with a GeSn/Ge multiple-quantum-well (MQW) photodiode (PD), demonstrating a 3-dB bandwidth $(f_{3-dB})$ above 10 GHz for the first time. The device layer stack was grown on a standard 300 mm (001) Si substrate using RPCVD, showing potential for large-scale integration. Radio frequency (RF) characterization was performed using $2- mumathrm{m}$ RF optical measurement setup. To our knowledge, this is also the first PDs on Si with direct RF measurement to quantitatively confirm the high speed functionality at $2 mu mathrm{m}$.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121764625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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