Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614660
L. Kumar, L. Jenni, M. Haluska, C. Roman, C. Hierold
Here, we report the intermixing of piezoresistive and conduction modulation current in a carbon nanotube field effect transistor (CNT - FET) based resonator. We show that due to static displacement of the nanotube, as a result of electrostatic actuation, the motional current at the resonance frequency consist of both current components. For instance at a DC gate bias of 1.3 V, 3/4 of the motional current is conduction modulation current while the rest arises from piezoresistive effects. The intermixing effect due to asymmetry influences the fundamental harmonic response as well as the physical nature of the electrical signal being sensed; both of which are important for understanding frequency harmonics in nanoresonators and developing efficient readout schemes for nanoscale sensors.
{"title":"Intermixing of motional currents in suspended CNT-FET based resonators","authors":"L. Kumar, L. Jenni, M. Haluska, C. Roman, C. Hierold","doi":"10.1109/IEDM.2018.8614660","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614660","url":null,"abstract":"Here, we report the intermixing of piezoresistive and conduction modulation current in a carbon nanotube field effect transistor (CNT - FET) based resonator. We show that due to static displacement of the nanotube, as a result of electrostatic actuation, the motional current at the resonance frequency consist of both current components. For instance at a DC gate bias of 1.3 V, 3/4 of the motional current is conduction modulation current while the rest arises from piezoresistive effects. The intermixing effect due to asymmetry influences the fundamental harmonic response as well as the physical nature of the electrical signal being sensed; both of which are important for understanding frequency harmonics in nanoresonators and developing efficient readout schemes for nanoscale sensors.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126794805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614653
L. Brunet, C. Fenouillet-Béranger, P. Batude, S. Beaurepaire, F. Ponthenier, N. Rambal, V. Mazzocchi, J. Pin, P. Acosta-Alba, S. Kerdilès, P. Besson, H. Fontaine, T. Lardin, F. Fournel, V. Larrey, F. Mazen, V. Balan, C. Morales, C. Guérin, V. Jousseaume, X. Federspiel, D. Ney, X. Garros, A. Roman, D. Scevola, P. Perreau, F. Kouemeni-Tchouake, L. Arnaud, C. Scibetta, S. Chevalliez, F. Aussenac, J. Aubin, S. Reboh, F. Andrieu, S. Maitrejean, M. Vinet
The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $mathrm{T}_{text{TOP}}=500^{circ}mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.
{"title":"Breakthroughs in 3D Sequential technology","authors":"L. Brunet, C. Fenouillet-Béranger, P. Batude, S. Beaurepaire, F. Ponthenier, N. Rambal, V. Mazzocchi, J. Pin, P. Acosta-Alba, S. Kerdilès, P. Besson, H. Fontaine, T. Lardin, F. Fournel, V. Larrey, F. Mazen, V. Balan, C. Morales, C. Guérin, V. Jousseaume, X. Federspiel, D. Ney, X. Garros, A. Roman, D. Scevola, P. Perreau, F. Kouemeni-Tchouake, L. Arnaud, C. Scibetta, S. Chevalliez, F. Aussenac, J. Aubin, S. Reboh, F. Andrieu, S. Maitrejean, M. Vinet","doi":"10.1109/IEDM.2018.8614653","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614653","url":null,"abstract":"The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $mathrm{T}_{text{TOP}}=500^{circ}mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123290399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614522
Yingchao Zhang, Ning Zheng, Yinji Ma, Tao Xie, Xue Feng
Peripheral nerves stimulation has been widely used in clinical practices, such as the vagus nerve stimulation (VNS) for heart failure, and motor nerve stimulation for controlling the prosthetics. However, the nerve injuries induced by the large mechanical and geometrical mismatch and complex surgical implantation process have restricted the further applications. Here, inspired by twining plants such as morning glories, we developed a 3D neural electrode that integrates the nano-gold film on flexible shape memory polymer (SMP) substrate from 2D planar state. Upon the response to 50°C normal saline, the flattened neural electrodes can self-climb to the 3D peripheral nerves with the aid of the shape memory effect. Two in vivo animal experiments are used to demonstrate the clinical practicality, i.e., VNS for the control of the heart rate (HR) and sciatic nerve stimulation for the control of the leg's movements. This technology offers a paradigm that fabricating the 3D bioelectronics in 2D planar state to match the 3D biological tissues by utilizing smart materials, and shows great potentials in clinical practices.
{"title":"Bio-inspired 3D neural electrodes for the peripheral nerves stimulation using shape memory polymers","authors":"Yingchao Zhang, Ning Zheng, Yinji Ma, Tao Xie, Xue Feng","doi":"10.1109/IEDM.2018.8614522","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614522","url":null,"abstract":"Peripheral nerves stimulation has been widely used in clinical practices, such as the vagus nerve stimulation (VNS) for heart failure, and motor nerve stimulation for controlling the prosthetics. However, the nerve injuries induced by the large mechanical and geometrical mismatch and complex surgical implantation process have restricted the further applications. Here, inspired by twining plants such as morning glories, we developed a 3D neural electrode that integrates the nano-gold film on flexible shape memory polymer (SMP) substrate from 2D planar state. Upon the response to 50°C normal saline, the flattened neural electrodes can self-climb to the 3D peripheral nerves with the aid of the shape memory effect. Two in vivo animal experiments are used to demonstrate the clinical practicality, i.e., VNS for the control of the heart rate (HR) and sciatic nerve stimulation for the control of the leg's movements. This technology offers a paradigm that fabricating the 3D bioelectronics in 2D planar state to match the 3D biological tissues by utilizing smart materials, and shows great potentials in clinical practices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126482282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614648
Che-Chia Chang, Pin-Chun Chen, B. Hudec, Po-Tsun Liu, T. Hou
This work provides a complete framework, including device, architecture, and algorithm, for implementing bio-inspired supervised spiking neural networks (SNNs) on hardware. An analog synapse with atypical dual bipolar resistive-switching (D-BRS) modes demonstrates interchangeable Hebbian spiking-timing-dependent plasticity (STDP) and anti-Hebbian STDP, and it is capable of implementing supervised ReSuMe SNNs in crossbar arrays. By using an “exchange” update scheme, accurate supervised learning (∼96% for MNIST) is achieved in a compact network.
这项工作提供了一个完整的框架，包括设备，架构和算法，用于在硬件上实现生物启发的监督尖峰神经网络(snn)。具有非典型双极电阻开关(D-BRS)模式的模拟突触具有可互换的Hebbian spike - time -dependent plasticity (STDP)和anti-Hebbian STDP，并且能够在交叉棒阵列中实现有监督的ReSuMe snn。通过使用“交换”更新方案，在紧凑的网络中实现了精确的监督学习(MNIST为96%)。
{"title":"Interchangeable Hebbian and Anti-Hebbian STDP Applied to Supervised Learning in Spiking Neural Network","authors":"Che-Chia Chang, Pin-Chun Chen, B. Hudec, Po-Tsun Liu, T. Hou","doi":"10.1109/IEDM.2018.8614648","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614648","url":null,"abstract":"This work provides a complete framework, including device, architecture, and algorithm, for implementing bio-inspired supervised spiking neural networks (SNNs) on hardware. An analog synapse with atypical dual bipolar resistive-switching (D-BRS) modes demonstrates interchangeable Hebbian spiking-timing-dependent plasticity (STDP) and anti-Hebbian STDP, and it is capable of implementing supervised ReSuMe SNNs in crossbar arrays. By using an “exchange” update scheme, accurate supervised learning (∼96% for MNIST) is achieved in a compact network.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115965597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614570
J. Jourdon, S. Lhostis, S. Moreau, J. Chossat, M. Arnoux, C. Sart, Y. Henrion, P. Lamontagne, L. Arnaud, N. Bresson, V. Balan, C. Euvrard, Y. Exbrayat, D. Scevola, E. Deloffre, S. Mermoz, A. Martin, H. Bilgen, F. André, C. Charles, D. Bouchu, A. Farcy, S. Guillaumet, A. Jouve, H. Frémont, S. Chéramy
Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A study of the influence of hybrid bonding pitch shrinkage on a 3D stacked backside illuminated CMOS image sensor was performed from a process, device performance and robustness perspectives, from $8.8 mumathrm{m}$ down to $1.44 mu mathrm{m}$ bonding pitches. As a result no defect related to smaller bonding pads was evidenced neither by thermal cycling nor by electromigration, thus validating fine-pitch hybrid bonding robustness and introduction for next generation image sensors.
{"title":"Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness","authors":"J. Jourdon, S. Lhostis, S. Moreau, J. Chossat, M. Arnoux, C. Sart, Y. Henrion, P. Lamontagne, L. Arnaud, N. Bresson, V. Balan, C. Euvrard, Y. Exbrayat, D. Scevola, E. Deloffre, S. Mermoz, A. Martin, H. Bilgen, F. André, C. Charles, D. Bouchu, A. Farcy, S. Guillaumet, A. Jouve, H. Frémont, S. Chéramy","doi":"10.1109/IEDM.2018.8614570","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614570","url":null,"abstract":"Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A study of the influence of hybrid bonding pitch shrinkage on a 3D stacked backside illuminated CMOS image sensor was performed from a process, device performance and robustness perspectives, from $8.8 mumathrm{m}$ down to $1.44 mu mathrm{m}$ bonding pitches. As a result no defect related to smaller bonding pads was evidenced neither by thermal cycling nor by electromigration, thus validating fine-pitch hybrid bonding robustness and introduction for next generation image sensors.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121171755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614690
B. Shankar, Ankit Soni, Sayak Dutta Gupta, S. Shikha, Sandeep Singh, S. Raghavan, M. Shrivastava
This experimental study reports first observations of (i) SOA boundary shift in GaN HEMTs and (ii) early time to fail of vertical AIGaN/GaN Epi stack under fast changing (sub-10ns risetime) cyclic transient stress conditions for a 600V qualified commercial grade HEMT stack. It is shown that a stack qualified for 10 years lifetime under DC stress, fails faster under cyclic transient stress. Integrated electrical and mechanical stress characterization routine involving Raman/PL mapping and CL spectroscopy reveals material limited unique failure physics under transient stress condition. Failure analysis using cross-sectional TEM investigations reveal signature of different degradation and failure mechanism under transient and DC stress conditions. A failure model is proposed for failure under cyclic transient stress.
本实验研究报告了第一次观察到(i) GaN HEMT中的SOA边界位移和(ii)垂直AIGaN/GaN Epi堆栈在快速变化(上升时间低于10ns)循环瞬态应力条件下的早期失效时间，用于600V合格的商业级HEMT堆栈。结果表明，在直流应力作用下具有10年寿命的叠层在循环瞬态应力作用下失效更快。包括拉曼/PL映射和CL光谱在内的综合电气和机械应力表征程序揭示了材料在瞬态应力条件下有限的独特失效物理。在瞬态和直流应力条件下，采用透射电镜对其进行了破坏分析，揭示了不同的退化特征和破坏机制。提出了循环瞬态应力作用下的失效模型。
{"title":"Time Dependent Early breakdown of AIGaN/GaN Epi Stacks and Shift in SOA Boundary of HEMTs Under Fast Cyclic Transient Stress","authors":"B. Shankar, Ankit Soni, Sayak Dutta Gupta, S. Shikha, Sandeep Singh, S. Raghavan, M. Shrivastava","doi":"10.1109/IEDM.2018.8614690","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614690","url":null,"abstract":"This experimental study reports first observations of (i) SOA boundary shift in GaN HEMTs and (ii) early time to fail of vertical AIGaN/GaN Epi stack under fast changing (sub-10ns risetime) cyclic transient stress conditions for a 600V qualified commercial grade HEMT stack. It is shown that a stack qualified for 10 years lifetime under DC stress, fails faster under cyclic transient stress. Integrated electrical and mechanical stress characterization routine involving Raman/PL mapping and CL spectroscopy reveals material limited unique failure physics under transient stress condition. Failure analysis using cross-sectional TEM investigations reveal signature of different degradation and failure mechanism under transient and DC stress conditions. A failure model is proposed for failure under cyclic transient stress.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121396001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614699
Yansong Yang, Ruochen Lu, S. Gong
This paper presents a micro-electro-mechanical system (MEMS) filter at 10.8 GHz as the first step of scaling electromechanical filters towards fifth-generation (5G) frequencies beyond 6 GHz. The scaling of the center frequency to 10. 8 GHz is made possible by resorting to a higher order asymmetrical lamb wave mode (A3) in lithium niobate (LiNbO3) MEMS resonators. The filter is then constructed using A3 resonator arrays in a ladder configuration. The fabricated resonator has demonstrated an electromechanical coupling $(k_{t}^{ 2})$ of 3.6% and a quality factor ($Q$) of 337. The $Q$ is among the highest reported for piezoelectric MEMS resonators operating at this frequency range. The fabricated filter at 10.8 GHz has a 3 dB bandwidth of 70 MHz, a minimum insertion loss of 3.7 dB, an in-band ripple less than 0.1 dB, and a compact footprint of $0.7times 0.5 text{mm}^{2}$.
{"title":"Scaling Acoustic Filters Towards 5G","authors":"Yansong Yang, Ruochen Lu, S. Gong","doi":"10.1109/IEDM.2018.8614699","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614699","url":null,"abstract":"This paper presents a micro-electro-mechanical system (MEMS) filter at 10.8 GHz as the first step of scaling electromechanical filters towards fifth-generation (5G) frequencies beyond 6 GHz. The scaling of the center frequency to 10. 8 GHz is made possible by resorting to a higher order asymmetrical lamb wave mode (A3) in lithium niobate (LiNbO3) MEMS resonators. The filter is then constructed using A3 resonator arrays in a ladder configuration. The fabricated resonator has demonstrated an electromechanical coupling $(k_{t}^{ 2})$ of 3.6% and a quality factor ($Q$) of 337. The $Q$ is among the highest reported for piezoelectric MEMS resonators operating at this frequency range. The fabricated filter at 10.8 GHz has a 3 dB bandwidth of 70 MHz, a minimum insertion loss of 3.7 dB, an in-band ripple less than 0.1 dB, and a compact footprint of $0.7times 0.5 text{mm}^{2}$.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128075444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614530
C. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, L. Czornomaz
We demonstrate RF-compatible quantum well InGaAs MOSFETs integrated on Si substrates, with $L_{mathrm{G}}$ down to 14 nm and a Si CMOS compatible RMG fabrication flow. Devices exhibit simultaneously extrapolated $f_{mathrm{t}}$ and $f_{max}$ of 370 and 310 GHz, respectively, the highest reported combined $f_{mathrm{t}}/f_{max}$ for III-V MOSFETs on Si. This is enabled by the scaled $L_{mathrm{G}}, g_{mathrm{m}}$ of $1.75 text{mS}/mu mathrm{n}$, 8 nm source and drain spacers and raised source and drain extensions maintaining low access resistance. The use of the InP/In0.75Ga0.25As/InP quantum well offers three times higher electron mobility and a 60% increase of $g_{mathrm{m}}$, compared to reference devices.
我们展示了集成在Si衬底上的rf兼容量子阱InGaAs mosfet, $L_{mathrm{G}}$低至14 nm，并具有Si CMOS兼容的RMG制造流程。器件同时外推$f_{mathrm{t}}$和$f_{max}$分别为370 GHz和310 GHz，这是硅基III-V mosfet的最高报道组合$f_{mathrm{t}}/f_{max}$。这是通过$1.75 text{mS}/mu mathrm{n}$的缩放$L_{mathrm{G}}, g_{mathrm{m}}$, 8纳米源极和漏极隔离器以及提高源极和漏极扩展来实现的，以保持低访问电阻。使用InP/In0.75Ga0.25As/InP量子阱提供了三倍高的电子迁移率和60% increase of $g_{mathrm{m}}$, compared to reference devices.
{"title":"High Performance Quantum Well InGaAs-On-Si MOSFETs With sub-20 nm Gate Length For RF Applications","authors":"C. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, L. Czornomaz","doi":"10.1109/IEDM.2018.8614530","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614530","url":null,"abstract":"We demonstrate RF-compatible quantum well InGaAs MOSFETs integrated on Si substrates, with <tex>$L_{mathrm{G}}$</tex> down to 14 nm and a Si CMOS compatible RMG fabrication flow. Devices exhibit simultaneously extrapolated <tex>$f_{mathrm{t}}$</tex> and <tex>$f_{max}$</tex> of 370 and 310 GHz, respectively, the highest reported combined <tex>$f_{mathrm{t}}/f_{max}$</tex> for III-V MOSFETs on Si. This is enabled by the scaled <tex>$L_{mathrm{G}}, g_{mathrm{m}}$</tex> of <tex>$1.75 text{mS}/mu mathrm{n}$</tex>, 8 nm source and drain spacers and raised source and drain extensions maintaining low access resistance. The use of the InP/In<inf>0.75</inf>Ga<inf>0.25</inf>As/InP quantum well offers three times higher electron mobility and a 60% increase of <tex>$g_{mathrm{m}}$</tex>, compared to reference devices.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132699642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614618
T. Hennen, D. Bedau, J. Rupp, C. Funck, S. Menzel, M. Grobis, R. Waser, D. Wouters
In this work, thin film (down to 10 nm) $(mathrm{V}_{1-mathrm{x}}text{Cr}_{mathrm{x}})_{2}mathrm{O}_{3}$ Mott-oxide based nano-devices (electrode width down to 120 nm) are fabricated for the first time. The devices show volatile threshold switching and NDR caused by thermal feedback. Fast (< 10 ns) and very stable (< 5% variation) cycle to cycle threshold switching is obtained over 1012 cycles. Thickness and area dependence of the NDR curves are consistent with uniform volume switching and are explained with a thermal feedback model calibrated to the temperature dependent conductance of the $(mathrm{V}_{1-mathrm{x}}text{Cr}_{mathrm{x}})_{2}mathrm{O}_{3}$ films, enabling predictions for further scaled device geometries.
{"title":"Forming-free Mott-oxide threshold selector nanodevice showing s-type NDR with high endurance (> 1012 cycles), excellent Vth stability (5%), fast (< 10 ns) switching, and promising scaling properties","authors":"T. Hennen, D. Bedau, J. Rupp, C. Funck, S. Menzel, M. Grobis, R. Waser, D. Wouters","doi":"10.1109/IEDM.2018.8614618","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614618","url":null,"abstract":"In this work, thin film (down to 10 nm) $(mathrm{V}_{1-mathrm{x}}text{Cr}_{mathrm{x}})_{2}mathrm{O}_{3}$ Mott-oxide based nano-devices (electrode width down to 120 nm) are fabricated for the first time. The devices show volatile threshold switching and NDR caused by thermal feedback. Fast (< 10 ns) and very stable (< 5% variation) cycle to cycle threshold switching is obtained over 1012 cycles. Thickness and area dependence of the NDR curves are consistent with uniform volume switching and are explained with a thermal feedback model calibrated to the temperature dependent conductance of the $(mathrm{V}_{1-mathrm{x}}text{Cr}_{mathrm{x}})_{2}mathrm{O}_{3}$ films, enabling predictions for further scaled device geometries.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133957137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/iedm.2018.8614639
M. Bocquet, T. Hirtzlin, Jacques-Olivier Klein, E. Nowak, E. Vianello, J. Portal, D. Querlioz
RRAM-based in-Memory Computing is an exciting road for implementing highly energy efficient neural networks. This vision is however challenged by RRAM variability, as the efficient implementation of in-memory computing does not allow error correction. In this work, we fabricated and tested a differential HfO2-based memory structure and its associated sense circuitry, which are ideal for in-memory computing. For the first time, we show that our approach achieves the same reliability benefits as error correction, but without any CMOS overhead. We show, also for the first time, that it can naturally implement Binarized Deep Neural Networks, a very recent development of Artificial Intelligence, with extreme energy efficiency, and that the system is fully satisfactory for image recognition applications. Finally, we evidence how the extra reliability provided by the differential memory allows programming the devices in low voltage conditions, where they feature high endurance of billions of cycles.
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