W. Tong, Alireza Ganjali, Omidreza Ghaffari, Chady Alsayed, L. Fréchette, J. Sylvestre
In a two-phase immersion cooling system, boiling on the spreader surface has been experimentally found to be non-uniform, and it is highly related to the surface temperature and the heat transfer coefficient. An experimentally obtained temperature-dependent boiling heat transfer coefficient has been applied to a numerical model to investigate the spreader's cooling performance. It is found that the surface temperature distribution becomes less uniform with higher input power. But it is more uniform when the thickness is increased. By defining the characteristic temperatures that represent different boiling regimes on the surface, the fraction of the surface area that has reached the critical heat flux has been numerically calculated, showing that increasing the thickness from 1 mm to 6 mm decreases the critical heat flux reached area by 23% at saturation liquid temperatures. Therefore, on the thicker spreader, more of the surface is utilized for nucleate boiling while localized hot regions that lead to surface dry-out are avoided. At a base temperature of 90 oC, the optimal thickness is found to be 4 mm, beyond which no significant improvement in heat removal can be obtained. Lower coolant temperatures can further increase the heat removal; it is reduced from an 18% improvement in the input power for the 1 mm case to only 3% in the 6 mm case for a coolant temperature drop of 24 oC. Therefore, a trade-off exists between the cost of maintaining the low liquid temperature and the increased heat removal capacity.
{"title":"Numerical and Parametric Investigation of the Effect of Heat Spreading On Boiling of a Dielectric Liquid for Immersion Cooling of Electronics","authors":"W. Tong, Alireza Ganjali, Omidreza Ghaffari, Chady Alsayed, L. Fréchette, J. Sylvestre","doi":"10.1115/1.4053310","DOIUrl":"https://doi.org/10.1115/1.4053310","url":null,"abstract":"\u0000 In a two-phase immersion cooling system, boiling on the spreader surface has been experimentally found to be non-uniform, and it is highly related to the surface temperature and the heat transfer coefficient. An experimentally obtained temperature-dependent boiling heat transfer coefficient has been applied to a numerical model to investigate the spreader's cooling performance. It is found that the surface temperature distribution becomes less uniform with higher input power. But it is more uniform when the thickness is increased. By defining the characteristic temperatures that represent different boiling regimes on the surface, the fraction of the surface area that has reached the critical heat flux has been numerically calculated, showing that increasing the thickness from 1 mm to 6 mm decreases the critical heat flux reached area by 23% at saturation liquid temperatures. Therefore, on the thicker spreader, more of the surface is utilized for nucleate boiling while localized hot regions that lead to surface dry-out are avoided. At a base temperature of 90 oC, the optimal thickness is found to be 4 mm, beyond which no significant improvement in heat removal can be obtained. Lower coolant temperatures can further increase the heat removal; it is reduced from an 18% improvement in the input power for the 1 mm case to only 3% in the 6 mm case for a coolant temperature drop of 24 oC. Therefore, a trade-off exists between the cost of maintaining the low liquid temperature and the increased heat removal capacity.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"61 3","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41302807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conventional reliability tests for the evaluation of pad cratering resistance are mainly classified into two categories: the board level test and the joint level test. The board level test is to imitate the loading conditions during normal operation. However, this type of test is expensive and not flexible. The joint level test is used extensively in the industry because it has the advantages of lower cost, higher throughput, and more quantitative results. It also allows the elimination of confounding factors such as PCB and component stiffness. Therefore, it is always desirable to predict the board level performance by a joint level test. In order to achieve this objective, the correlation between the joint level and the board level tests must be fully understood. Nevertheless, a precise correlation between the two types of tests for pad cratering evaluation is yet to be defined. This study investigates the pad cratering failure mode for the correlation of critical failure factors between joint and board level tests. An intermediate critical failure factor could be taken as a failure criterion in board level testing for failure detection. For verifying the validity of such a failure criterion, an experimental study should be performed. The 4-point bending test is chosen as the board level test for critical failure factor validation. In addition, an innovative pin shear test method is developed as the joint level test for failure factor detection. Both test methods are assessed by a series of parametric studies with an optimized process to ensure the accuracy of the results. From the results of the experimental study and simulation, the critical failure factor correlation is established between the board level 4-point bending and the joint level pin shear test. Using finite element analysis (FEA), the critical failure strain is identified from the pin shear test model and will be employed as the board level failure criterion. Subsequently the obtained failure criterion is verified by a 4-point bending model. As a result, this indirect correlation method can predict the board level failure with various geometric parameters.
{"title":"Prediction of Board Level Pad Cratering Strength with the Pre-Defined Failure Criteria From Joint Level Testing","authors":"Qiming Zhang, S. Lee","doi":"10.1115/1.4053309","DOIUrl":"https://doi.org/10.1115/1.4053309","url":null,"abstract":"\u0000 Conventional reliability tests for the evaluation of pad cratering resistance are mainly classified into two categories: the board level test and the joint level test. The board level test is to imitate the loading conditions during normal operation. However, this type of test is expensive and not flexible. The joint level test is used extensively in the industry because it has the advantages of lower cost, higher throughput, and more quantitative results. It also allows the elimination of confounding factors such as PCB and component stiffness. Therefore, it is always desirable to predict the board level performance by a joint level test. In order to achieve this objective, the correlation between the joint level and the board level tests must be fully understood. Nevertheless, a precise correlation between the two types of tests for pad cratering evaluation is yet to be defined.\u0000 This study investigates the pad cratering failure mode for the correlation of critical failure factors between joint and board level tests. An intermediate critical failure factor could be taken as a failure criterion in board level testing for failure detection. For verifying the validity of such a failure criterion, an experimental study should be performed. The 4-point bending test is chosen as the board level test for critical failure factor validation. In addition, an innovative pin shear test method is developed as the joint level test for failure factor detection. Both test methods are assessed by a series of parametric studies with an optimized process to ensure the accuracy of the results. From the results of the experimental study and simulation, the critical failure factor correlation is established between the board level 4-point bending and the joint level pin shear test. Using finite element analysis (FEA), the critical failure strain is identified from the pin shear test model and will be employed as the board level failure criterion. Subsequently the obtained failure criterion is verified by a 4-point bending model. As a result, this indirect correlation method can predict the board level failure with various geometric parameters.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42201975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Omidreza Ghaffari, W. Tong, Y. N. Larimi, C. A. Sayed, Alireza Ganjali, J. Morissette, Francis Grenier, Simon Jasmin, L. Fréchette, J. Sylvestre
This paper investigated the effect of heat spreading on the boiling of the Novec 649™ for two-phase immersion cooling of electronics. Reference pool boiling tests were performed by attaching a 25.4 mm by 25.4 mm square copper plate to a same-sized heater, thus minimizing lateral heat spreading. Experimental measurements showed that the critical heat flux (CHF) happened at a heat flux of 17.4±0.8 W/cm2. Then, lateral heat spreading through the heat spreader was studied by attaching larger (47 mm by 47 mm) spreaders with four different thicknesses to the copper plate. With an increase in the integrated heat spreader (IHS) thickness from 1 mm to 6 mm, the CHF increased by more than 60% at the saturation condition. One plate was a 1 mm-thick IHS removed from a commercial microprocessor. In this case, the CHF happens at 8.6 W/cm2 (50% lower compared to the reference case) in the saturation condition. At CHF, the boiling can be observed on the whole surface, with columns and slugs regime at the center and the fully developed nucleate boiling regime at the edges. This nonuniform boiling was more pronounced in subcooled conditions, in which the CHF occurred at the center while there were regions at the edges that had no boiling. Finally, the performance of a microporous-coated IHS (with 3.15 mm thickness) was compared to the 6 mm thick IHS. The thermal resistance was almost equal for powers above 200 W. This indicates that lateral heat spreading is a critical parameter for the thermal design of immersion cooling along with microporous coating.
本文研究了热传导对电子设备两相浸没冷却Novec 649™沸腾的影响。参考池沸腾试验是通过将25.4 mm × 25.4 mm的方形铜板贴在相同尺寸的加热器上进行的，从而最大限度地减少了侧向热量传播。实验测量表明，临界热流密度(CHF)为17.4±0.8 W/cm2。然后，通过将四种不同厚度的较大(47mm × 47mm)的散热器连接到铜板上，研究了通过散热器的侧向散热。饱和条件下，随着集成散热器(IHS)厚度从1 mm增加到6 mm, CHF增加了60%以上。一块板是从商用微处理器上拆下来的1毫米厚的IHS。在这种情况下，CHF在饱和条件下发生在8.6 W/cm2(比参考情况低50%)。在高温下，整个表面都可以观察到沸腾，中心为柱状和段塞状，边缘为充分发展的核状沸腾。这种不均匀沸腾在过冷条件下更为明显，在过冷条件下，CHF发生在中心，而边缘区域没有沸腾。最后，将微孔涂层的IHS(厚度为3.15 mm)与6 mm厚的IHS进行了性能比较。当功率大于200w时，热阻几乎相等。这表明横向传热是微孔涂层浸没冷却热设计的关键参数。
{"title":"Experimental Investigation of the Effect of Heat Spreading on Boiling of a Dielectric Liquid for Immersion Cooling of Electronics","authors":"Omidreza Ghaffari, W. Tong, Y. N. Larimi, C. A. Sayed, Alireza Ganjali, J. Morissette, Francis Grenier, Simon Jasmin, L. Fréchette, J. Sylvestre","doi":"10.1115/1.4051943","DOIUrl":"https://doi.org/10.1115/1.4051943","url":null,"abstract":"\u0000 This paper investigated the effect of heat spreading on the boiling of the Novec 649™ for two-phase immersion cooling of electronics. Reference pool boiling tests were performed by attaching a 25.4 mm by 25.4 mm square copper plate to a same-sized heater, thus minimizing lateral heat spreading. Experimental measurements showed that the critical heat flux (CHF) happened at a heat flux of 17.4±0.8 W/cm2. Then, lateral heat spreading through the heat spreader was studied by attaching larger (47 mm by 47 mm) spreaders with four different thicknesses to the copper plate. With an increase in the integrated heat spreader (IHS) thickness from 1 mm to 6 mm, the CHF increased by more than 60% at the saturation condition. One plate was a 1 mm-thick IHS removed from a commercial microprocessor. In this case, the CHF happens at 8.6 W/cm2 (50% lower compared to the reference case) in the saturation condition. At CHF, the boiling can be observed on the whole surface, with columns and slugs regime at the center and the fully developed nucleate boiling regime at the edges. This nonuniform boiling was more pronounced in subcooled conditions, in which the CHF occurred at the center while there were regions at the edges that had no boiling. Finally, the performance of a microporous-coated IHS (with 3.15 mm thickness) was compared to the 6 mm thick IHS. The thermal resistance was almost equal for powers above 200 W. This indicates that lateral heat spreading is a critical parameter for the thermal design of immersion cooling along with microporous coating.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"63503030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through the application of cryogenic cooling via liquid nitrogen (LN2), the power consumption of a CPU was substantially reduced. Using a digitally controlled solenoid valve and an additively manufactured cold plate, the manual process of LN2 cooling was automated for precise control of cold plate temperature. The power consumption and frequency relationship of the processor were established across three different thermal solutions to demonstrate the effect of temperature on this relationship. It was found that power consumption of the processor decreased at lower temperatures due to a reduction in current leakage and the core voltage necessary for stable operation. This culminated in a reduction of up to 10.7% in processor power consumption for the automated solution and 21.5% for the manual LN2 solution when compared to the air-cooled baseline. Due to the binary nature of the solenoid valve used, flow rate was tuned via an in-line needle valve to increase thermal stability. It was found that for lower flow rates, approximately 5.0 g/s, temperatures oscillated within a range of ±11.5 °C while for higher flow rates of 10–12 g/s, generated amplitudes are as small as ±3.5 °C. Additionally, several tests measured the rate of LN2 consumption and found that the automated solution used 230%–280% more coolant than the manual thermal solution, implying there is room for improvement in the cold plate geometry, LN2 vapor exhaust design, and coolant delivery optimization.
{"title":"Viability of Cryogenic Cooling to Reduce Processor Power Consumption","authors":"Alec Nordlund, M. Harrison, J. Gess","doi":"10.1115/1.4051752","DOIUrl":"https://doi.org/10.1115/1.4051752","url":null,"abstract":"\u0000 Through the application of cryogenic cooling via liquid nitrogen (LN2), the power consumption of a CPU was substantially reduced. Using a digitally controlled solenoid valve and an additively manufactured cold plate, the manual process of LN2 cooling was automated for precise control of cold plate temperature. The power consumption and frequency relationship of the processor were established across three different thermal solutions to demonstrate the effect of temperature on this relationship. It was found that power consumption of the processor decreased at lower temperatures due to a reduction in current leakage and the core voltage necessary for stable operation. This culminated in a reduction of up to 10.7% in processor power consumption for the automated solution and 21.5% for the manual LN2 solution when compared to the air-cooled baseline. Due to the binary nature of the solenoid valve used, flow rate was tuned via an in-line needle valve to increase thermal stability. It was found that for lower flow rates, approximately 5.0 g/s, temperatures oscillated within a range of ±11.5 °C while for higher flow rates of 10–12 g/s, generated amplitudes are as small as ±3.5 °C. Additionally, several tests measured the rate of LN2 consumption and found that the automated solution used 230%–280% more coolant than the manual thermal solution, implying there is room for improvement in the cold plate geometry, LN2 vapor exhaust design, and coolant delivery optimization.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"63502951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sebastien Sequeira, K. Bennion, J. Cousineau, S. Narumanchi, G. Moreno, Satish Kumar, Y. Joshi
One of the key challenges for the electric vehicle industry is to develop high-power-density electric motors. Achieving higher power density requires efficient heat removal from inside the motor. In order to improve thermal management, a multi-physics modeling framework that is able to accurately predict the behavior of the motor, while being computationally efficient, is essential. This paper first presents a detailed validation of a Lumped Parameter Thermal Network (LPTN) model of an Internal Permanent Magnet synchronous motor within the commercially available Motor-CAD® modeling environment. The validation is based on temperature comparison with experimental data and with more detailed Finite Element Analysis (FEA). All critical input parameters of the LPTN are considered in detail for each layer of the stator, especially the contact resistances between the impregnation, liner, laminations and housing. Finally, a sensitivity analysis for each of the critical input parameters is provided. A maximum difference of 4% - for the highest temperature in the slot-winding and the end-winding - was found between the LPTN and the experimental data. Comparing the results from the LPTN and the FEA model, the maximum difference was 2% for the highest temperature in the slot-winding and end-winding. As for the LTPN sensitivity analysis, the thermal parameter with the highest sensitivity was found to be the liner-to-lamination contact resistance.
{"title":"Validation and Parametric Investigations of an Internal Permanent Magnet Motor Using a Lumped Parameter Thermal Model","authors":"Sebastien Sequeira, K. Bennion, J. Cousineau, S. Narumanchi, G. Moreno, Satish Kumar, Y. Joshi","doi":"10.1115/1.4053121","DOIUrl":"https://doi.org/10.1115/1.4053121","url":null,"abstract":"\u0000 One of the key challenges for the electric vehicle industry is to develop high-power-density electric motors. Achieving higher power density requires efficient heat removal from inside the motor. In order to improve thermal management, a multi-physics modeling framework that is able to accurately predict the behavior of the motor, while being computationally efficient, is essential. This paper first presents a detailed validation of a Lumped Parameter Thermal Network (LPTN) model of an Internal Permanent Magnet synchronous motor within the commercially available Motor-CAD® modeling environment. The validation is based on temperature comparison with experimental data and with more detailed Finite Element Analysis (FEA). All critical input parameters of the LPTN are considered in detail for each layer of the stator, especially the contact resistances between the impregnation, liner, laminations and housing. Finally, a sensitivity analysis for each of the critical input parameters is provided. A maximum difference of 4% - for the highest temperature in the slot-winding and the end-winding - was found between the LPTN and the experimental data. Comparing the results from the LPTN and the FEA model, the maximum difference was 2% for the highest temperature in the slot-winding and end-winding. As for the LTPN sensitivity analysis, the thermal parameter with the highest sensitivity was found to be the liner-to-lamination contact resistance.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46907835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Qin, Shuai Zhao, Yanwei Dai, Lingyun Liu, Tong An, Pei Chen, Yanpeng Gong
Thermo-mechanical reliability assessment for sintered silver is a crucial issue as sintered silver is a promising candidate of die-attachment materials for power devices. In this paper, the nano-indentation tests are performed for sintered silver in typical die-attach interconnection under different thermal cycles. Based on thermal cycling test, the Young's modulus and hardness of sintered silver layer have been presented. It is found that the Young's modulus and hardness of sintered silver layer changes slightly although the microstructure of sintered silver also presents some variations. The stress and strain curves for different thermal cycling tests for sintered silver based on reverse analysis of nano-indentation are also given. The results show that the elastoplastic constitutive equations change significantly after thermal cycling tests, and the yielding stress decreases remarkably after 70 thermal cycles. The experimental investigation also show that the cracking behaviors of sintered silver depends on its geometry characteristics, which implies that the possible optimization of sintered silver layer could enhance its thermo-mechanical performance.
{"title":"Indentation Tests for Sintered Silver in Die-Attach Interconnection After Thermal Cycling","authors":"F. Qin, Shuai Zhao, Yanwei Dai, Lingyun Liu, Tong An, Pei Chen, Yanpeng Gong","doi":"10.1115/1.4053028","DOIUrl":"https://doi.org/10.1115/1.4053028","url":null,"abstract":"\u0000 Thermo-mechanical reliability assessment for sintered silver is a crucial issue as sintered silver is a promising candidate of die-attachment materials for power devices. In this paper, the nano-indentation tests are performed for sintered silver in typical die-attach interconnection under different thermal cycles. Based on thermal cycling test, the Young's modulus and hardness of sintered silver layer have been presented. It is found that the Young's modulus and hardness of sintered silver layer changes slightly although the microstructure of sintered silver also presents some variations. The stress and strain curves for different thermal cycling tests for sintered silver based on reverse analysis of nano-indentation are also given. The results show that the elastoplastic constitutive equations change significantly after thermal cycling tests, and the yielding stress decreases remarkably after 70 thermal cycles. The experimental investigation also show that the cracking behaviors of sintered silver depends on its geometry characteristics, which implies that the possible optimization of sintered silver layer could enhance its thermo-mechanical performance.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47977738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the heat transport mechanism in semiconductor elements within a homogeneous thermoelectric cooling system using the dual-phase-lag model. The thermal lagging behavior is analyzed and explored during the energy transport process. The coupled energy and constitutive partial differential equations are solved simultaneously to reduce the complexity of the high-order spatial and time derivatives. This approach simplifies the mathematical solution process and reduces numerical instabilities when compared to the conventional methodology in which either the temperature or heat flux are solved individually with a single equation. The effect of the thermal lagging behavior on energy transport is examined and compared to results by using the Cattaneo-Vernotte model. Furthermore, the phase-lag behavior on the temperature and heat flux profiles are investigated in detail. This study provides perceptive information for engineering applications in which microscale heat transport phenomenon plays a significant role during the design process. Adding the dual-phase-lag model to the traditional heat diffusion model will be a complementary option for engineers in the thermoelectric industry.
{"title":"Understanding Thermal Lagging Behaviors in Thermoelectric Elements with the Dual-Phase-Lag Model","authors":"W. Yeung, T. Lam","doi":"10.1115/1.4052948","DOIUrl":"https://doi.org/10.1115/1.4052948","url":null,"abstract":"\u0000 This study investigates the heat transport mechanism in semiconductor elements within a homogeneous thermoelectric cooling system using the dual-phase-lag model. The thermal lagging behavior is analyzed and explored during the energy transport process. The coupled energy and constitutive partial differential equations are solved simultaneously to reduce the complexity of the high-order spatial and time derivatives. This approach simplifies the mathematical solution process and reduces numerical instabilities when compared to the conventional methodology in which either the temperature or heat flux are solved individually with a single equation. The effect of the thermal lagging behavior on energy transport is examined and compared to results by using the Cattaneo-Vernotte model. Furthermore, the phase-lag behavior on the temperature and heat flux profiles are investigated in detail. This study provides perceptive information for engineering applications in which microscale heat transport phenomenon plays a significant role during the design process. Adding the dual-phase-lag model to the traditional heat diffusion model will be a complementary option for engineers in the thermoelectric industry.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48187950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent advances in the microelectronics industry have increased the demand for smaller and more compact package devices with higher performance. This paper presents an analytical multi-parametric design optimization approach for the miniaturization of flip-chip package, while considering the filling time of the subsequent underfill encapsulation process. The design optimization approach was based on the latest regional segregation-based analytical filling time model. Numerical simulation was conducted to verify the governed analytical model. The discrepancies in filling times are less than 9.9% and the predicted critical bump pitch has a low deviation of 4.1%, affirming that both the analytical and numerical models were in great consensus. The variation effects of bump pitch, gap height and contact angle on the filling time were analysed and discussed thoroughly. Both the critical bump pitch and the critical gap height were computed and fitted into respective empirical equations. Subsequently, a new multi-parametric design optimization approach based on the thresholding and criticality of underfill parameters was proposed to determine the optimum parameters that yield to the most compact flip-chip package with acceptable low filling time during the encapsulation process. Lastly, this proposed optimization technique was tested on the four flip-chips used in a previously published underfill experiment.
{"title":"Analytical Multi-Parametric Design Optimization for the Miniaturization of Flip-Chip Package","authors":"Fei Chong Ng, M. A. Abas","doi":"10.1115/1.4052920","DOIUrl":"https://doi.org/10.1115/1.4052920","url":null,"abstract":"\u0000 Recent advances in the microelectronics industry have increased the demand for smaller and more compact package devices with higher performance. This paper presents an analytical multi-parametric design optimization approach for the miniaturization of flip-chip package, while considering the filling time of the subsequent underfill encapsulation process. The design optimization approach was based on the latest regional segregation-based analytical filling time model. Numerical simulation was conducted to verify the governed analytical model. The discrepancies in filling times are less than 9.9% and the predicted critical bump pitch has a low deviation of 4.1%, affirming that both the analytical and numerical models were in great consensus. The variation effects of bump pitch, gap height and contact angle on the filling time were analysed and discussed thoroughly. Both the critical bump pitch and the critical gap height were computed and fitted into respective empirical equations. Subsequently, a new multi-parametric design optimization approach based on the thresholding and criticality of underfill parameters was proposed to determine the optimum parameters that yield to the most compact flip-chip package with acceptable low filling time during the encapsulation process. Lastly, this proposed optimization technique was tested on the four flip-chips used in a previously published underfill experiment.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2021-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47157942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Palash V. Acharya, Manojkumar Lokanathan, A. Ouroua, R. Hebner, S. Strank, V. Bahadur
Machine learning (ML)-based predictive techniques are used in conjunction with a game-theoretic approach to predict the thermal behavior of a power electronics package and study the relative influence of encapsulation material properties and thermal management in influencing hotspot temperatures. Parametric steady-state and transient thermal simulations are conducted for a commercially available 1.2 kV/444 A SiC half-bridge module. An extensive databank of 2592 (steady-state) and 1200 (transient) data points generated via numerical simulations is used to train and evaluate the performance of three ML algorithms (random forest, support vector machine and neural network) in modeling the thermal behavior. The parameter space includes the thermal conductivities of the encapsulant, baseplate, heat sink and cooling conditions deployed at the sink; the parametric space covers a variety of materials and cooling scenarios. Excellent prediction accuracies with R2 values > 99.5% are obtained for the algorithms. SHAP (Shapley Additive exPlanations) dependence plots are used to quantify the relative impact of device and heat sink parameters on junction temperatures. We observe that while heatsink cooling conditions significantly influence the steady-state junction temperature, their contribution in determining the junction temperature in dynamic mode is diminished. Using ML-SHAP models, we quantify the impact of emerging polymeric nanocomposites (with high conductivities and diffusivities) on hotspot temperature reduction, with the device operating in static and dynamic modes. Overall, this study highlights the attractiveness of ML-based approaches for thermal design, and provides a framework for setting targets for future encapsulation materials.
基于机器学习(ML)的预测技术结合博弈论方法来预测电力电子封装的热行为，并研究封装材料性能和热管理对热点温度的相对影响。对市售的1.2 kV/444 a SiC半桥模块进行了参数稳态和瞬态热模拟。通过数值模拟生成的2592(稳态)和1200(瞬态)数据点的广泛数据库用于训练和评估三种ML算法(随机森林，支持向量机和神经网络)在模拟热行为方面的性能。参数空间包括所述密封剂、底板、散热器的导热系数以及所述散热器处布置的冷却条件;参数化空间涵盖了多种材料和冷却场景。结果表明，该算法具有较好的预测精度，R2值为> ~ 99.5%。SHAP (Shapley Additive exPlanations)依赖性图用于量化器件和散热器参数对结温的相对影响。我们观察到，虽然散热器冷却条件显著影响稳态结温，但它们在确定动态模式结温方面的贡献减弱了。使用ML-SHAP模型，我们量化了新兴的聚合物纳米复合材料(具有高导电性和扩散性)对热点温度降低的影响，设备在静态和动态模式下运行。总的来说，这项研究突出了基于ml的热设计方法的吸引力，并为未来封装材料的目标设定提供了一个框架。
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