I. Kaur, S. Mujahid, YubRaj Paudel, H. Rhee, Prashant Singh
Single unit cell thick lattice frame materials have applications in efficient heat exchangers. The present study is focused on strut-based sandwich-type configurations obtained through reticulation of unit cell topologies of Tetrakaidecahedron, Octet, and Rhombic dodecahedron shapes at a porosity of 0.9 with water as the working fluid. Interfacial heat transfer coefficient values on struts and endwalls were determined by imposing constant temperature boundary condition. Averaged heat transfer coefficient on the endwall was the highest for Tetrakaidecahedron lattice whereas Rhombic dodecahedron lattice exhibited the highest average interfacial heat transfer coefficients on the struts. Flow analysis showed the presence of strong secondary flow features on planes normal to the mean flow direction that demonstrated the unique flow mixing capabilities of these lattices. Reported interfacial heat transfer coefficient at struts and endwall can be used in volume-averaged computations of metal foams (representative of lattices' flow and thermal properties) under local thermal non-equilibrium.
{"title":"Numerical Analysis of Flow and Heat Transfer Characteristics of Lattice-Based Compact Heat Sinks","authors":"I. Kaur, S. Mujahid, YubRaj Paudel, H. Rhee, Prashant Singh","doi":"10.1115/1.4056305","DOIUrl":"https://doi.org/10.1115/1.4056305","url":null,"abstract":"\u0000 Single unit cell thick lattice frame materials have applications in efficient heat exchangers. The present study is focused on strut-based sandwich-type configurations obtained through reticulation of unit cell topologies of Tetrakaidecahedron, Octet, and Rhombic dodecahedron shapes at a porosity of 0.9 with water as the working fluid. Interfacial heat transfer coefficient values on struts and endwalls were determined by imposing constant temperature boundary condition. Averaged heat transfer coefficient on the endwall was the highest for Tetrakaidecahedron lattice whereas Rhombic dodecahedron lattice exhibited the highest average interfacial heat transfer coefficients on the struts. Flow analysis showed the presence of strong secondary flow features on planes normal to the mean flow direction that demonstrated the unique flow mixing capabilities of these lattices. Reported interfacial heat transfer coefficient at struts and endwall can be used in volume-averaged computations of metal foams (representative of lattices' flow and thermal properties) under local thermal non-equilibrium.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43601529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Thekkut, R. Sivasubramony, A. Raj, Yuki Kawana, Jones Assiedu, K. Mirpuri, N. Shahane, P. Thompson, P. Borgesen
Sintered copper nano particles are being considered as alternatives to solder and/or sintered silver in different applications. Like for the alternatives, interpretation of accelerated fatigue test results does however require modeling, typically involving prediction of stresses and strains vs. time and temperature based on constitutive relations. This poses a challenge as the inelastic deformation properties depend strongly on both the initial particles and details of the processing, i.e. unlike for solder general constitutive relations are not possible. The present work provides a mechanistic description of the early transient creep of relevance in cycling, including effects of sintering parameters and subsequent oxidation. Inelastic deformation is dominated by diffusion, rather than dislocation motion. Generalized constitutive relations are provided to the extent that quantitative modeling of a specific structure only requires the measurement of a single creep curve for that.
{"title":"Effective Constitutive Relations for Sintered Nano Copper Joints","authors":"S. Thekkut, R. Sivasubramony, A. Raj, Yuki Kawana, Jones Assiedu, K. Mirpuri, N. Shahane, P. Thompson, P. Borgesen","doi":"10.1115/1.4056113","DOIUrl":"https://doi.org/10.1115/1.4056113","url":null,"abstract":"Sintered copper nano particles are being considered as alternatives to solder and/or sintered silver in different applications. Like for the alternatives, interpretation of accelerated fatigue test results does however require modeling, typically involving prediction of stresses and strains vs. time and temperature based on constitutive relations. This poses a challenge as the inelastic deformation properties depend strongly on both the initial particles and details of the processing, i.e. unlike for solder general constitutive relations are not possible. The present work provides a mechanistic description of the early transient creep of relevance in cycling, including effects of sintering parameters and subsequent oxidation. Inelastic deformation is dominated by diffusion, rather than dislocation motion. Generalized constitutive relations are provided to the extent that quantitative modeling of a specific structure only requires the measurement of a single creep curve for that.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47064971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Tompkins, A. Medina García, D. Huitink, H. Liao
In this study, TIM degradation is driven through HALT using temperature cycling with a prescribedvibrational acceleration for two commercially available materials having thermal conductivities of 6.0 and 8.5 W/m-K. HALT specimens were prepared by applying TIM through a 4-mil stencil over AlSiC baseplates in the shape of those used in Wolfspeed CAS325M12HM2 power electronics modules. Baseplates were mounted onto aluminum carrier blocks with embedded thermocouples to characterize the thermal resistance across the baseplate and TIM layer. Thermal dissipation into the top of the baseplates was provided by a custom heating block, which mimics the size and placement of the die junctions in CAS325 modules, applying power loads of 200, 300, and 400W. After initial characterization, samples were transferred to the HALT chamber with one set of samples exposed to temperature cycling only (TCO) and the other temperature cycling and vibration (TCV). Both sample sets were cycled between temperature extremes of -40 and 180 °C with vibrations applied at a peak acceleration of 3.21 Grms. After hundreds of cycles, samples were reevaluated to assess changes in thermal resistance to provide an accelerated measure of TIM degradation. This allows for reliability prediction of useful lifetime (illustrated in a solar inverter case study herein), as well as to provide a basis for developing an accelerated testing method to related temperature cycling to faster methods of degradation. Such techniques provide a means to develop maintenance schedules for power modules for ensuringsufficient thermal performance over the operating lifetime.
{"title":"Module-Level Thermal Interface Material Degradation in Halt","authors":"J. Tompkins, A. Medina García, D. Huitink, H. Liao","doi":"10.1115/1.4056030","DOIUrl":"https://doi.org/10.1115/1.4056030","url":null,"abstract":"\u0000 In this study, TIM degradation is driven through HALT using temperature cycling with a prescribedvibrational acceleration for two commercially available materials having thermal conductivities of 6.0 and 8.5 W/m-K. HALT specimens were prepared by applying TIM through a 4-mil stencil over AlSiC baseplates in the shape of those used in Wolfspeed CAS325M12HM2 power electronics modules. Baseplates were mounted onto aluminum carrier blocks with embedded thermocouples to characterize the thermal resistance across the baseplate and TIM layer. Thermal dissipation into the top of the baseplates was provided by a custom heating block, which mimics the size and placement of the die junctions in CAS325 modules, applying power loads of 200, 300, and 400W. After initial characterization, samples were transferred to the HALT chamber with one set of samples exposed to temperature cycling only (TCO) and the other temperature cycling and vibration (TCV). Both sample sets were cycled between temperature extremes of -40 and 180 °C with vibrations applied at a peak acceleration of 3.21 Grms. After hundreds of cycles, samples were reevaluated to assess changes in thermal resistance to provide an accelerated measure of TIM degradation. This allows for reliability prediction of useful lifetime (illustrated in a solar inverter case study herein), as well as to provide a basis for developing an accelerated testing method to related temperature cycling to faster methods of degradation. Such techniques provide a means to develop maintenance schedules for power modules for ensuringsufficient thermal performance over the operating lifetime.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47174207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Iradukunda, D. Huitink, Kevin Kayijuka, T. Gebrael, N. Miljkovic
Power densification and rising module heat losses cannot be managed by traditional "external-to-case" cooling solutions. This is especially pronounced in high voltage systems, where intervening layers of insulating material between the power devices and cooling solution need to be sufficiently thick to provide adequate voltage isolation. As operating voltages increase, the required thicknesses for these insulating layers become so large that they limit the ability to extract the heat. A direct cooling approach that addresses voltage separation issues represents a unique opportunity to deliver coolant to the hottest regions, while opening up the opportunity for increased scaling of power electronics modules. However technical concerns about long-term performance of coolants and their voltage isolation characteristics coupled with integration challenges impede adoption. Here, the reliability and performance of a dielectric fluid of the hydrofluoroether type, HFE7500, are examined to advance the feasibility of a direct cooling approach for improved thermal management of high-voltage, high-power module. The breakdown voltage of the dielectric fluid is characterized through relevant temperatures, flow rates, and electric fields with the ultimate goal of developing design rules for direct integrated cooling schemes.
{"title":"Hfe7500 Coolant Dielectric Strength Augmentation Under Convective Conditions","authors":"A. Iradukunda, D. Huitink, Kevin Kayijuka, T. Gebrael, N. Miljkovic","doi":"10.1115/1.4056031","DOIUrl":"https://doi.org/10.1115/1.4056031","url":null,"abstract":"\u0000 Power densification and rising module heat losses cannot be managed by traditional \"external-to-case\" cooling solutions. This is especially pronounced in high voltage systems, where intervening layers of insulating material between the power devices and cooling solution need to be sufficiently thick to provide adequate voltage isolation. As operating voltages increase, the required thicknesses for these insulating layers become so large that they limit the ability to extract the heat. A direct cooling approach that addresses voltage separation issues represents a unique opportunity to deliver coolant to the hottest regions, while opening up the opportunity for increased scaling of power electronics modules. However technical concerns about long-term performance of coolants and their voltage isolation characteristics coupled with integration challenges impede adoption. Here, the reliability and performance of a dielectric fluid of the hydrofluoroether type, HFE7500, are examined to advance the feasibility of a direct cooling approach for improved thermal management of high-voltage, high-power module. The breakdown voltage of the dielectric fluid is characterized through relevant temperatures, flow rates, and electric fields with the ultimate goal of developing design rules for direct integrated cooling schemes.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43613150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heat spreading from local, time-dependent heat sources in electronic packages results in the propagation of temperature non-uniformities through the stack of material layers attached to the chip. Available models either predict the chip temperatures only in the steady-state. We develop a transient resistance/capacitance network-based modeling approach capable of predicting the spatiotemporal temperature fields for this chip-on-stack geometry, accounting for in-plane heat spreading, through-plane heat conduction, and the effective convection resistance boundary conditions. The estimates from the present model are validated with direct comparison to a finite-volume numerical model for three-dimensional heat conduction. In the presence of a step heat input, the results demonstrate that the model accurately captures the transient temperature rise across the multi-substrate stack comprising layers with different anisotropic properties. For a case where the rectangular stack is exposed to a sinusoidally varying heat input the model is able to capture the general trends in the transient temperature fields in the plane where the heat source is applied to the multi-substrate stack. In summary, the developed resistance/capacitance network-based transient model offers a low-computational-cost method to predict the spatiotemporal temperature distribution over an arbitrary transient heat source interfacing a multi-layer stack of substrates.
{"title":"A Transient Resistance/Capacitance Network-Based Model for Heat Spreading in Substrate Stacks Having Multiple Anisotropic Layers","authors":"Soumya Bandyopadhyay, J. Weibel","doi":"10.1115/1.4055987","DOIUrl":"https://doi.org/10.1115/1.4055987","url":null,"abstract":"\u0000 Heat spreading from local, time-dependent heat sources in electronic packages results in the propagation of temperature non-uniformities through the stack of material layers attached to the chip. Available models either predict the chip temperatures only in the steady-state. We develop a transient resistance/capacitance network-based modeling approach capable of predicting the spatiotemporal temperature fields for this chip-on-stack geometry, accounting for in-plane heat spreading, through-plane heat conduction, and the effective convection resistance boundary conditions. The estimates from the present model are validated with direct comparison to a finite-volume numerical model for three-dimensional heat conduction. In the presence of a step heat input, the results demonstrate that the model accurately captures the transient temperature rise across the multi-substrate stack comprising layers with different anisotropic properties. For a case where the rectangular stack is exposed to a sinusoidally varying heat input the model is able to capture the general trends in the transient temperature fields in the plane where the heat source is applied to the multi-substrate stack. In summary, the developed resistance/capacitance network-based transient model offers a low-computational-cost method to predict the spatiotemporal temperature distribution over an arbitrary transient heat source interfacing a multi-layer stack of substrates.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42398111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Printed electronics is a fastest growing and emerging technology that have shown much potential in several industries including automotive, wearables, healthcare, and aerospace. Its applications can be found not only in flexible but also in large area electronics. Inkjet technology has gained much attention due to its low-cost, low material consumption, and capability for mass manufacturing. The preferred conductive metal of choice has been mostly silver due to its excellent electrical properties and ease in sintering. However, silver comes to be expensive than its counterpart copper. Since copper is prone to oxidation, much focus has been given towards photonic sintering that involves sudden burst of pulsed light at certain energy to sinter the copper Nanoparticles. With this technique, only the printed material gets sintered in a matter of seconds without having a great impact on its substrate. With all the knowledge, there is still a large gap in the process side with copper where it is important to look how the print process affects the electrical and mechanical properties of copper. With the process developed, the resistivity of printed copper was found to be 5 times the bulk copper. In regards to adhesion to the polyimide film, mechanical shear load to failure was found to be within 15-20 gF. To demonstrate the complete process, commercial-off-the-shelf components are also mounted on the additively printed pads. Statistically, control charting technique is implemented to understand any process variation over long duration of prints.
{"title":"Process Development for Printed Copper with Surface Mount Devices On Inkjet Metallization","authors":"P. Lall, Kartik Goyal, C. Hill","doi":"10.1115/1.4055986","DOIUrl":"https://doi.org/10.1115/1.4055986","url":null,"abstract":"\u0000 Printed electronics is a fastest growing and emerging technology that have shown much potential in several industries including automotive, wearables, healthcare, and aerospace. Its applications can be found not only in flexible but also in large area electronics. Inkjet technology has gained much attention due to its low-cost, low material consumption, and capability for mass manufacturing. The preferred conductive metal of choice has been mostly silver due to its excellent electrical properties and ease in sintering. However, silver comes to be expensive than its counterpart copper. Since copper is prone to oxidation, much focus has been given towards photonic sintering that involves sudden burst of pulsed light at certain energy to sinter the copper Nanoparticles. With this technique, only the printed material gets sintered in a matter of seconds without having a great impact on its substrate. With all the knowledge, there is still a large gap in the process side with copper where it is important to look how the print process affects the electrical and mechanical properties of copper. With the process developed, the resistivity of printed copper was found to be 5 times the bulk copper. In regards to adhesion to the polyimide film, mechanical shear load to failure was found to be within 15-20 gF. To demonstrate the complete process, commercial-off-the-shelf components are also mounted on the additively printed pads. Statistically, control charting technique is implemented to understand any process variation over long duration of prints.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43593198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Miniaturization as well as manufacturing processes that electronics devices are subjected to, often results to increase in operational parameters such as current density, temperature, mechanical load, with potential to induce stresses that may be detrimental to device reliability. Past studies have identified some failure mechanisms common to these devices. Examples of these failure mechanisms include fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. While some review activities related to reliability model development based on these failure mechanisms can be easily found in literature, to the best of our knowledge, a single review paper, which captures the reliability model progresses made over the past four decades across these failure mechanisms in comparison with Standards such as Joint Electron Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) is to the best of our knowledge lacking. To fill this gap, a detailed review of failure mechanism driven reliability models, with emphasis on physics of failure (PoF) for power electronics was carried out in this paper. Although, other failure mechanisms exist, our review is only limited to fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. It was found that, most reliability research modelling efforts are yet to be fully integrated into Standards.
{"title":"Failure Mechanisms Driven Reliability Models for Power Electronics: A Review","authors":"E. Okafor, D. Huitink","doi":"10.1115/1.4055774","DOIUrl":"https://doi.org/10.1115/1.4055774","url":null,"abstract":"\u0000 Miniaturization as well as manufacturing processes that electronics devices are subjected to, often results to increase in operational parameters such as current density, temperature, mechanical load, with potential to induce stresses that may be detrimental to device reliability. Past studies have identified some failure mechanisms common to these devices. Examples of these failure mechanisms include fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. While some review activities related to reliability model development based on these failure mechanisms can be easily found in literature, to the best of our knowledge, a single review paper, which captures the reliability model progresses made over the past four decades across these failure mechanisms in comparison with Standards such as Joint Electron Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) is to the best of our knowledge lacking. To fill this gap, a detailed review of failure mechanism driven reliability models, with emphasis on physics of failure (PoF) for power electronics was carried out in this paper. Although, other failure mechanisms exist, our review is only limited to fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. It was found that, most reliability research modelling efforts are yet to be fully integrated into Standards.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46223999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study introduces a modified dynamic multiphysics modeling framework to characterize the electromagnetic-electro-thermal (EET) coupled behavior of a power conversion system during a long load operation. The modeling framework extends the prior model with more comprehensive analysis and enhanced computational efficiency and modeling simplicity. This framework incorporates a fully integrated electromagnetic circuit (FIEC) model for extracting parasitics, including self and mutual inductances and also exploring their effect on the switching characteristics and power losses, and a dynamic power loss-temperature thermal (PTT) model for describing the temperature-dependent instantaneous electrical behavior and power loss. Moreover, a simple resistance-capacitance (RC) snubber circuit design is applied to prevent overvoltage and diminish voltage oscillations and spike value during the operation, and their power losses are also assessed and considered in the dynamic EET coupled modeling. Furthermore, the proposed PTT model employs an equivalent thermal RC network to calculate the chip junction temperature with a given power. Additionally, a simple power-temperature relationship derived from the FIEC co-simulation is applied for modeling simplicity and computational efficiency. This framework is tested on a three-phase inverter operating with a 180-degree conduction mode. The proposed FIEC co-simulation and CFD thermal models are validated by double pulse (DPT) and IR thermography experiments, respectively. Moreover, the PTT model is validated compared with the conventional dynamic coupled electro-thermal model. Finally, a design guideline for enhanced thermal performance of the tested power conversion system is sought through parametric analysis.
{"title":"Dynamic Modeling Framework for Evaluating Electromagnetic-Electro-Thermal Behavior of Power Conversion System During Load Operation","authors":"Hsien-Chie Cheng, Yan-Cheng Liu","doi":"10.1115/1.4055591","DOIUrl":"https://doi.org/10.1115/1.4055591","url":null,"abstract":"\u0000 This study introduces a modified dynamic multiphysics modeling framework to characterize the electromagnetic-electro-thermal (EET) coupled behavior of a power conversion system during a long load operation. The modeling framework extends the prior model with more comprehensive analysis and enhanced computational efficiency and modeling simplicity. This framework incorporates a fully integrated electromagnetic circuit (FIEC) model for extracting parasitics, including self and mutual inductances and also exploring their effect on the switching characteristics and power losses, and a dynamic power loss-temperature thermal (PTT) model for describing the temperature-dependent instantaneous electrical behavior and power loss. Moreover, a simple resistance-capacitance (RC) snubber circuit design is applied to prevent overvoltage and diminish voltage oscillations and spike value during the operation, and their power losses are also assessed and considered in the dynamic EET coupled modeling. Furthermore, the proposed PTT model employs an equivalent thermal RC network to calculate the chip junction temperature with a given power. Additionally, a simple power-temperature relationship derived from the FIEC co-simulation is applied for modeling simplicity and computational efficiency. This framework is tested on a three-phase inverter operating with a 180-degree conduction mode. The proposed FIEC co-simulation and CFD thermal models are validated by double pulse (DPT) and IR thermography experiments, respectively. Moreover, the PTT model is validated compared with the conventional dynamic coupled electro-thermal model. Finally, a design guideline for enhanced thermal performance of the tested power conversion system is sought through parametric analysis.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47015906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tiwei Wei, Sougata Hazra, Yujui Lin, M. Gupta, M. Degner, M. Asheghi, E. K. Goodson
Silicon-based embedded microchannel with 3D manifold micro-cooler offers lower pressure drop and increased heat removal capability (>1 kW/cm2) for microprocessors and power electronics cooling using single-phase water. In this paper, we present a thermal-fluidic numerical analysis of silicon-embedded micro-channel cooling. We develop a full-scale computational fluid dynamics (CFD) model of a large footprint (24 × 24 mm2) device having embedded microchannels and a 3D manifold. It is found that the pressure/velocity distributions at three different critical regions inside the inlet manifold have a significant impact on the temperature distribution. A previous study reported a shift of the chip temperature hot-spot at high flow rates, this study delves deep into the flow and pressure variations within the Manifold (MF) and Cold Plate (CP) that leads to this shift. This study also investigates the degree of flow maldistribution, first between the manifold channels caused by the plenum and then between the Cold Plate channels caused by the individual MF channels. Finally, this study concludes with a comparison between two different 3D manifold inlet channel heights. The comparison reveals that the manifold with 1.5 mm thickness can reduce the pressure drop by a factor of 4 while maintaining the same thermal resistance of 0.04 K.cm2/W, thus indicating an increase in the coefficient of performance (COP) by a factor of 4, compared with a manifold thickness of 0.7 mm.
{"title":"Numerical Study of Large Footprint (24 × 24mm2) Silicon-Based Embedded Microchannel 3D Manifold Coolers","authors":"Tiwei Wei, Sougata Hazra, Yujui Lin, M. Gupta, M. Degner, M. Asheghi, E. K. Goodson","doi":"10.1115/1.4055468","DOIUrl":"https://doi.org/10.1115/1.4055468","url":null,"abstract":"\u0000 Silicon-based embedded microchannel with 3D manifold micro-cooler offers lower pressure drop and increased heat removal capability (>1 kW/cm2) for microprocessors and power electronics cooling using single-phase water. In this paper, we present a thermal-fluidic numerical analysis of silicon-embedded micro-channel cooling. We develop a full-scale computational fluid dynamics (CFD) model of a large footprint (24 × 24 mm2) device having embedded microchannels and a 3D manifold. It is found that the pressure/velocity distributions at three different critical regions inside the inlet manifold have a significant impact on the temperature distribution. A previous study reported a shift of the chip temperature hot-spot at high flow rates, this study delves deep into the flow and pressure variations within the Manifold (MF) and Cold Plate (CP) that leads to this shift. This study also investigates the degree of flow maldistribution, first between the manifold channels caused by the plenum and then between the Cold Plate channels caused by the individual MF channels. Finally, this study concludes with a comparison between two different 3D manifold inlet channel heights. The comparison reveals that the manifold with 1.5 mm thickness can reduce the pressure drop by a factor of 4 while maintaining the same thermal resistance of 0.04 K.cm2/W, thus indicating an increase in the coefficient of performance (COP) by a factor of 4, compared with a manifold thickness of 0.7 mm.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46326591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Joshua Kasitz, Aniket Ajay Lad, M. J. Hoque, N. Miljkovic, D. Huitink
High power electronics are a key component in the electrification of aircraft. Large amounts of power need to be handled onboard to generate sufficient lift for flight. The transient nature of the aircraft's mission profile produces varied loading and environmental influences, making consistent cooling and device reliability difficult to maintain. Due to limitations in weight and performance metrics, the thermal management capability becomes a key inhibiting factor in preventing adoption of all electric aircraft. Many efforts are focused on the improvement of high-powered electronics such as the inverters, batteries, and motors, but there is a need for increased focus on the implications of each improved device on the total system with regards to thermal management. To address the many concerns for thermal management within aviation, this paper will review the prevalent factors of flight and couple them to their respective challenges to highlight the overarching effort needed to successfully integrate efficient electric propulsion devices with their protective thermal management systems. A review will be combined with a brief analytical study over inverter cooling to examine the effects of various transient parameters on the device temperature of an inverter in flight. The impact of failure in the cooling systems on the shutdown process will also be examined. Both studies are tied to the motivation for examining the impacts of new and transient challenges faced by electric power systems and help signify the importance of this focus as these systems become more present and capable within the aviation industry.
{"title":"Transient Nature of Flight and Its Impact on Thermal Management for All Electric Aircraft","authors":"Joshua Kasitz, Aniket Ajay Lad, M. J. Hoque, N. Miljkovic, D. Huitink","doi":"10.1115/1.4055464","DOIUrl":"https://doi.org/10.1115/1.4055464","url":null,"abstract":"\u0000 High power electronics are a key component in the electrification of aircraft. Large amounts of power need to be handled onboard to generate sufficient lift for flight. The transient nature of the aircraft's mission profile produces varied loading and environmental influences, making consistent cooling and device reliability difficult to maintain. Due to limitations in weight and performance metrics, the thermal management capability becomes a key inhibiting factor in preventing adoption of all electric aircraft. Many efforts are focused on the improvement of high-powered electronics such as the inverters, batteries, and motors, but there is a need for increased focus on the implications of each improved device on the total system with regards to thermal management. To address the many concerns for thermal management within aviation, this paper will review the prevalent factors of flight and couple them to their respective challenges to highlight the overarching effort needed to successfully integrate efficient electric propulsion devices with their protective thermal management systems. A review will be combined with a brief analytical study over inverter cooling to examine the effects of various transient parameters on the device temperature of an inverter in flight. The impact of failure in the cooling systems on the shutdown process will also be examined. Both studies are tied to the motivation for examining the impacts of new and transient challenges faced by electric power systems and help signify the importance of this focus as these systems become more present and capable within the aviation industry.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2022-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46649670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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