Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111231
L. Fuller
A computer-integrated-manufacturing (CIM) system which has been installed at the Rochester Institute of Technology to support a student-run integrated-circuit factory is described. The hardware and software selected are described. The capabilities of the system are discussed. The status of the project, long-term goals, and additional educational activities are outlined.<>
{"title":"Implementation of a CIM system for semiconductor manufacturing at Rochester Institute of Technology","authors":"L. Fuller","doi":"10.1109/ASMC.1990.111231","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111231","url":null,"abstract":"A computer-integrated-manufacturing (CIM) system which has been installed at the Rochester Institute of Technology to support a student-run integrated-circuit factory is described. The hardware and software selected are described. The capabilities of the system are discussed. The status of the project, long-term goals, and additional educational activities are outlined.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111215
P. Deosthali, A. Gardel
The authors describe how the use of simulation technology captures the dynamics and interdependencies of very-large-scale-integration (VLSI) fabrication. A case study of a photolithography cell demonstrates how simulation is used to perform capacity planning to optimize the production line. The emphasis is on identifying the bottleneck areas and evaluating proposed changes to minimize the time to market of proprietary chips.<>
{"title":"Using simulation in semiconductor fabrication","authors":"P. Deosthali, A. Gardel","doi":"10.1109/ASMC.1990.111215","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111215","url":null,"abstract":"The authors describe how the use of simulation technology captures the dynamics and interdependencies of very-large-scale-integration (VLSI) fabrication. A case study of a photolithography cell demonstrates how simulation is used to perform capacity planning to optimize the production line. The emphasis is on identifying the bottleneck areas and evaluating proposed changes to minimize the time to market of proprietary chips.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116485847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111212
M. Levitt, J. Abraham
A method is presented that allows job shops, such as wafer fabrication lines (fabs), to be analyzed for the application of just-in-time (JIT) production methods. From the resources available and the process recipe, a Kanban policy is derived that allows a pull-type production system to be implemented. Using this method example fabs were analyzed and the JIT/Kanban policies derived were simulated. The simulations show that the proposed method performs very well compared to other fab scheduling policies.<>
{"title":"Just-in-time methods for semiconductor manufacturing","authors":"M. Levitt, J. Abraham","doi":"10.1109/ASMC.1990.111212","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111212","url":null,"abstract":"A method is presented that allows job shops, such as wafer fabrication lines (fabs), to be analyzed for the application of just-in-time (JIT) production methods. From the resources available and the process recipe, a Kanban policy is derived that allows a pull-type production system to be implemented. Using this method example fabs were analyzed and the JIT/Kanban policies derived were simulated. The simulations show that the proposed method performs very well compared to other fab scheduling policies.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123590280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111218
C.M. Weatherwax, C. Tsareff
The development and construction of the expert system, the acquisition and representation of knowledge, and an implementation of the system are discussed. In this implementation, systems covering the photolithography and ion implantation areas were used for full-time production use by manufacturing personnel. Implementation and acceptance issues are addressed. Operators can use the expert systems to solve many routine processing problems that were once the exclusive domain of sustaining engineers. Improvements in the areas of productivity, quality, and downtime were demonstrated.<>
{"title":"Diagnostic expert system application to problem solving in a semiconductor manufacturing facility","authors":"C.M. Weatherwax, C. Tsareff","doi":"10.1109/ASMC.1990.111218","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111218","url":null,"abstract":"The development and construction of the expert system, the acquisition and representation of knowledge, and an implementation of the system are discussed. In this implementation, systems covering the photolithography and ion implantation areas were used for full-time production use by manufacturing personnel. Implementation and acceptance issues are addressed. Operators can use the expert systems to solve many routine processing problems that were once the exclusive domain of sustaining engineers. Improvements in the areas of productivity, quality, and downtime were demonstrated.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123000281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111223
J. R. Burke
Some of the objectives of the Semiconductor Research Corporation (SRC), which is a consortium whose full members include most of the major integrated circuit and equipment producing companies in the United States, are discussed. The SRC research program is discussed. The long range objectives of producing a prototype DRAM with a density of 256 Mb and a prototype 1-Gb DRAM chip are discussed. Other goals and economics are discussed.<>
{"title":"The gigabit chip: required manufacturing approaches","authors":"J. R. Burke","doi":"10.1109/ASMC.1990.111223","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111223","url":null,"abstract":"Some of the objectives of the Semiconductor Research Corporation (SRC), which is a consortium whose full members include most of the major integrated circuit and equipment producing companies in the United States, are discussed. The SRC research program is discussed. The long range objectives of producing a prototype DRAM with a density of 256 Mb and a prototype 1-Gb DRAM chip are discussed. Other goals and economics are discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114199741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111216
S. Lou, H. Yan, S. Sethi, A. Gardel, P. Deosthali
A flow-rate control policy to manage the production of a wafer fabrication facility is described. The policy is derived by formulating and solving a stochastic control problem. The results are then used to develop two sets of production control rules. The first one adjusts the lot release by determining when and how many new lots should be started. The second one controls the reentrant process in the photolithography area, commonly known as the hub. The control rules are robust against random disturbances because they provide a feedback control based on the information of the entire shop floor.<>
{"title":"Hub-centered production control of wafer fabrication","authors":"S. Lou, H. Yan, S. Sethi, A. Gardel, P. Deosthali","doi":"10.1109/ASMC.1990.111216","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111216","url":null,"abstract":"A flow-rate control policy to manage the production of a wafer fabrication facility is described. The policy is derived by formulating and solving a stochastic control problem. The results are then used to develop two sets of production control rules. The first one adjusts the lot release by determining when and how many new lots should be started. The second one controls the reentrant process in the photolithography area, commonly known as the hub. The control rules are robust against random disturbances because they provide a feedback control based on the information of the entire shop floor.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133916067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111219
W.R. McMahon
An assessment of the reasons for Japanese ascendancy in semiconductor manufacturing is presented. A discussion of effective American countermeasures in general is given. In particular, certain Sematech responses are included.<>
{"title":"Partnering to restore US competitiveness in semiconductor manufacturing","authors":"W.R. McMahon","doi":"10.1109/ASMC.1990.111219","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111219","url":null,"abstract":"An assessment of the reasons for Japanese ascendancy in semiconductor manufacturing is presented. A discussion of effective American countermeasures in general is given. In particular, certain Sematech responses are included.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130131950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111221
B. Smoak, D. O'Ferrell, D. Brestovansky, S. Cheung
The characterization of an Applied Materials 7600 silicon epi reactor using a reactor analysis system is described. By analyzing gaseous impurities such as oxygen, moisture (H/sub 2/O), and particulates, contaminations introduced by machine design and operation are shown to far outweigh the impurities contained in the inlet materials. The actual testing and analysis involves production epi systems at the materials wafer fab at Harris Semiconductor in Palm Bay, Florida. A case study is presented which shows how, through systematic use of the Linde reactor analysis, contamination levels can be reduced by varying operating parameters such as load time, temperature and housing purge flow rate. Epitaxial film defects and process yield are significantly improved.<>
{"title":"Yield improvement in silicon epitaxy through gas purity analysis and control at the wafer","authors":"B. Smoak, D. O'Ferrell, D. Brestovansky, S. Cheung","doi":"10.1109/ASMC.1990.111221","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111221","url":null,"abstract":"The characterization of an Applied Materials 7600 silicon epi reactor using a reactor analysis system is described. By analyzing gaseous impurities such as oxygen, moisture (H/sub 2/O), and particulates, contaminations introduced by machine design and operation are shown to far outweigh the impurities contained in the inlet materials. The actual testing and analysis involves production epi systems at the materials wafer fab at Harris Semiconductor in Palm Bay, Florida. A case study is presented which shows how, through systematic use of the Linde reactor analysis, contamination levels can be reduced by varying operating parameters such as load time, temperature and housing purge flow rate. Epitaxial film defects and process yield are significantly improved.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131161527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111213
M. Joshi
The design and successful implementation of just-in-time (JIT) technology for running two semiconductor wafer fabrication facilities (fabs) that substantially reduced cycle times, improved yields, and saved over 5 million dollars are outlined. This was achieved in a relatively short time (about 6 months per fab). JIT methodology improved worker morale, predictability of schedules, and flexibility of product mix. An overview of JIT operations and definitions of key JIT terms are given.<>
{"title":"Making wafers in the JIT style","authors":"M. Joshi","doi":"10.1109/ASMC.1990.111213","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111213","url":null,"abstract":"The design and successful implementation of just-in-time (JIT) technology for running two semiconductor wafer fabrication facilities (fabs) that substantially reduced cycle times, improved yields, and saved over 5 million dollars are outlined. This was achieved in a relatively short time (about 6 months per fab). JIT methodology improved worker morale, predictability of schedules, and flexibility of product mix. An overview of JIT operations and definitions of key JIT terms are given.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126215584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111238
C. Bobbitt.
A statistical method that allows for simplicity of design and complements other statistical methods called multi-vari analysis (MVA) is described. MVA can be applied to virtually any manufacturing process. The results produced from this type of study give the engineer a good understanding of the manufacturing process. With this technique, engineers can determine manufacturing process capability and decide what steps need to be taken for further process control or improvement. The steps in performing a MVA process characterization study are given. MVA graphing and graph analysis and other uses for MVA data are discussed.<>
{"title":"Understanding manufacturing process variation with multi-vari analysis","authors":"C. Bobbitt.","doi":"10.1109/ASMC.1990.111238","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111238","url":null,"abstract":"A statistical method that allows for simplicity of design and complements other statistical methods called multi-vari analysis (MVA) is described. MVA can be applied to virtually any manufacturing process. The results produced from this type of study give the engineer a good understanding of the manufacturing process. With this technique, engineers can determine manufacturing process capability and decide what steps need to be taken for further process control or improvement. The steps in performing a MVA process characterization study are given. MVA graphing and graph analysis and other uses for MVA data are discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125848372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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