Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111232
J. Kristoff
Summary form only given. IBM's Advanced Semiconductor Technology Center (ASTC), which provides a model of a development fabricator for future generations of semiconductor technology, is discussed. The ASTC assures development with a manufacturing environment. Facilities, equipment, and materials have been designed to meet future technology manufacturability. Some technology trends are given.<>
{"title":"The Advanced Semiconductor Technology Center: a technology engine for the future","authors":"J. Kristoff","doi":"10.1109/ASMC.1990.111232","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111232","url":null,"abstract":"Summary form only given. IBM's Advanced Semiconductor Technology Center (ASTC), which provides a model of a development fabricator for future generations of semiconductor technology, is discussed. The ASTC assures development with a manufacturing environment. Facilities, equipment, and materials have been designed to meet future technology manufacturability. Some technology trends are given.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"57 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133719303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111233
T. Kielty, J. Delahunty
A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed.<>
{"title":"Automated Pareto analysis for continuously improving a VLSI fabrication area's process stability","authors":"T. Kielty, J. Delahunty","doi":"10.1109/ASMC.1990.111233","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111233","url":null,"abstract":"A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131018041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111207
G. Depinto, J. Wilson
A low-pressure chemical-vapor-deposition (LPCVD) nitride process that was characterized for film uniformity and particle density is described. The appropriate factors and levels for an optimization experiment were established. A full factorial experiment and a Taguchi orthogonal array were selected. A confirmation run was processed to verify the optimum factor level settings from two design methodologies. SPC methods, (as measured by C/sub p/) were used to measure an overall process improvement for film uniformity. Particle trends for the implemented process are compared to particle trends on a previously used process.<>
{"title":"Optimization of LPCVD silicon nitride deposition process by use of designed experiments","authors":"G. Depinto, J. Wilson","doi":"10.1109/ASMC.1990.111207","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111207","url":null,"abstract":"A low-pressure chemical-vapor-deposition (LPCVD) nitride process that was characterized for film uniformity and particle density is described. The appropriate factors and levels for an optimization experiment were established. A full factorial experiment and a Taguchi orthogonal array were selected. A confirmation run was processed to verify the optimum factor level settings from two design methodologies. SPC methods, (as measured by C/sub p/) were used to measure an overall process improvement for film uniformity. Particle trends for the implemented process are compared to particle trends on a previously used process.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126662952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111222
C. Schuckert, D. Murray, C. Roberts, G. Cheek, T. Goida
A photoimagable polyimide layer which has been evaluated as a stress relief buffer for use with integrated circuits (ICs) packaged in plastic is discussed. The wafer-level overcoat process is manufacturable using available spin coat and develop tracks and is compared to conventional post wirebond die overcoating. Some properties of the polyimide layer, the manufacturing process, and the results achieved on actual commercial products are reviewed.<>
{"title":"Polyimide stress buffers in IC technology","authors":"C. Schuckert, D. Murray, C. Roberts, G. Cheek, T. Goida","doi":"10.1109/ASMC.1990.111222","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111222","url":null,"abstract":"A photoimagable polyimide layer which has been evaluated as a stress relief buffer for use with integrated circuits (ICs) packaged in plastic is discussed. The wafer-level overcoat process is manufacturable using available spin coat and develop tracks and is compared to conventional post wirebond die overcoating. Some properties of the polyimide layer, the manufacturing process, and the results achieved on actual commercial products are reviewed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"13 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114018741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111211
D. Hodges
Very-large-scale integration (VLSI) manufacturing techniques in Japan are compared with those in the United States. Factory design, employment practices, random vs. causal yield fluctuations, process control and productivity, and computer integrated manufacturing (CIM) systems are discussed.<>
{"title":"VLSI manufacturing in Japan and the United States","authors":"D. Hodges","doi":"10.1109/ASMC.1990.111211","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111211","url":null,"abstract":"Very-large-scale integration (VLSI) manufacturing techniques in Japan are compared with those in the United States. Factory design, employment practices, random vs. causal yield fluctuations, process control and productivity, and computer integrated manufacturing (CIM) systems are discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121636342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111229
R. Trahan, K. Dean
A software-based solution for integrated-circuit (IC) yield analysis is presented. A methodology for the incorporation of process test insert, product test, and product yield data from various sources is given. This information is then formatted into a common database, specifically RS1, where both RS1 and company-generated software procedures can perform statistical yield analysis on chosen data. System features highlighted include automatic operation, modular architecture for expansion, SPC, and yield reporting capabilities. Several examples of product yield enhancements utilizing test structure data and system procedures are presented.<>
{"title":"A comprehensive IC yield analysis system in RS1","authors":"R. Trahan, K. Dean","doi":"10.1109/ASMC.1990.111229","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111229","url":null,"abstract":"A software-based solution for integrated-circuit (IC) yield analysis is presented. A methodology for the incorporation of process test insert, product test, and product yield data from various sources is given. This information is then formatted into a common database, specifically RS1, where both RS1 and company-generated software procedures can perform statistical yield analysis on chosen data. System features highlighted include automatic operation, modular architecture for expansion, SPC, and yield reporting capabilities. Several examples of product yield enhancements utilizing test structure data and system procedures are presented.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122990712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111226
P. Fang
A methodology used to implement yield modeling in a custom integrated-circuit manufacturing facility is described. The sources for the inputs to the models are described. The component approach to yield modeling is explained, where component defect density (D/sub 0/) information is used to build an overall yield prediction. A reverse model using a single D/sub 0/ number is detailed. Verifications and selection criteria are given for model selection.<>
{"title":"Yield modeling in a custom IC manufacturing line","authors":"P. Fang","doi":"10.1109/ASMC.1990.111226","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111226","url":null,"abstract":"A methodology used to implement yield modeling in a custom integrated-circuit manufacturing facility is described. The sources for the inputs to the models are described. The component approach to yield modeling is explained, where component defect density (D/sub 0/) information is used to build an overall yield prediction. A reverse model using a single D/sub 0/ number is detailed. Verifications and selection criteria are given for model selection.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123653795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111208
G. Angel, N. Meyyappan, F. Sinclair, W. Tu
Data on beam potential measurements and gate oxide yield studies a high current implanter are presented. The beam potential measurements were made using a test structure on a silicon wafer with a time resolved in situ data gathering system in the mechanically scanned implanter. The yield studies used specially designed test devices with oxide breakdown measurements before and after a high dose implant. Data for different conditions in the implanter show that the voltage of the beam is forced on the surface exposed to the ion beam. This voltage can be effectively controlled by the use of electron injection from an electron shower as currently practiced. Preliminary results from the yield studies show very good yields over a wide range of conditions. Analysis of the results in terms of a theoretical model suggests that charge induced breakdown of very thin gate oxides in ion implantation will not become an insuperable obstacle in the foreseeable future.<>
{"title":"Charging measurement and control in high current implanters","authors":"G. Angel, N. Meyyappan, F. Sinclair, W. Tu","doi":"10.1109/ASMC.1990.111208","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111208","url":null,"abstract":"Data on beam potential measurements and gate oxide yield studies a high current implanter are presented. The beam potential measurements were made using a test structure on a silicon wafer with a time resolved in situ data gathering system in the mechanically scanned implanter. The yield studies used specially designed test devices with oxide breakdown measurements before and after a high dose implant. Data for different conditions in the implanter show that the voltage of the beam is forced on the surface exposed to the ion beam. This voltage can be effectively controlled by the use of electron injection from an electron shower as currently practiced. Preliminary results from the yield studies show very good yields over a wide range of conditions. Analysis of the results in terms of a theoretical model suggests that charge induced breakdown of very thin gate oxides in ion implantation will not become an insuperable obstacle in the foreseeable future.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115864334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111220
B.W. Smith, K. Hirschman
The impact of submicron mask defect printability for semiconductor processing is investigated. Computer simulations of image intensities resulting from programmed defects are compared to recorded images produced from defects of known size and proximity. Defects ranging in sizes from 0.6 to 2.0 mu m, located from 0 to 5 mu m from features imaged in various resist materials over silicon, silicon dioxide, silicon nitride, polysilicon, and aluminum show varying degrees of printability. Results analyzed through scanning electron microscopy are compared to theoretical results through two-dimensional modeling.<>
{"title":"Impact of process characteristics on submicron defect effects","authors":"B.W. Smith, K. Hirschman","doi":"10.1109/ASMC.1990.111220","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111220","url":null,"abstract":"The impact of submicron mask defect printability for semiconductor processing is investigated. Computer simulations of image intensities resulting from programmed defects are compared to recorded images produced from defects of known size and proximity. Defects ranging in sizes from 0.6 to 2.0 mu m, located from 0 to 5 mu m from features imaged in various resist materials over silicon, silicon dioxide, silicon nitride, polysilicon, and aluminum show varying degrees of printability. Results analyzed through scanning electron microscopy are compared to theoretical results through two-dimensional modeling.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127122424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111236
E. Sachs, Á. Ingólfsson, S. Ha
An approach to process control called generalized SPC which allows for the diagnosis of a process while the process is being tuned is discussed. A control module, the run by run controller, that implements a form of adaptive control based on the sequential design of experiments is discussed. Statistical process control is compared to the run by run controller.<>
{"title":"Tuning a process while performing SPC: an approach based on the sequential design of experiments","authors":"E. Sachs, Á. Ingólfsson, S. Ha","doi":"10.1109/ASMC.1990.111236","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111236","url":null,"abstract":"An approach to process control called generalized SPC which allows for the diagnosis of a process while the process is being tuned is discussed. A control module, the run by run controller, that implements a form of adaptive control based on the sequential design of experiments is discussed. Statistical process control is compared to the run by run controller.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124728489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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