Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309896
I. A. Ferzli, F. Najm
Statistical Vt variations lead to large variations of leakage current, which cause statistical voltage drops on the power grid that can affect Circuit timing. We propose a statistical analysis technique whereby variances of the leakage currents are used to estimate the susceptibility to timing violations due to leakage-induced voltage drops.
{"title":"Statistical estimation of circuit timing vulnerability due to leakage-induced power grid voltage drop","authors":"I. A. Ferzli, F. Najm","doi":"10.1109/ICICDT.2004.1309896","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309896","url":null,"abstract":"Statistical Vt variations lead to large variations of leakage current, which cause statistical voltage drops on the power grid that can affect Circuit timing. We propose a statistical analysis technique whereby variances of the leakage currents are used to estimate the susceptibility to timing violations due to leakage-induced voltage drops.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116253479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309956
G. Oleszek, D. Enicks
This paper presents the results of studies on oxygen concentration levels in in-situ boron doped sub-50 nm SiGe and SiGeC base strained layer NPN HBTs. The layers were characterized using four-point probe, secondary ion mass spectrometry and X-ray diffraction. The effect of oxygen concentration levels on boron sheet resistance, minority carrier lifetime, and device performance were investigated. It was found that oxygen can incorporate in SiGe by an order of magnitude over silicon. It is also determined that elevated oxygen can reduce the substitutional electrically active boron concentration and/or degrade the mobility, resulting in reduced sheet resistance. Similarly for elevated-oxygen concentration levels greater than 3/spl times/10/sup 18/ at/cc, device performance was found to be degraded.
{"title":"Impact of elevated oxygen concentration on in-situ doped sub-50 nm SiGe and SiGeC base strained layer NPN HBT","authors":"G. Oleszek, D. Enicks","doi":"10.1109/ICICDT.2004.1309956","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309956","url":null,"abstract":"This paper presents the results of studies on oxygen concentration levels in in-situ boron doped sub-50 nm SiGe and SiGeC base strained layer NPN HBTs. The layers were characterized using four-point probe, secondary ion mass spectrometry and X-ray diffraction. The effect of oxygen concentration levels on boron sheet resistance, minority carrier lifetime, and device performance were investigated. It was found that oxygen can incorporate in SiGe by an order of magnitude over silicon. It is also determined that elevated oxygen can reduce the substitutional electrically active boron concentration and/or degrade the mobility, resulting in reduced sheet resistance. Similarly for elevated-oxygen concentration levels greater than 3/spl times/10/sup 18/ at/cc, device performance was found to be degraded.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132609724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309974
J. Leray, J. Baggio, V. Ferlet-Cavrois, O. Flament
Since the 80s it is known that Terrestrial Cosmic Rays, mainly reported as Atmospheric Neutrons, can penetrate the natural shielding of buildings, equipments and circuit package and induce Soft Errors in integrated circuits and Breakdown of power devices. The high-energy neutron fluxes of interest range between 10 particles/cm/sup 2//hour at sea level and 10/sup 4/ particles/cm/sup 2//hour at typical airplanes flight altitude of 30000 feet, with modulation due to Solar Flares. In the 90s the phenomenon has pervaded as a consequence of the roadmap of electronic devices, especially downscaling of design rules, increase of signal bandwidth and increase of the size of DRAM and SRAM memory, standalone or embedded on processors and System-on-Chips. Failure-In-Time and Soft Error Rate became unacceptable. Test Standards and design solutions have been proposed to maintain reliability of commercial products and improve those used in special such as avionic computers. The paper describes the Atmospheric Neutron flux, the effects in the main classes of devices and specific cases such as neutron-induced single event upset observed in CMOS vs. CMOS/SOI and some mitigation issues. A model called CCPM (Critical Cross-Point Model) is proposed to provide critical graphs of technology node sensitivity along the scaling trend of CMOS.
{"title":"Atmospheric neutron effects in advanced microelectronics, standards and applications","authors":"J. Leray, J. Baggio, V. Ferlet-Cavrois, O. Flament","doi":"10.1109/ICICDT.2004.1309974","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309974","url":null,"abstract":"Since the 80s it is known that Terrestrial Cosmic Rays, mainly reported as Atmospheric Neutrons, can penetrate the natural shielding of buildings, equipments and circuit package and induce Soft Errors in integrated circuits and Breakdown of power devices. The high-energy neutron fluxes of interest range between 10 particles/cm/sup 2//hour at sea level and 10/sup 4/ particles/cm/sup 2//hour at typical airplanes flight altitude of 30000 feet, with modulation due to Solar Flares. In the 90s the phenomenon has pervaded as a consequence of the roadmap of electronic devices, especially downscaling of design rules, increase of signal bandwidth and increase of the size of DRAM and SRAM memory, standalone or embedded on processors and System-on-Chips. Failure-In-Time and Soft Error Rate became unacceptable. Test Standards and design solutions have been proposed to maintain reliability of commercial products and improve those used in special such as avionic computers. The paper describes the Atmospheric Neutron flux, the effects in the main classes of devices and specific cases such as neutron-induced single event upset observed in CMOS vs. CMOS/SOI and some mitigation issues. A model called CCPM (Critical Cross-Point Model) is proposed to provide critical graphs of technology node sensitivity along the scaling trend of CMOS.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"85 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113998907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332591
J. Clabes, J. Friedrich, M. Sweet, Jack DiLullo, S. Chu, D. Plass, James Dawson, P. Muench, Larry Powell, Michael Floyd, B. Sinharoy, Mike Lee, Michael Goulet, J. Wagoner, N. Schwartz, S. Runyon, Gary Gorman, Phillip Restle, R. Kalla, J. McGill, S. Dodson
POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5's dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip's frequency, area, power, and thermal targets.
{"title":"Design and implementation of the POWER5/spl trade/ microprocessor","authors":"J. Clabes, J. Friedrich, M. Sweet, Jack DiLullo, S. Chu, D. Plass, James Dawson, P. Muench, Larry Powell, Michael Floyd, B. Sinharoy, Mike Lee, Michael Goulet, J. Wagoner, N. Schwartz, S. Runyon, Gary Gorman, Phillip Restle, R. Kalla, J. McGill, S. Dodson","doi":"10.1109/ISSCC.2004.1332591","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332591","url":null,"abstract":"POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5's dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip's frequency, area, power, and thermal targets.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-17DOI: 10.1109/ICICDT.2004.1309928
I. Aller, J. Clabes
This paper first gives an overview of double-gate structures in general. briefly covers the FinFET technology.. and then describes how the unique characteristics of this fully depleted MOSFET device impact integrated circuit design.
{"title":"The double-gate FinFET: device and impact on IC design automation","authors":"I. Aller, J. Clabes","doi":"10.1109/ICICDT.2004.1309928","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309928","url":null,"abstract":"This paper first gives an overview of double-gate structures in general. briefly covers the FinFET technology.. and then describes how the unique characteristics of this fully depleted MOSFET device impact integrated circuit design.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126953783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICICDT.2004.1309892
P. Aum
{"title":"Leakage-induced signal degradation in VLSI interconnection for buffered bus line & logic","authors":"P. Aum","doi":"10.1109/ICICDT.2004.1309892","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309892","url":null,"abstract":"","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131814325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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