Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309899
M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani
A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.
{"title":"A 0.18 /spl mu/m 4 Mbit toggling MRAM","authors":"M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani","doi":"10.1109/ICICDT.2004.1309899","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309899","url":null,"abstract":"A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309955
C. O. Chui, K. Saraswat
Various advanced germanium (Ge) metal-oxide-semiconductor field-effect transistor (MOSFET) technologies with high-permittivity (high-/spl kappa/) gate dielectrics and shallow junctions have been demonstrated. Numerous novel Ge technologies on surface cleaning, gate dielectric, and dopant incorporation are presented In addition, we disclose an innovative self-aligned gate-last fabrication process not only to demonstrate functional Ge MOSFETs, but also to provide a vehicle to characterize many novel material integration schemes.
{"title":"Advanced germanium MOSFET technologies with high-/spl kappa/ gate dielectrics and shallow junctions","authors":"C. O. Chui, K. Saraswat","doi":"10.1109/ICICDT.2004.1309955","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309955","url":null,"abstract":"Various advanced germanium (Ge) metal-oxide-semiconductor field-effect transistor (MOSFET) technologies with high-permittivity (high-/spl kappa/) gate dielectrics and shallow junctions have been demonstrated. Numerous novel Ge technologies on surface cleaning, gate dielectric, and dopant incorporation are presented In addition, we disclose an innovative self-aligned gate-last fabrication process not only to demonstrate functional Ge MOSFETs, but also to provide a vehicle to characterize many novel material integration schemes.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309917
T. Dao
Power consumption including leakage current is becoming one of the most important limiting factors in VLSI, especially in the sub-65nm technologies. While technologies are facing multiple challenges in scaling, there have been successful developments on reduction of power consumption and leakage current in circuit and system design techniques based on the cooperation between two traditionally separated technical fields - technology and design. The benefits of separate gate access capability of DG-FDSOI technology on supporting these kinds of cooperation techniques have been addressed together with the impact on circuit designs which take advantages of this technology.
{"title":"Advanced double-gate fully-depleted silicon-on-insulator (DG-FDSOI) device and device impact on circuit design & power management","authors":"T. Dao","doi":"10.1109/ICICDT.2004.1309917","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309917","url":null,"abstract":"Power consumption including leakage current is becoming one of the most important limiting factors in VLSI, especially in the sub-65nm technologies. While technologies are facing multiple challenges in scaling, there have been successful developments on reduction of power consumption and leakage current in circuit and system design techniques based on the cooperation between two traditionally separated technical fields - technology and design. The benefits of separate gate access capability of DG-FDSOI technology on supporting these kinds of cooperation techniques have been addressed together with the impact on circuit designs which take advantages of this technology.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124715193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309937
S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan
Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to "Fast Silicon Technology"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.
{"title":"Fast/sub 14/ Technology: design technology for the automation of multi-gigahertz digital logic","authors":"S. Horne, D. Glowka, S. McMahon, P. Nixon, M. Seningen, G. Vijayan","doi":"10.1109/ICICDT.2004.1309937","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309937","url":null,"abstract":"Fast/sub 14/ Technology automates the implementation of multi-GHz digital logic circuits in standard CMOS fabrication processes. Fast/sub 14/ Technology derives its name from the atomic number of silicon (which translates to \"Fast Silicon Technology\"). Fast/sub 14/ Technology is comprised of five critical design elements: Multiphase Overlapped Clocking; 1-of-N Dynamic Logic (NDO family); Expert Routing Technology/sup TM/; Unified Design Database; Design Methodology and Electronic Design Automation (EDA) Tools Suite. Fast/sub 14/ Technology enables a significant improvement in chip design productivity for high-speed digital logic. Fast/sub 14/ Technology also provides significant power and silicon area efficiency benefits over other design methodologies in the high-performance logic design space. These benefits enable embedded processors and special-purpose digital logic products to achieve the levels of performance previously achieved only through custom design flows while maintaining efficient levels of power. These high performance levels are achieved at greatly reduced development costs and with lower risk of circuit problems as compared to the custom design flows used for desktop processors.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309933
T. Takayanagi, J. L. Shin, J. Su, A. Leon
A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.
{"title":"Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation","authors":"T. Takayanagi, J. L. Shin, J. Su, A. Leon","doi":"10.1109/ICICDT.2004.1309933","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309933","url":null,"abstract":"A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"19 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121019102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309919
C. Mazure, G. Celler, C. Maleville, I. Cayrefourcq
300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut/spl trade/ technology allow forming two types of strained Si - strained Si on SiGe on insulator, known as SGOI, and strained Si directly on insulator, known as sSOI. Fabrication methods and wafer characteristics for SOI, SGOI, and sSOI are discussed here.
{"title":"Advanced SOI substrate manufacturing","authors":"C. Mazure, G. Celler, C. Maleville, I. Cayrefourcq","doi":"10.1109/ICICDT.2004.1309919","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309919","url":null,"abstract":"300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut/spl trade/ technology allow forming two types of strained Si - strained Si on SiGe on insulator, known as SGOI, and strained Si directly on insulator, known as sSOI. Fabrication methods and wafer characteristics for SOI, SGOI, and sSOI are discussed here.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"464 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134037835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309979
K. Cheung
Advanced gate dielectrics for MOSFET, be it ultra thin SiO/sub 2/ or high-k materials are destined for deep submicron technology that is moving increasingly toward 1 voltage or below operating voltage. In this paper, we show that the well-established method of reliability evaluation and lifetime projection for gate dielectric, namely time dependent dielectric breakdown (TDDB), will no long be a suitable method for reliability evaluation, for gate dielectrics in low voltage operation.
{"title":"Can TDDB continue to serve as reliability test method for advance gate dielectric?","authors":"K. Cheung","doi":"10.1109/ICICDT.2004.1309979","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309979","url":null,"abstract":"Advanced gate dielectrics for MOSFET, be it ultra thin SiO/sub 2/ or high-k materials are destined for deep submicron technology that is moving increasingly toward 1 voltage or below operating voltage. In this paper, we show that the well-established method of reliability evaluation and lifetime projection for gate dielectric, namely time dependent dielectric breakdown (TDDB), will no long be a suitable method for reliability evaluation, for gate dielectrics in low voltage operation.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309908
T. Hirarnoto
In this paper, we present our recent research work on device structures in the 10 nm scale. Considering the short channel immunity in the nanoscale regime, the fully-depleted SOI structures, including double-gate structures and FinFETs, have been selected. The optimum device structures have been discussed in terms of short channel effect, low power, and device characteristic fluctuations. The idea of "body-effect conscious" device design is proposed.
{"title":"Advanced device structure for aggressively scaled MOSFETs","authors":"T. Hirarnoto","doi":"10.1109/ICICDT.2004.1309908","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309908","url":null,"abstract":"In this paper, we present our recent research work on device structures in the 10 nm scale. Considering the short channel immunity in the nanoscale regime, the fully-depleted SOI structures, including double-gate structures and FinFETs, have been selected. The optimum device structures have been discussed in terms of short channel effect, low power, and device characteristic fluctuations. The idea of \"body-effect conscious\" device design is proposed.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127313876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309890
Y. Tsai, David Duartep, N. Vijaykrishnan, M. J. Irwin
The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25/spl mu/m, 0.18/spl mu/m, 0.07/spl mu/m and 0.065/spl mu/m technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.
{"title":"Impact of process scaling on the efficacy of leakage reduction schemes","authors":"Y. Tsai, David Duartep, N. Vijaykrishnan, M. J. Irwin","doi":"10.1109/ICICDT.2004.1309890","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309890","url":null,"abstract":"The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25/spl mu/m, 0.18/spl mu/m, 0.07/spl mu/m and 0.065/spl mu/m technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"31 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131545937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309942
K. Bowman, S. Samaan, N. Hakim
A previous model derivation of the maximum clock frequency (FMAX) distribution for a VLSI design is reviewed to enable pre-silicon predictions of frequency bins and process/design optimization for specific product targets. Model projections were compared with measured FMAX data for a 0.25/spl mu/m microprocessor. In this paper, an additional comparison is performed with a 0.13/spl mu/m microprocessor, illustrating the close agreement between the simulated and measured distributions in mean, variance, and shape for different values of temperature and supply voltage. The previous model revealed that within-die variations primarily reduce the mean FMAX, or reciprocally, increase the mean of the maximum critical path delay (T/sub cp,max/) distribution. In this paper, a closed-form analytical equation of the T/sub cp,max/ mean increase is derived as an extension to the FMAX distribution model, which further elucidates the dependency on within-die variations. For a given set of process- and circuit-level parameters, this model provides insight into the delay guard-band required to achieve specific performance goals. Moreover, the model identifies the point of diminishing returns for redesigning critical paths in the tail of the timing histogram. To explore the region of validity, a model assumption for the shape of the critical path delay distribution is examined to guide practical VLSI design decisions.
{"title":"Maximum clock frequency distribution model with practical VLSI design considerations","authors":"K. Bowman, S. Samaan, N. Hakim","doi":"10.1109/ICICDT.2004.1309942","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309942","url":null,"abstract":"A previous model derivation of the maximum clock frequency (FMAX) distribution for a VLSI design is reviewed to enable pre-silicon predictions of frequency bins and process/design optimization for specific product targets. Model projections were compared with measured FMAX data for a 0.25/spl mu/m microprocessor. In this paper, an additional comparison is performed with a 0.13/spl mu/m microprocessor, illustrating the close agreement between the simulated and measured distributions in mean, variance, and shape for different values of temperature and supply voltage. The previous model revealed that within-die variations primarily reduce the mean FMAX, or reciprocally, increase the mean of the maximum critical path delay (T/sub cp,max/) distribution. In this paper, a closed-form analytical equation of the T/sub cp,max/ mean increase is derived as an extension to the FMAX distribution model, which further elucidates the dependency on within-die variations. For a given set of process- and circuit-level parameters, this model provides insight into the delay guard-band required to achieve specific performance goals. Moreover, the model identifies the point of diminishing returns for redesigning critical paths in the tail of the timing histogram. To explore the region of validity, a model assumption for the shape of the critical path delay distribution is examined to guide practical VLSI design decisions.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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