Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309945
R. Aitken, S. Becker
Aggressive performance and power goals for coming process generations are forcing rethinking of some of the basic assumptions of CMOS transistors, and leading to innovative approaches such as strained silicon and metal gates. These methods have implications for the design of standard cells, embedded memories, and other library components. This paper examines these new trends and shows how they affect the design of these components, and by extension, the systems-on-chip built from them.
{"title":"Cell library techniques using advanced transistor structures","authors":"R. Aitken, S. Becker","doi":"10.1109/ICICDT.2004.1309945","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309945","url":null,"abstract":"Aggressive performance and power goals for coming process generations are forcing rethinking of some of the basic assumptions of CMOS transistors, and leading to innovative approaches such as strained silicon and metal gates. These methods have implications for the design of standard cells, embedded memories, and other library components. This paper examines these new trends and shows how they affect the design of these components, and by extension, the systems-on-chip built from them.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133052952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309970
P. Lenahan
This paper reviews the present day understanding of several atomic scale defects and defect/hydrogen interactions found in Si/SiO/sub 2/-SiON systems which are likely involved in the negative bias temperature instability.
{"title":"Atomic scale defects in the Si/SiON system and the negative bias temperature instability","authors":"P. Lenahan","doi":"10.1109/ICICDT.2004.1309970","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309970","url":null,"abstract":"This paper reviews the present day understanding of several atomic scale defects and defect/hydrogen interactions found in Si/SiO/sub 2/-SiON systems which are likely involved in the negative bias temperature instability.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130209600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309971
G. Cellere, M. G. Valentini, Alessandro Paccagnella
pMOSFETs negatively biased under operating conditions and subjected to high temperature experience a progressive threshold voltage shift (Negative Bias Temperature Instability, NBTI). NBTI depends on several technological factors. We are showing in this paper a comprehensive study which discuss the NBTI dependence on channel length and channel width: overall, devices with shorter and wider channel are the most sensitive to NBTI. We are also discussing the strong sensitivity of NBTI to latent plasma induced damage: this makes NBTI a reliable index of latent damage.
{"title":"Effect of channel width, length, and latent damage on NBTI","authors":"G. Cellere, M. G. Valentini, Alessandro Paccagnella","doi":"10.1109/ICICDT.2004.1309971","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309971","url":null,"abstract":"pMOSFETs negatively biased under operating conditions and subjected to high temperature experience a progressive threshold voltage shift (Negative Bias Temperature Instability, NBTI). NBTI depends on several technological factors. We are showing in this paper a comprehensive study which discuss the NBTI dependence on channel length and channel width: overall, devices with shorter and wider channel are the most sensitive to NBTI. We are also discussing the strong sensitivity of NBTI to latent plasma induced damage: this makes NBTI a reliable index of latent damage.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131994965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309927
J. Parker, M. Reath, A. Krauss, W. J. Campbell
Arcing between the plasma and the wafer, kit, or target in PVD processes can cause significant wafer damage and foreign material contamination which limits wafer yield. Monitoring the plasma and quickly detecting this arcing phenomena is critical to ensuring that today's PVD processes run optimally and maximize product yield. This is particularly true in 300mm semiconductor manufacturing, where energies used are higher and more product is exposed to the plasma with each wafer run than in similar 200mm semiconductor manufacturing processes.
{"title":"Monitoring and preventing arc-induced wafer damage in 300mm manufacturing","authors":"J. Parker, M. Reath, A. Krauss, W. J. Campbell","doi":"10.1109/ICICDT.2004.1309927","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309927","url":null,"abstract":"Arcing between the plasma and the wafer, kit, or target in PVD processes can cause significant wafer damage and foreign material contamination which limits wafer yield. Monitoring the plasma and quickly detecting this arcing phenomena is critical to ensuring that today's PVD processes run optimally and maximize product yield. This is particularly true in 300mm semiconductor manufacturing, where energies used are higher and more product is exposed to the plasma with each wafer run than in similar 200mm semiconductor manufacturing processes.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"14 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114018826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309924
C. Ang, W. Lu, A. Yap, L. C. Goh, L. Goh, Y. K. Lim, C. Chua, L. Ko, T. Tan, S. Toh, L. Hsia
The influence of the SiN cap-layer NH/sub 3/ pre-treatment process on the electromigration (EM), plasma-induced damage (PID), gate oxide integrity (GOI) and BEOL defectivity has been studied. A noteworthy trade-off between EM, PID, GOI performance, and BEOL defectivity is revealed. On one hand, aggressive NH/sub 3/ pre-treatment process yields improved EM lifetime and PID. On the other hand, the process may provoke Cu hillock and IMD blister defects, as well as GOI yield failure if the treatment is over-aggressive. These disparate observations have been satisfactorily explained using RF plasma-induced heating mechanism in the underlying Cu and IMD. This paper also shows the need to adjust the NH/sub 3/ pretreatment process to meet the overall yield, reliability and manufacturability requirements.
{"title":"A study of SiN cap NH/sub 3/ plasma pre-treatment process on the PID, EM, GOI performance and BEOL defectivity in Cu dual damascene technology","authors":"C. Ang, W. Lu, A. Yap, L. C. Goh, L. Goh, Y. K. Lim, C. Chua, L. Ko, T. Tan, S. Toh, L. Hsia","doi":"10.1109/ICICDT.2004.1309924","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309924","url":null,"abstract":"The influence of the SiN cap-layer NH/sub 3/ pre-treatment process on the electromigration (EM), plasma-induced damage (PID), gate oxide integrity (GOI) and BEOL defectivity has been studied. A noteworthy trade-off between EM, PID, GOI performance, and BEOL defectivity is revealed. On one hand, aggressive NH/sub 3/ pre-treatment process yields improved EM lifetime and PID. On the other hand, the process may provoke Cu hillock and IMD blister defects, as well as GOI yield failure if the treatment is over-aggressive. These disparate observations have been satisfactorily explained using RF plasma-induced heating mechanism in the underlying Cu and IMD. This paper also shows the need to adjust the NH/sub 3/ pretreatment process to meet the overall yield, reliability and manufacturability requirements.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309897
G. Sery
Summary form only given. Logic product density and performance trends have continued to follow the course predicted by Moore's Law. To support the trends in the future and build logic products approaching one billion or more transistors before the end of the decade, several challenges must be met. These challenges include: 1) maintaining transistor/interconnect feature scaling, 2) the increasing power density dilemma, 3) increasing relative difficulty of 2-D feature resolution and general critical dimension control, 4) identifying cost effective solutions to increasing process and design database complexity, and 5), improving general performance and quality predictability in the face of the growing control, complexity and predictability issues. The trend in transistor scaling can be maintained while addressing the power density issue with new transistor structures, design approaches, and product architectures (e.g. high-k, metal gate, etc.). Items 3 to 5 are the focus of this work and are also strongly inter-related. The general 2-D patterning and resolution control problems will require several solution approaches both through design and technology e.g. reduce design degrees of freedom, use of simpler arrayed structures, improved uniformity, improved tools, etc. The data base complexity/cost problem will require solutions likely to involve use of improved data structure, improved use of hierarchy, and improved software and hardware solutions. Performance assessment, predictability and quality assessment will benefit from solutions to the control and complexity issues noted above. In addition, new design techniques/tools as well as improved process characterization models and methods can address the general performance/quality assessment challenge.
{"title":"Impact of process variation phenomena on performance and quality assessment","authors":"G. Sery","doi":"10.1109/ICICDT.2004.1309897","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309897","url":null,"abstract":"Summary form only given. Logic product density and performance trends have continued to follow the course predicted by Moore's Law. To support the trends in the future and build logic products approaching one billion or more transistors before the end of the decade, several challenges must be met. These challenges include: 1) maintaining transistor/interconnect feature scaling, 2) the increasing power density dilemma, 3) increasing relative difficulty of 2-D feature resolution and general critical dimension control, 4) identifying cost effective solutions to increasing process and design database complexity, and 5), improving general performance and quality predictability in the face of the growing control, complexity and predictability issues. The trend in transistor scaling can be maintained while addressing the power density issue with new transistor structures, design approaches, and product architectures (e.g. high-k, metal gate, etc.). Items 3 to 5 are the focus of this work and are also strongly inter-related. The general 2-D patterning and resolution control problems will require several solution approaches both through design and technology e.g. reduce design degrees of freedom, use of simpler arrayed structures, improved uniformity, improved tools, etc. The data base complexity/cost problem will require solutions likely to involve use of improved data structure, improved use of hierarchy, and improved software and hardware solutions. Performance assessment, predictability and quality assessment will benefit from solutions to the control and complexity issues noted above. In addition, new design techniques/tools as well as improved process characterization models and methods can address the general performance/quality assessment challenge.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122558270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309935
R. Puri
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages arid multiple threshold voltages in the optimization of dynamic arid static power. The use of multiple supply voltages presents some unique Physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters.
{"title":"Minimizing power under performance constraint","authors":"R. Puri","doi":"10.1109/ICICDT.2004.1309935","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309935","url":null,"abstract":"Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages arid multiple threshold voltages in the optimization of dynamic arid static power. The use of multiple supply voltages presents some unique Physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121568288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309911
Qiang Chen, Lihui Wang, J. Meindl
Compact, physics-based models of subthreshold swing and threshold voltage are presented for undoped double-gate (DG) MOSFETs in symmetric, asymmetric, and ground-plane modes of operation. Applying the new device models, a novel scale-length based methodology is demonstrated to comprehensively and exhaustively investigate threshold voltage variations in DG MOSFETs. In light of ultra-thin silicon film used as the channel and possible introduction of high-permittivity gate dielectrics, physical, analytical models of quantum mechanical effects, gate direct tunneling current, and fringe-induced barrier lowering effect are developed to assess their impact on DG MOSFET scalability. Scaling limits projections indicate that individual DG MOSFET's with good turn-off behavior are feasible at 10nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires significant improvement in process control.
{"title":"Physics-based device models for nanoscale double-gate MOSFETs","authors":"Qiang Chen, Lihui Wang, J. Meindl","doi":"10.1109/ICICDT.2004.1309911","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309911","url":null,"abstract":"Compact, physics-based models of subthreshold swing and threshold voltage are presented for undoped double-gate (DG) MOSFETs in symmetric, asymmetric, and ground-plane modes of operation. Applying the new device models, a novel scale-length based methodology is demonstrated to comprehensively and exhaustively investigate threshold voltage variations in DG MOSFETs. In light of ultra-thin silicon film used as the channel and possible introduction of high-permittivity gate dielectrics, physical, analytical models of quantum mechanical effects, gate direct tunneling current, and fringe-induced barrier lowering effect are developed to assess their impact on DG MOSFET scalability. Scaling limits projections indicate that individual DG MOSFET's with good turn-off behavior are feasible at 10nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires significant improvement in process control.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122488494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309946
Zhihong Liu, Weiquan Zhang, Fuchen Mu
In this paper, the methodology of the reliability modeling and simulation for the state-of-the-art technology is presented. The extraction for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method is discussed. The integration of these models into the transistor level and gate level simulation flow can be used by the designers to satisfy the reliability requirements.
{"title":"Build-in reliability analysis for circuit design in the nanometer technology era","authors":"Zhihong Liu, Weiquan Zhang, Fuchen Mu","doi":"10.1109/ICICDT.2004.1309946","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309946","url":null,"abstract":"In this paper, the methodology of the reliability modeling and simulation for the state-of-the-art technology is presented. The extraction for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method is discussed. The integration of these models into the transistor level and gate level simulation flow can be used by the designers to satisfy the reliability requirements.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131054079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309953
B. Nguyen, A. Thean, T. White, A. Vandooren, M. Sadaka, L. Mathew, A. Barr, S. Thomas, M. Zalava, Da Zhang, D. Eades, Zhonghai Shi, J. Schaeffer, D. Triyoso, S. Samavedam, V. Vartanian, T. Stephen, B. Goolsby, S. Zollner, Ran Liu, R. Noble, T. Nguyen, V. Dhandapani, B. Xie, X. Wang, J. Jiang, R. Rai, M. Sadd, M. Ramón, S. Kalpat, L. Prabhu, V. Kaushik, Y. Du, T. Dao, M. Mendicino, Marius K. Orlowski, P. Tobin, J. Mogab, S. Venkatesan
In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
{"title":"Integration challenges of new materials and device architectures for IC applications","authors":"B. Nguyen, A. Thean, T. White, A. Vandooren, M. Sadaka, L. Mathew, A. Barr, S. Thomas, M. Zalava, Da Zhang, D. Eades, Zhonghai Shi, J. Schaeffer, D. Triyoso, S. Samavedam, V. Vartanian, T. Stephen, B. Goolsby, S. Zollner, Ran Liu, R. Noble, T. Nguyen, V. Dhandapani, B. Xie, X. Wang, J. Jiang, R. Rai, M. Sadd, M. Ramón, S. Kalpat, L. Prabhu, V. Kaushik, Y. Du, T. Dao, M. Mendicino, Marius K. Orlowski, P. Tobin, J. Mogab, S. Venkatesan","doi":"10.1109/ICICDT.2004.1309953","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309953","url":null,"abstract":"In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124002918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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