Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309964
G. Cellere, A. Paccagnella, P. Caprara, A. Visconti
We have shown results on irradiation of EPROM and Flash devices with Ag and I ions. Bit flip are seldom observed in FG memories, because the control circuitry is by far more radiation sensitive than the memory array itself. Nevertheless, we have shown that, after heavy ions irradiation, cells may experience large threshold voltage shifts. Drain current or threshold voltage shifts are randomly distributed across the device. In particular, charge loss detected after a heavy ion stroke a FG is too large to be described by existing models. The aim of future work is to extend the understanding of the physical mechanism underlying charge loss from the programmed FG.
{"title":"Heavy ion irradiation of floating gate memory cells","authors":"G. Cellere, A. Paccagnella, P. Caprara, A. Visconti","doi":"10.1109/ICICDT.2004.1309964","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309964","url":null,"abstract":"We have shown results on irradiation of EPROM and Flash devices with Ag and I ions. Bit flip are seldom observed in FG memories, because the control circuitry is by far more radiation sensitive than the memory array itself. Nevertheless, we have shown that, after heavy ions irradiation, cells may experience large threshold voltage shifts. Drain current or threshold voltage shifts are randomly distributed across the device. In particular, charge loss detected after a heavy ion stroke a FG is too large to be described by existing models. The aim of future work is to extend the understanding of the physical mechanism underlying charge loss from the programmed FG.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128326505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309966
P. Aum
{"title":"Low-K cu damascene interconnection leakage and process induced damage assessment","authors":"P. Aum","doi":"10.1109/ICICDT.2004.1309966","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309966","url":null,"abstract":"","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309913
P. Coronel, S. Harrison, R. Cerutti, S. Monfray, S. Skotnicki
Utilizing the SON (Silicon On Nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (High Performance and Low Power) with very high Ion/Ioff trade off. Drive currents of 1954/spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333/spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained @1.2V with Tox = 20A and Lgate = 70nm. DIBL is very well controlled, measured below 60mV for gates as short as 40nm. These features place our devices among the most performant ever reported. After this GAA planar device demonstration, we are looking for his optimization in consideration of the future technologic node challenges: We define a new architecture for GAA and DG device in order to minimize the overlap capacitance, to use a SOI substrate and to create a GAA circuit with the same layout density than bulk. We develop a new concept of Metal gate and/or High-K integration in MOSFET: the PRETCH (Poly Replacement Through Contact Hole) to allow the best compromise between the mobility, and the Vt adjust for the future device generation. The first demonstration of the PRETCH integration was done on bulk CMOS.
{"title":"Highly performant double gate MOSFET realized with SON process: how we address the design and process for the GAA SON challenges ?","authors":"P. Coronel, S. Harrison, R. Cerutti, S. Monfray, S. Skotnicki","doi":"10.1109/ICICDT.2004.1309913","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309913","url":null,"abstract":"Utilizing the SON (Silicon On Nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (High Performance and Low Power) with very high Ion/Ioff trade off. Drive currents of 1954/spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333/spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained @1.2V with Tox = 20A and Lgate = 70nm. DIBL is very well controlled, measured below 60mV for gates as short as 40nm. These features place our devices among the most performant ever reported. After this GAA planar device demonstration, we are looking for his optimization in consideration of the future technologic node challenges: We define a new architecture for GAA and DG device in order to minimize the overlap capacitance, to use a SOI substrate and to create a GAA circuit with the same layout density than bulk. We develop a new concept of Metal gate and/or High-K integration in MOSFET: the PRETCH (Poly Replacement Through Contact Hole) to allow the best compromise between the mobility, and the Vt adjust for the future device generation. The first demonstration of the PRETCH integration was done on bulk CMOS.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The in-line plasma process monitoring was successfully performed with non-contact direct measurement (NCDM) tool and its results were well matched with those from devices. Using this monitoring method, we developed a plasma nitrided gate oxide process for mobile DRAMs with low operating voltage. We confirm that plasma nitrided gate oxide can block the boron penetration in DRAMs, which has higher thermal budget than other devices, and that the NCDM tool can be used for checking the degree of plasma nitridation. We assure that the NCDM tool is a time-effective tool for plasma nitridation process development.
{"title":"The development of dual gate poly scheme with plasma nitrided gate oxide for mobile high performance DRAMs: plasma process monitoring and the correlation with electrical results","authors":"Sug-hun Hong, Taek-Soo Jeon, Bonwon Koo, Seok-Hun Hyun, Yun-Seung Shin, U-In Chung, June Moon","doi":"10.1109/ICICDT.2004.1309948","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309948","url":null,"abstract":"The in-line plasma process monitoring was successfully performed with non-contact direct measurement (NCDM) tool and its results were well matched with those from devices. Using this monitoring method, we developed a plasma nitrided gate oxide process for mobile DRAMs with low operating voltage. We confirm that plasma nitrided gate oxide can block the boron penetration in DRAMs, which has higher thermal budget than other devices, and that the NCDM tool can be used for checking the degree of plasma nitridation. We assure that the NCDM tool is a time-effective tool for plasma nitridation process development.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133747365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309902
Cosimo Gerardi, B. DeSalvo, S. Lombardo, Thierry Baron
We have fabricated nanocrystal memories both single cells and arrays by using low pressure chemical vapor deposition of silicon nanocrystals. The potentialities of nanocrystal memories are discussed both in terms of nanocrystal deposition and control dielectrics optimization. Excellent performances are achieved, showing that this technology shows potentialities for non volatile memory cell scaling. In addition we discuss the impact of the fluctuations in nanocrystals distribution on the scaling possibilities of these memories.
{"title":"Performances of Si nanocrystal memories obtained by by CVD and their potentialities to further scaling of non-volatile memories","authors":"Cosimo Gerardi, B. DeSalvo, S. Lombardo, Thierry Baron","doi":"10.1109/ICICDT.2004.1309902","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309902","url":null,"abstract":"We have fabricated nanocrystal memories both single cells and arrays by using low pressure chemical vapor deposition of silicon nanocrystals. The potentialities of nanocrystal memories are discussed both in terms of nanocrystal deposition and control dielectrics optimization. Excellent performances are achieved, showing that this technology shows potentialities for non volatile memory cell scaling. In addition we discuss the impact of the fluctuations in nanocrystals distribution on the scaling possibilities of these memories.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125175929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309972
J. Lauer, J. Shohet, R. Hansen, R. D. Bathke, B. Grierson, G. Upadhyaya, K. Kukkady, J. Kalwitz
Dielectric charging plays a key role in processing damage of semiconductor devices. VUV radiation with energies in the range of 4-30 eV can induce charge on electronic materials. Radiation charging of Si wafers coated with 3000A of Si/sub 3/N/sub 4/ from synchrotron VUV exposure with photon fluxes in the range of 10/sup 9/-10/sup 13/ photons/sec cm/sup -2/ were measured with a Kelvin probe. The photoemission current and substrate voltage were monitored during each exposure. The integral of photoemission current was compared to the net charge measured with the Kelvin probe for VUV photon energies between 7-21 eV. The net charge induced on the dielectric results from both photoemission (which saturates for long exposure times) as well as from charge carriers generated within the dielectric. Since the threshold photon energy for photoemission is higher than that for electron-hole pair production, it is seen that photoemission can be minimized if the photon energies are below the threshold energy.
{"title":"Energy dependence of vacuum-ultraviolet-induced radiation damage to electronic materials","authors":"J. Lauer, J. Shohet, R. Hansen, R. D. Bathke, B. Grierson, G. Upadhyaya, K. Kukkady, J. Kalwitz","doi":"10.1109/ICICDT.2004.1309972","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309972","url":null,"abstract":"Dielectric charging plays a key role in processing damage of semiconductor devices. VUV radiation with energies in the range of 4-30 eV can induce charge on electronic materials. Radiation charging of Si wafers coated with 3000A of Si/sub 3/N/sub 4/ from synchrotron VUV exposure with photon fluxes in the range of 10/sup 9/-10/sup 13/ photons/sec cm/sup -2/ were measured with a Kelvin probe. The photoemission current and substrate voltage were monitored during each exposure. The integral of photoemission current was compared to the net charge measured with the Kelvin probe for VUV photon energies between 7-21 eV. The net charge induced on the dielectric results from both photoemission (which saturates for long exposure times) as well as from charge carriers generated within the dielectric. Since the threshold photon energy for photoemission is higher than that for electron-hole pair production, it is seen that photoemission can be minimized if the photon energies are below the threshold energy.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115965795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309916
L. Mathew, Yang Du, A. Thean, M. Sadd, A. Vandooren, C. Parker, T. Stephens, R. Mora, R. Rai, M. Zavala, D. Sing, S. Kalpai, J. Hughes, R. Shimer, S. Jallepalli, G. Workman, B. White, B. Nguyen, A. Mogab
Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. It is desirable to fabricate multi-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully.
{"title":"Multi gated device architectures advances, advantages and challenges","authors":"L. Mathew, Yang Du, A. Thean, M. Sadd, A. Vandooren, C. Parker, T. Stephens, R. Mora, R. Rai, M. Zavala, D. Sing, S. Kalpai, J. Hughes, R. Shimer, S. Jallepalli, G. Workman, B. White, B. Nguyen, A. Mogab","doi":"10.1109/ICICDT.2004.1309916","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309916","url":null,"abstract":"Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. It is desirable to fabricate multi-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309960
Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford
Atomic layer deposition (ALD) has gained acceptance as a thin film deposition technique in the semiconductor device manufacturing due to the stringent requirements of thickness uniformity, thermal budget, and step coverage over aggressive advanced IC device structures. We have developed unique ALD processes to deposit multi-component thin films such as HfSiO/sub x/ for high-k gate dielectric applications by co-injection of Hf and Si precursors. This process enables the formation of homogeneous single-layer hafnium silicate films as deposited. In contrast, the commonly used nanolaminate technique (i.e., an alternating stack of HfO/sub 2/ and SiO/sub 2/ layers) requires high temperature post-deposition annealing to interdiffuse the HfO/sub 2/ and SiO/sub 2/ to form a hafnium silicate film. We have also developed an Al/sub 2/O/sub 3/ batch ALD process on 300mm. Si (100) substrates using a multiwafer hot-wall reactor. Deposition of Al/sub 2/O/sub 3/ thin films from trimethylaluminum and ozone was accomplished using a 50-wafer batch system. For 4.6 nm thick Al/sub 2/O/sub 3/, excellent film thickness uniformity with a within-wafer (WIW) non-uniformity of <1.0% 1/spl sigma/ and a wafer to wafer (WTW) thickness non-uniformity of less than /spl plusmn/1.0% was achieved over a full batch.
{"title":"Atomic layer deposition of high-k thin films for gate and capacitor dielectrics","authors":"Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford","doi":"10.1109/ICICDT.2004.1309960","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309960","url":null,"abstract":"Atomic layer deposition (ALD) has gained acceptance as a thin film deposition technique in the semiconductor device manufacturing due to the stringent requirements of thickness uniformity, thermal budget, and step coverage over aggressive advanced IC device structures. We have developed unique ALD processes to deposit multi-component thin films such as HfSiO/sub x/ for high-k gate dielectric applications by co-injection of Hf and Si precursors. This process enables the formation of homogeneous single-layer hafnium silicate films as deposited. In contrast, the commonly used nanolaminate technique (i.e., an alternating stack of HfO/sub 2/ and SiO/sub 2/ layers) requires high temperature post-deposition annealing to interdiffuse the HfO/sub 2/ and SiO/sub 2/ to form a hafnium silicate film. We have also developed an Al/sub 2/O/sub 3/ batch ALD process on 300mm. Si (100) substrates using a multiwafer hot-wall reactor. Deposition of Al/sub 2/O/sub 3/ thin films from trimethylaluminum and ozone was accomplished using a 50-wafer batch system. For 4.6 nm thick Al/sub 2/O/sub 3/, excellent film thickness uniformity with a within-wafer (WIW) non-uniformity of <1.0% 1/spl sigma/ and a wafer to wafer (WTW) thickness non-uniformity of less than /spl plusmn/1.0% was achieved over a full batch.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309957
H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, S. Kalpat, J. Grant, Z.X. Jiang, D. Gilmer, D. Menke, W. Taylor, O. Adetutu, B. White
Device instability is one of the most challenging issues to implement High-K gate dielectric. Incorporation of deuterium during the ALD process effectively improves the interface quality that enhances High-K device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD High-K gate dielectric processing is the final choice.
{"title":"Threshold voltage instability and plasma induced damage of polySi/HfO/sub 2/ devices - positive impact of deuterium incorporation","authors":"H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, S. Kalpat, J. Grant, Z.X. Jiang, D. Gilmer, D. Menke, W. Taylor, O. Adetutu, B. White","doi":"10.1109/ICICDT.2004.1309957","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309957","url":null,"abstract":"Device instability is one of the most challenging issues to implement High-K gate dielectric. Incorporation of deuterium during the ALD process effectively improves the interface quality that enhances High-K device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD High-K gate dielectric processing is the final choice.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134579027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309909
M. Horstmann, D. Greenlaw, T. Feudel, Andy Wei, K. Frohberg, G. Burbach, M. Gerhardt, Markus Lenski, R. Stephan, K. Wieczorek, Matthias Schaller, J. Hohage, H. Ruelke, J. Klais, P. Huebler, Scott Luning, R. Bentum, G. Grasshoff, C. Schwan, Jon D. Cheek, J. Buller, S. Krishnan, M. Raab, N. Kepler
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.
{"title":"Advanced transistor structures for high performance microprocessors","authors":"M. Horstmann, D. Greenlaw, T. Feudel, Andy Wei, K. Frohberg, G. Burbach, M. Gerhardt, Markus Lenski, R. Stephan, K. Wieczorek, Matthias Schaller, J. Hohage, H. Ruelke, J. Klais, P. Huebler, Scott Luning, R. Bentum, G. Grasshoff, C. Schwan, Jon D. Cheek, J. Buller, S. Krishnan, M. Raab, N. Kepler","doi":"10.1109/ICICDT.2004.1309909","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309909","url":null,"abstract":"Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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