Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309947
A. Modelli, A. Visconti, R. Bez
With reference to the mainstream technology, the most relevant failure mechanisms that affect reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The degradation of device. performance induced by program/erase cycling is discussed, specifically for what concern the leakage that affect a very small fraction of memory cells after cycling. The dependence of the leakage on tunnel oxide thickness, number of cycles, and temperature is analyzed. The leakage current is explained by trap-assisted tunneling involving one, two or more traps, with decreasing occurrence probability. Finally, data are presented showing the robustness of scaled Flash memory to alpha particles and electromagnetic radiation.
{"title":"Advanced flash memory reliability","authors":"A. Modelli, A. Visconti, R. Bez","doi":"10.1109/ICICDT.2004.1309947","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309947","url":null,"abstract":"With reference to the mainstream technology, the most relevant failure mechanisms that affect reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The degradation of device. performance induced by program/erase cycling is discussed, specifically for what concern the leakage that affect a very small fraction of memory cells after cycling. The dependence of the leakage on tunnel oxide thickness, number of cycles, and temperature is analyzed. The leakage current is explained by trap-assisted tunneling involving one, two or more traps, with decreasing occurrence probability. Finally, data are presented showing the robustness of scaled Flash memory to alpha particles and electromagnetic radiation.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309978
Y. Mitani, H. Satake
In this paper, time evolutions of threshold voltage (V/sub TH/) in p-MOSFETs have been investigated and discussed from the viewpoint of a statistical distribution. No change in the dispersion of the V/sub TH/ distribution under bias temperature (BT) stress was observed, whereas average values of V/sub TH/ monotonically increased. On the other hand, the V/sub TH/ distribution was remarkably deteriorated after soft breakdown progression of gate oxides.
{"title":"Time evolution of V/sub TH/ distribution under BT stress in ultra-thin gate oxides","authors":"Y. Mitani, H. Satake","doi":"10.1109/ICICDT.2004.1309978","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309978","url":null,"abstract":"In this paper, time evolutions of threshold voltage (V/sub TH/) in p-MOSFETs have been investigated and discussed from the viewpoint of a statistical distribution. No change in the dispersion of the V/sub TH/ distribution under bias temperature (BT) stress was observed, whereas average values of V/sub TH/ monotonically increased. On the other hand, the V/sub TH/ distribution was remarkably deteriorated after soft breakdown progression of gate oxides.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129971682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309980
Si-Woo Lee, Changmoon Ahn, B. Kim, S. Chang, D.H. Han, C. An, J. Won, Jaeyoung Kim, Seungwook Jung, Dongho-Shin, Kyungseok Oh, Won-seong Lee, Donggun Park
Degradation of thin oxide is investigated under various HDP-CVD process conditions such as deposition time, plasma power, process temperature and electrode spacing. We observed that the oxide is vulnerable to be damaged at longer HDP-CVD process time, higher plasma power and higher process temperature using BV and Qbd measurement in whole area of 300mm wafers. It also strongly related with the equipment parameter such as electrode spacing. The oxide degradation phenomena were rather successfully explained by charging damage through photoconduction mechanism.
{"title":"Thin oxide degradation from HDP-CVD oxide deposition in 300mm process","authors":"Si-Woo Lee, Changmoon Ahn, B. Kim, S. Chang, D.H. Han, C. An, J. Won, Jaeyoung Kim, Seungwook Jung, Dongho-Shin, Kyungseok Oh, Won-seong Lee, Donggun Park","doi":"10.1109/ICICDT.2004.1309980","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309980","url":null,"abstract":"Degradation of thin oxide is investigated under various HDP-CVD process conditions such as deposition time, plasma power, process temperature and electrode spacing. We observed that the oxide is vulnerable to be damaged at longer HDP-CVD process time, higher plasma power and higher process temperature using BV and Qbd measurement in whole area of 300mm wafers. It also strongly related with the equipment parameter such as electrode spacing. The oxide degradation phenomena were rather successfully explained by charging damage through photoconduction mechanism.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309922
Hichem MSaad
Summary form only given. The semiconductor industry has witnessed a successful introduction of copper based interconnects and low permittivity insulators with 130nm node devices. The advent of 90nm node devices has led to the introduction of first generation of carbon doped dielectric films. Further scaling will require materials with lower permittivity and this has accelerated the development of a second generation of carbon doped oxides with imbedded porosity. While the addition of carbon to a silicon based dielectric lowers the permittivity of the insulator, carbon doping may also lead to degradation in the surface properties of such films. Frequently, carbon enrichment at surfaces is known to cause issues with the wetting characteristics of the surface. In addition, the mechanical strength of interfaces formed with carbon enriched surfaces may be poor compared to congruent surfaces. The high number of chemically and morphologically different materials in the integrated interconnects structure increase the possibility of mechanical structural failure. A detailed understanding of the basic material properties and the behavior of the carbon doped materials during subsequent processing is therefore of prime importance. This paper will present an overview of process and film property characterization of different generations of carbon doped oxides. Integration properties of these films and correlation to processing parameters and physical properties of the materials will be discussed. Novel processing techniques are discussed that enable the implementation of advanced low dielectric constant materials without sacrificing the high volume manufacturability of such films.
{"title":"Film properties and integration performance of carbon doped oxides","authors":"Hichem MSaad","doi":"10.1109/ICICDT.2004.1309922","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309922","url":null,"abstract":"Summary form only given. The semiconductor industry has witnessed a successful introduction of copper based interconnects and low permittivity insulators with 130nm node devices. The advent of 90nm node devices has led to the introduction of first generation of carbon doped dielectric films. Further scaling will require materials with lower permittivity and this has accelerated the development of a second generation of carbon doped oxides with imbedded porosity. While the addition of carbon to a silicon based dielectric lowers the permittivity of the insulator, carbon doping may also lead to degradation in the surface properties of such films. Frequently, carbon enrichment at surfaces is known to cause issues with the wetting characteristics of the surface. In addition, the mechanical strength of interfaces formed with carbon enriched surfaces may be poor compared to congruent surfaces. The high number of chemically and morphologically different materials in the integrated interconnects structure increase the possibility of mechanical structural failure. A detailed understanding of the basic material properties and the behavior of the carbon doped materials during subsequent processing is therefore of prime importance. This paper will present an overview of process and film property characterization of different generations of carbon doped oxides. Integration properties of these films and correlation to processing parameters and physical properties of the materials will be discussed. Novel processing techniques are discussed that enable the implementation of advanced low dielectric constant materials without sacrificing the high volume manufacturability of such films.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121825129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309965
H. McCulloh, B. O'Connell, S. Drizlikh, D. Brisbin
Plasma damage resulting from fluorine doped High Density Plasma Deposition (FHDP) was investigated. A dielectric barrier layer placed either directly under the FHDP or directly over the gate was found to protect the gate oxide from plasma damage. The mechanism by which the dielectric layers counteract plasma damage from upper dielectric layers is investigated.
{"title":"Reducing FHDP plasma induced damage with silicon-rich oxide and oxynitride barrier layers","authors":"H. McCulloh, B. O'Connell, S. Drizlikh, D. Brisbin","doi":"10.1109/ICICDT.2004.1309965","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309965","url":null,"abstract":"Plasma damage resulting from fluorine doped High Density Plasma Deposition (FHDP) was investigated. A dielectric barrier layer placed either directly under the FHDP or directly over the gate was found to protect the gate oxide from plasma damage. The mechanism by which the dielectric layers counteract plasma damage from upper dielectric layers is investigated.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122704835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309900
R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White
This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.
{"title":"An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V","authors":"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White","doi":"10.1109/ICICDT.2004.1309900","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309900","url":null,"abstract":"This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131126436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309926
T. Hook, H. Bonges, D. Harmon, W. Lai
In this paper we show that the SOI FET is conductive during processing, and also that a FET shunted across the gate and source/drain of another transistor does in fact protect that device against charging damage.
{"title":"SOI charging prevention: chip-level net tracing and diode protection","authors":"T. Hook, H. Bonges, D. Harmon, W. Lai","doi":"10.1109/ICICDT.2004.1309926","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309926","url":null,"abstract":"In this paper we show that the SOI FET is conductive during processing, and also that a FET shunted across the gate and source/drain of another transistor does in fact protect that device against charging damage.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133266309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309955
C. O. Chui, K. Saraswat
Various advanced germanium (Ge) metal-oxide-semiconductor field-effect transistor (MOSFET) technologies with high-permittivity (high-/spl kappa/) gate dielectrics and shallow junctions have been demonstrated. Numerous novel Ge technologies on surface cleaning, gate dielectric, and dopant incorporation are presented In addition, we disclose an innovative self-aligned gate-last fabrication process not only to demonstrate functional Ge MOSFETs, but also to provide a vehicle to characterize many novel material integration schemes.
{"title":"Advanced germanium MOSFET technologies with high-/spl kappa/ gate dielectrics and shallow junctions","authors":"C. O. Chui, K. Saraswat","doi":"10.1109/ICICDT.2004.1309955","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309955","url":null,"abstract":"Various advanced germanium (Ge) metal-oxide-semiconductor field-effect transistor (MOSFET) technologies with high-permittivity (high-/spl kappa/) gate dielectrics and shallow junctions have been demonstrated. Numerous novel Ge technologies on surface cleaning, gate dielectric, and dopant incorporation are presented In addition, we disclose an innovative self-aligned gate-last fabrication process not only to demonstrate functional Ge MOSFETs, but also to provide a vehicle to characterize many novel material integration schemes.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309899
M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani
A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.
{"title":"A 0.18 /spl mu/m 4 Mbit toggling MRAM","authors":"M. Durlam, D. Addie, J. Åkerman, B. Butcher, P. Brown, J. Chan, M. Deherrera, B. Engel, B. Feil, G. Grynkewich, J. Janesky, M. Johnson, K. Kyler, J. Molla, J. Martin, K. Nagel, J. Nahas, J. Ren, N. Rizzo, T. Rodriguez, L. Savtchenko, J. Salter, J. Slaughter, K. Smith, J.J. Sun, M. Lien, K. Papworth, P. Shah, W. Qin, R. Williams, L. Wise, S. Tehrani","doi":"10.1109/ICICDT.2004.1309899","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309899","url":null,"abstract":"A 4 Mbit Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is described. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) bit cell. The 4 Mbit MRAM circuit was designed in a five level metal, 0.18 /spl mu/m CMOS process with a bit cell size of 1.55 /spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4 Mbit circuit is the largest MRAM memory demonstration to date.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309917
T. Dao
Power consumption including leakage current is becoming one of the most important limiting factors in VLSI, especially in the sub-65nm technologies. While technologies are facing multiple challenges in scaling, there have been successful developments on reduction of power consumption and leakage current in circuit and system design techniques based on the cooperation between two traditionally separated technical fields - technology and design. The benefits of separate gate access capability of DG-FDSOI technology on supporting these kinds of cooperation techniques have been addressed together with the impact on circuit designs which take advantages of this technology.
{"title":"Advanced double-gate fully-depleted silicon-on-insulator (DG-FDSOI) device and device impact on circuit design & power management","authors":"T. Dao","doi":"10.1109/ICICDT.2004.1309917","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309917","url":null,"abstract":"Power consumption including leakage current is becoming one of the most important limiting factors in VLSI, especially in the sub-65nm technologies. While technologies are facing multiple challenges in scaling, there have been successful developments on reduction of power consumption and leakage current in circuit and system design techniques based on the cooperation between two traditionally separated technical fields - technology and design. The benefits of separate gate access capability of DG-FDSOI technology on supporting these kinds of cooperation techniques have been addressed together with the impact on circuit designs which take advantages of this technology.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124715193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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