This paper proposes an automatic debugging method for single-electron transistor arrays. The method iteratively calls a SAT solver to find a counterexample and identify errors based on the counterexample. It can fix an incorrect SET array which can be corrected by changing an edge's configuration. The experimental results show that the proposed debugging method is efficient and effective. It finds all the possible corrections for an incorrect SET array within an average of 0.021 seconds.
{"title":"A counterexample-based debugging method for reconfigurable single-electron transistor arrays","authors":"Wenjiao Zeng, Siyi Liu, Yu-Da Chen, Yung-Chih Chen","doi":"10.1109/EDSSC.2017.8126417","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126417","url":null,"abstract":"This paper proposes an automatic debugging method for single-electron transistor arrays. The method iteratively calls a SAT solver to find a counterexample and identify errors based on the counterexample. It can fix an incorrect SET array which can be corrected by changing an edge's configuration. The experimental results show that the proposed debugging method is efficient and effective. It finds all the possible corrections for an incorrect SET array within an average of 0.021 seconds.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125070566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126524
J. Ghosh
It is well known that a two-dimensional electron gas (2DEG) exists at the MgZnO/ZnO interface. Both the formation mechanism and the origin of this 2DEG is of immense interest. The origin has been attributed to the polarization charge present coupled with the donor-like surface states on the MgZnO surface. In this paper, a physics-based model is described to explain the 2DEG as well as the bare surface barrier height by considering the low density surface donor states distributed over a range of energies below a particular donor energy level. The model shows good agreement with the reported experimental results. The model for the 2DEG in a MgZnO/CdZnO heterostructure is also analyzed.
{"title":"Modeling of 2DEG and surface barrier height in ZnO-based heterostructures using surface states","authors":"J. Ghosh","doi":"10.1109/EDSSC.2017.8126524","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126524","url":null,"abstract":"It is well known that a two-dimensional electron gas (2DEG) exists at the MgZnO/ZnO interface. Both the formation mechanism and the origin of this 2DEG is of immense interest. The origin has been attributed to the polarization charge present coupled with the donor-like surface states on the MgZnO surface. In this paper, a physics-based model is described to explain the 2DEG as well as the bare surface barrier height by considering the low density surface donor states distributed over a range of energies below a particular donor energy level. The model shows good agreement with the reported experimental results. The model for the 2DEG in a MgZnO/CdZnO heterostructure is also analyzed.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124119298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126500
Wei-Han Chen, K. Tang
In this work, an automatic gain control amplifier for high voltage spindle recording is proposed. It is composed of a fix-gain amplifier and a variable gain amplifier (VGA) with threshold detecting logic to control the gain of VGA. The system provides 3 different gain set: 54dB, 60dB and 66dB. The bandwidth of the system covers from 0.5Hz to 1.5 KHz. The power is 7.7uW, and the integral input referred noise is 5.5uV. With the threshold detecting logic, the system can avoid saturation when high voltage spindle happens.
{"title":"An automatic gain control amplifier for high voltage spindle recording","authors":"Wei-Han Chen, K. Tang","doi":"10.1109/EDSSC.2017.8126500","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126500","url":null,"abstract":"In this work, an automatic gain control amplifier for high voltage spindle recording is proposed. It is composed of a fix-gain amplifier and a variable gain amplifier (VGA) with threshold detecting logic to control the gain of VGA. The system provides 3 different gain set: 54dB, 60dB and 66dB. The bandwidth of the system covers from 0.5Hz to 1.5 KHz. The power is 7.7uW, and the integral input referred noise is 5.5uV. With the threshold detecting logic, the system can avoid saturation when high voltage spindle happens.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127763658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126460
Guantong Su, Guoqiang Bai
We have proposed a method of designing embedded clock-cycle-sensitive Hardware Trojans (HTs) to manipulate finite state machine (FSM). By using pipeline to choose and customize critical path, the Trojans can facilitate a series of attack and need no redundant circuits. One cannot detect any malicious architecture through logic analysis because the proposed circuitry is the part of FSM. Furthermore, this kind of HTs alerts the trusted systems designers to the importance of clock tree structure. The attackers may utilize modified clock to bypass certain security model or change the circuit behavior.
{"title":"The undetectable clock cycle sensitive hardware trojan","authors":"Guantong Su, Guoqiang Bai","doi":"10.1109/EDSSC.2017.8126460","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126460","url":null,"abstract":"We have proposed a method of designing embedded clock-cycle-sensitive Hardware Trojans (HTs) to manipulate finite state machine (FSM). By using pipeline to choose and customize critical path, the Trojans can facilitate a series of attack and need no redundant circuits. One cannot detect any malicious architecture through logic analysis because the proposed circuitry is the part of FSM. Furthermore, this kind of HTs alerts the trusted systems designers to the importance of clock tree structure. The attackers may utilize modified clock to bypass certain security model or change the circuit behavior.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of 6.1 ps after a 17 dB loss channel at 60Gb/s.
{"title":"A 10–60 Gb/s wireline transmitter with a 4-tap multiple-MUX based FFE","authors":"Fangxu Lv, Jianye Wang, Xuqiang Zheng, S. Yuan, Ziqiang Wang, Yajun He, Zhihua Wang, Hanjun Jiang","doi":"10.1109/EDSSC.2017.8126505","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126505","url":null,"abstract":"A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of 6.1 ps after a 17 dB loss channel at 60Gb/s.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126297300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126553
D. Lin, I. Tang, Jia-Chyi Wu, Jiangang Zeng
This paper investigates the design of a compact monopole LTE three-dimension (3D) antenna. LTE operational bandwidth is indispensable while a 3D antenna is used to make 4G mobile phone applicable. The gaps between handset housing and circuit board will be used to design an antenna suitable in the confined space. To simplify the design, a common plane waveguide needs to be fed by the antenna. The advantage is that it is easy to shape the antenna only using the single layer of metal media board and also simple to make circuit board in the future. The main design of the antenna structure is to apply multipath monopole antennas to resonate the low frequency and high frequency bands. Then we can extend the high-frequency bandwidth of LTE by a 3D metal coupling section. For spreading the bandwidth, we need to use the coupling rod to get better match of impedance. Simulation and test measurements of the 3D antenna design are also studied.
{"title":"Design and analysis of LTE 3D antennas","authors":"D. Lin, I. Tang, Jia-Chyi Wu, Jiangang Zeng","doi":"10.1109/EDSSC.2017.8126553","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126553","url":null,"abstract":"This paper investigates the design of a compact monopole LTE three-dimension (3D) antenna. LTE operational bandwidth is indispensable while a 3D antenna is used to make 4G mobile phone applicable. The gaps between handset housing and circuit board will be used to design an antenna suitable in the confined space. To simplify the design, a common plane waveguide needs to be fed by the antenna. The advantage is that it is easy to shape the antenna only using the single layer of metal media board and also simple to make circuit board in the future. The main design of the antenna structure is to apply multipath monopole antennas to resonate the low frequency and high frequency bands. Then we can extend the high-frequency bandwidth of LTE by a 3D metal coupling section. For spreading the bandwidth, we need to use the coupling rod to get better match of impedance. Simulation and test measurements of the 3D antenna design are also studied.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129224125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8355949
Chunwei Zhang, Yang Li, Xiaoqian Fu, Zhiming Li
In this paper, the total harmonic distortion (THD) of the critical mode power factor correction (PFC) converter with constant on-time is analyzed. Our analyses find that the high THD mainly comes from the high current distortion at low input voltage condition. To solve the problem, a novel partially variable on-time boost PFC converter is proposed. For the proposed PFC converter, the on-time is enhanced when the input voltage is smaller than half output voltage, so as to alleviate the distortion of input current. The experimental results show that the novel PFC converter achieve small THD (≪10%) and high power factor (≫0.99) at different input voltages, which are greatly improved compare with the traditional PFC.
{"title":"A novel partially variable on-time critical mode boost PFC converter","authors":"Chunwei Zhang, Yang Li, Xiaoqian Fu, Zhiming Li","doi":"10.1109/EDSSC.2017.8355949","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8355949","url":null,"abstract":"In this paper, the total harmonic distortion (THD) of the critical mode power factor correction (PFC) converter with constant on-time is analyzed. Our analyses find that the high THD mainly comes from the high current distortion at low input voltage condition. To solve the problem, a novel partially variable on-time boost PFC converter is proposed. For the proposed PFC converter, the on-time is enhanced when the input voltage is smaller than half output voltage, so as to alleviate the distortion of input current. The experimental results show that the novel PFC converter achieve small THD (≪10%) and high power factor (≫0.99) at different input voltages, which are greatly improved compare with the traditional PFC.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129308332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126484
Yu-Cheng Lin, Pei-Hsuan Hsu, Song-Nien Tang
Many semiconductor industries gradually tend to transit from the complex 2D design to a high regularity of 1D gridded design. In this transition process, cut distribution position has become the most important challenge. For more advanced nanometer designs, cuts may be too dense to be printed by 193i lithography. While Directed Self-Assembly (DSA) is outstanding in recent years, it is a great potential option. In this paper, we discuss how to pick the appropriate DSA patterns to make cuts and produce 1D gridded design as the original circuit with the same function. With the assignment of different guiding template, DSA pattern shape and size will follow the assignment. In our experiments, simulated annealing algorithm is applied to pick patterns for the conflict number minimization.
{"title":"Guiding template assignment using DSA for cut redistribution of 1d layout","authors":"Yu-Cheng Lin, Pei-Hsuan Hsu, Song-Nien Tang","doi":"10.1109/EDSSC.2017.8126484","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126484","url":null,"abstract":"Many semiconductor industries gradually tend to transit from the complex 2D design to a high regularity of 1D gridded design. In this transition process, cut distribution position has become the most important challenge. For more advanced nanometer designs, cuts may be too dense to be printed by 193i lithography. While Directed Self-Assembly (DSA) is outstanding in recent years, it is a great potential option. In this paper, we discuss how to pick the appropriate DSA patterns to make cuts and produce 1D gridded design as the original circuit with the same function. With the assignment of different guiding template, DSA pattern shape and size will follow the assignment. In our experiments, simulated annealing algorithm is applied to pick patterns for the conflict number minimization.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126487
Shun-Cheng Yang, Cheng-Jia Dai, Li-Cheng Chang, C. Wu
In this work, we demonstrate a way to modulate threshold voltage of InGaAs Fin-structured High-electron-mobility transistors (Fin-HEMTs) by narrowing fin width of the devices. Normally-off InGaAs FinHEMT has been successfully achieved when fin width of devices is smaller than around 180 nm. Also, we introduce a theory to explain side wall gates control of FinHEMTs to modulate threshold voltage.
{"title":"Modulate threshold voltage to achieve enhancement mode fin-structured InGaAs high electron mobility transistors (fin-HEMTs) through narrowing fin structure's width","authors":"Shun-Cheng Yang, Cheng-Jia Dai, Li-Cheng Chang, C. Wu","doi":"10.1109/EDSSC.2017.8126487","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126487","url":null,"abstract":"In this work, we demonstrate a way to modulate threshold voltage of InGaAs Fin-structured High-electron-mobility transistors (Fin-HEMTs) by narrowing fin width of the devices. Normally-off InGaAs FinHEMT has been successfully achieved when fin width of devices is smaller than around 180 nm. Also, we introduce a theory to explain side wall gates control of FinHEMTs to modulate threshold voltage.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122969879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126550
Dengjie Wang, Fangxu Lv, Yajun He, Ziqiang Wang, Hong Chen
This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show that the total jitter of the recovered clock is 4.7ps when the CDR locked at 28 Gb/s. In addition, this CDR can track a 500 KHz sinusoidal phase jitter with 2UI amplitude.
{"title":"A 28Gbps reference-less VCO based CDR with separate proportional path technology in 65nm CMOS","authors":"Dengjie Wang, Fangxu Lv, Yajun He, Ziqiang Wang, Hong Chen","doi":"10.1109/EDSSC.2017.8126550","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126550","url":null,"abstract":"This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show that the total jitter of the recovered clock is 4.7ps when the CDR locked at 28 Gb/s. In addition, this CDR can track a 500 KHz sinusoidal phase jitter with 2UI amplitude.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123437890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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