Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
{"title":"Design of hybrid memristor-MOS XOR and XNOR logic gates","authors":"Xiaoyan Xu, Xiaole Cui, M. Luo, Qiujun Lin, Yichi Luo, Yufeng Zhou","doi":"10.1109/EDSSC.2017.8126414","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126414","url":null,"abstract":"Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115169536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126486
Ruping Xiao, Mingzhong Li, M. Law, Pui-in Mak, R. P. Martin
We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63% positive prediction (Pr) using the MIT-BIH Arrhythmia database. A chip prototype is also implemented in a standard 0.18-μm CMOS process. Synthesized with a customized subthreshold digital library for minimum energy operation, the proposed QRS detector occupies an active area of 0.13 mm2 and consumes merely 93nW.
{"title":"Ultra-low power QRS detection using adaptive thresholding based on forward search interval technique","authors":"Ruping Xiao, Mingzhong Li, M. Law, Pui-in Mak, R. P. Martin","doi":"10.1109/EDSSC.2017.8126486","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126486","url":null,"abstract":"We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63% positive prediction (Pr) using the MIT-BIH Arrhythmia database. A chip prototype is also implemented in a standard 0.18-μm CMOS process. Synthesized with a customized subthreshold digital library for minimum energy operation, the proposed QRS detector occupies an active area of 0.13 mm2 and consumes merely 93nW.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126504
Y. Liu, Bing Li
Real-time lossless compression can reduce the burden of big data transmission and storage. Hardware compression is faster and more energy saving when compared with software. This paper proposes a novel LZO hardware architecture and various acceleration methods, integrates the compressor module and other IP modules. Finally, test and demonstration are provided on the DE2 development board. The results show that the compression speed increases by about 5 times and compression ratio increases by about 1.4% when compared to software implementation.
{"title":"Implementation of LZO real-time lossless compression on FPGA","authors":"Y. Liu, Bing Li","doi":"10.1109/EDSSC.2017.8126504","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126504","url":null,"abstract":"Real-time lossless compression can reduce the burden of big data transmission and storage. Hardware compression is faster and more energy saving when compared with software. This paper proposes a novel LZO hardware architecture and various acceleration methods, integrates the compressor module and other IP modules. Finally, test and demonstration are provided on the DE2 development board. The results show that the compression speed increases by about 5 times and compression ratio increases by about 1.4% when compared to software implementation.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125613358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8355947
Yang-Hua Chang, Chien-min Wang
In this study, the characteristics of a double-channel AlGaN/GaN HEMT are improved. Firstly, depletion mode is changed to enhancement mode by changing the thickness of an AlGaN layer, implementing a p-doped region, and changing the material of buffer layer. Secondly, Al ratio in the upper AlGaN layer is optimized to improve the flatness of Gm-VGS curve so that the linearity is improved. Finally, breakdown voltage is increased by using a double-gate structure.
{"title":"Improving breakdown voltage of double-channel E-mode AlGaN/GaN HEMTs using a double-gate structure","authors":"Yang-Hua Chang, Chien-min Wang","doi":"10.1109/EDSSC.2017.8355947","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8355947","url":null,"abstract":"In this study, the characteristics of a double-channel AlGaN/GaN HEMT are improved. Firstly, depletion mode is changed to enhancement mode by changing the thickness of an AlGaN layer, implementing a p-doped region, and changing the material of buffer layer. Secondly, Al ratio in the upper AlGaN layer is optimized to improve the flatness of Gm-VGS curve so that the linearity is improved. Finally, breakdown voltage is increased by using a double-gate structure.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132229805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126527
Qihang Jiang, Shuguo Li
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.
{"title":"A design of manually optimized (15, 4) parallel counter","authors":"Qihang Jiang, Shuguo Li","doi":"10.1109/EDSSC.2017.8126527","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126527","url":null,"abstract":"This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114753288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126479
Guiheng Zhang, Wei Zhang, Jun Fu, Zhuang Li
This paper presents a 2-input and 3-output 0.35–1.5GHz switch cell with active balun. The proposed differential switch cell is composed of 8 differential series-shunt-series switches which improve the transmit efficiency of switch cell. Two wideband active baluns are used to compensate for the loss of passive switch cell which almost consumes no DC power. Fabricated by 0.18μm SiGe BiCMOS technology, the switch cell shows highest insertion gain of 9 dB and more than 40 dB isolation in working frequency band.
{"title":"Design of 0.35–1.5GHz 2-input 3-output SiGe switch cell with active balun","authors":"Guiheng Zhang, Wei Zhang, Jun Fu, Zhuang Li","doi":"10.1109/EDSSC.2017.8126479","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126479","url":null,"abstract":"This paper presents a 2-input and 3-output 0.35–1.5GHz switch cell with active balun. The proposed differential switch cell is composed of 8 differential series-shunt-series switches which improve the transmit efficiency of switch cell. Two wideband active baluns are used to compensate for the loss of passive switch cell which almost consumes no DC power. Fabricated by 0.18μm SiGe BiCMOS technology, the switch cell shows highest insertion gain of 9 dB and more than 40 dB isolation in working frequency band.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126433
Xiaoyong He, Te-pei Lu, Zhaoxia Jing
This paper presents a design of command queuing engine in eMMC5.1 host system. With the proposed engine, multiple commands can be collected and executed in order of priority instead of executed as they arrive. The proposed engine helps reducing latency on small data transfers so that performance in multitasking scenarios is improved. This design is verified by simulation for various requests and the synthesis results show that it can work at the frequency up to 424 MHz based on 0.13μm CMOS technology.
{"title":"Design of command queuing engine in eMMC5.1 host system","authors":"Xiaoyong He, Te-pei Lu, Zhaoxia Jing","doi":"10.1109/EDSSC.2017.8126433","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126433","url":null,"abstract":"This paper presents a design of command queuing engine in eMMC5.1 host system. With the proposed engine, multiple commands can be collected and executed in order of priority instead of executed as they arrive. The proposed engine helps reducing latency on small data transfers so that performance in multitasking scenarios is improved. This design is verified by simulation for various requests and the synthesis results show that it can work at the frequency up to 424 MHz based on 0.13μm CMOS technology.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126435
Liu Ji-zhi, Li Zhiwei, Hou Fei
In this letter, a diode trigger silicon-controlled rectifier (DTSCR) with small diode width is proposed for Electrostatic discharge (ESD) protection of the low-voltage integrated circuits. The trigger voltage of DTSCR is adjusted by the width of the diodes which are used to trigger on the SCR device. Experimental data show the trigger voltage increases with decreasing the area of the diodes. The trigger voltage of the DTSCR with small diode width can increase 0.75V compared to that with large diode width. This method can increase the trigger voltage of the DTSCR with reducing the chip area.
{"title":"A diode-triggered silicon-controlled rectifier with small diode width for electrostatic discharge applications","authors":"Liu Ji-zhi, Li Zhiwei, Hou Fei","doi":"10.1109/EDSSC.2017.8126435","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126435","url":null,"abstract":"In this letter, a diode trigger silicon-controlled rectifier (DTSCR) with small diode width is proposed for Electrostatic discharge (ESD) protection of the low-voltage integrated circuits. The trigger voltage of DTSCR is adjusted by the width of the diodes which are used to trigger on the SCR device. Experimental data show the trigger voltage increases with decreasing the area of the diodes. The trigger voltage of the DTSCR with small diode width can increase 0.75V compared to that with large diode width. This method can increase the trigger voltage of the DTSCR with reducing the chip area.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115305887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Various thicknesses (0, 5 and 70 nm) TiO2:Nb (TNO) films are used for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with Mo/TNO source-drain (S-D) electrodes. All the as-prepared TFTs show similar electrical performance. However, the on-current of a-IGZO TFT with Mo/TNO(5 nm) S-D electrodes decreases dramatically after 300 °C annealing due to the large S-D parasitic resistance. In contrast, the S-D contact remain low for Mo/TNO(70 nm) S-D electrodes by 300 °C annealing.
{"title":"TiO2:Nb film thickness influences on the amorphous InGaZnO thin film transistors with Mo/TiO2:Nb source-drain electrodes","authors":"Q.P. Lin, Bao-zhu Chang, Letao Zhang, Xiaoliang Zhou, Hongyu He, Shengdong Zhang","doi":"10.1109/EDSSC.2017.8126430","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126430","url":null,"abstract":"Various thicknesses (0, 5 and 70 nm) TiO2:Nb (TNO) films are used for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with Mo/TNO source-drain (S-D) electrodes. All the as-prepared TFTs show similar electrical performance. However, the on-current of a-IGZO TFT with Mo/TNO(5 nm) S-D electrodes decreases dramatically after 300 °C annealing due to the large S-D parasitic resistance. In contrast, the S-D contact remain low for Mo/TNO(70 nm) S-D electrodes by 300 °C annealing.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126421
Yang Da-xiang, Li Debajit Basak, K. Pun
A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
{"title":"Reduction of clock jitter effect in 1-bit CT delta-sigma modulators by correlated clocks","authors":"Yang Da-xiang, Li Debajit Basak, K. Pun","doi":"10.1109/EDSSC.2017.8126421","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126421","url":null,"abstract":"A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123264594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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