Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
{"title":"Design of hybrid memristor-MOS XOR and XNOR logic gates","authors":"Xiaoyan Xu, Xiaole Cui, M. Luo, Qiujun Lin, Yichi Luo, Yufeng Zhou","doi":"10.1109/EDSSC.2017.8126414","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126414","url":null,"abstract":"Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115169536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126486
Ruping Xiao, Mingzhong Li, M. Law, Pui-in Mak, R. P. Martin
We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63% positive prediction (Pr) using the MIT-BIH Arrhythmia database. A chip prototype is also implemented in a standard 0.18-μm CMOS process. Synthesized with a customized subthreshold digital library for minimum energy operation, the proposed QRS detector occupies an active area of 0.13 mm2 and consumes merely 93nW.
{"title":"Ultra-low power QRS detection using adaptive thresholding based on forward search interval technique","authors":"Ruping Xiao, Mingzhong Li, M. Law, Pui-in Mak, R. P. Martin","doi":"10.1109/EDSSC.2017.8126486","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126486","url":null,"abstract":"We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63% positive prediction (Pr) using the MIT-BIH Arrhythmia database. A chip prototype is also implemented in a standard 0.18-μm CMOS process. Synthesized with a customized subthreshold digital library for minimum energy operation, the proposed QRS detector occupies an active area of 0.13 mm2 and consumes merely 93nW.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126527
Qihang Jiang, Shuguo Li
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.
{"title":"A design of manually optimized (15, 4) parallel counter","authors":"Qihang Jiang, Shuguo Li","doi":"10.1109/EDSSC.2017.8126527","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126527","url":null,"abstract":"This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114753288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126435
Liu Ji-zhi, Li Zhiwei, Hou Fei
In this letter, a diode trigger silicon-controlled rectifier (DTSCR) with small diode width is proposed for Electrostatic discharge (ESD) protection of the low-voltage integrated circuits. The trigger voltage of DTSCR is adjusted by the width of the diodes which are used to trigger on the SCR device. Experimental data show the trigger voltage increases with decreasing the area of the diodes. The trigger voltage of the DTSCR with small diode width can increase 0.75V compared to that with large diode width. This method can increase the trigger voltage of the DTSCR with reducing the chip area.
{"title":"A diode-triggered silicon-controlled rectifier with small diode width for electrostatic discharge applications","authors":"Liu Ji-zhi, Li Zhiwei, Hou Fei","doi":"10.1109/EDSSC.2017.8126435","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126435","url":null,"abstract":"In this letter, a diode trigger silicon-controlled rectifier (DTSCR) with small diode width is proposed for Electrostatic discharge (ESD) protection of the low-voltage integrated circuits. The trigger voltage of DTSCR is adjusted by the width of the diodes which are used to trigger on the SCR device. Experimental data show the trigger voltage increases with decreasing the area of the diodes. The trigger voltage of the DTSCR with small diode width can increase 0.75V compared to that with large diode width. This method can increase the trigger voltage of the DTSCR with reducing the chip area.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115305887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126479
Guiheng Zhang, Wei Zhang, Jun Fu, Zhuang Li
This paper presents a 2-input and 3-output 0.35–1.5GHz switch cell with active balun. The proposed differential switch cell is composed of 8 differential series-shunt-series switches which improve the transmit efficiency of switch cell. Two wideband active baluns are used to compensate for the loss of passive switch cell which almost consumes no DC power. Fabricated by 0.18μm SiGe BiCMOS technology, the switch cell shows highest insertion gain of 9 dB and more than 40 dB isolation in working frequency band.
{"title":"Design of 0.35–1.5GHz 2-input 3-output SiGe switch cell with active balun","authors":"Guiheng Zhang, Wei Zhang, Jun Fu, Zhuang Li","doi":"10.1109/EDSSC.2017.8126479","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126479","url":null,"abstract":"This paper presents a 2-input and 3-output 0.35–1.5GHz switch cell with active balun. The proposed differential switch cell is composed of 8 differential series-shunt-series switches which improve the transmit efficiency of switch cell. Two wideband active baluns are used to compensate for the loss of passive switch cell which almost consumes no DC power. Fabricated by 0.18μm SiGe BiCMOS technology, the switch cell shows highest insertion gain of 9 dB and more than 40 dB isolation in working frequency band.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126461
L. Shijun, Zou Xuecheng, Wang Baocun
3D QLC (Quad-Level-Cell) NAND technology with 16 voltage levels per cell will be one of the next generation memory technologies after 3D TLC (Triple Level Cell) NAND flash succeeded. Besides, program algorithm for 16 voltage levels is studied in this paper, the important read algorithms are investigated because the data errors of QLC device will be easily generated due to power loss, program distribute, etc. The read method with offset and soft message generation for Low Density Parity Check (LDPC) Belief Propagation (BP) soft-decision decoding are presented.
{"title":"Program and read methods with offset in quad-level-cell NAND design","authors":"L. Shijun, Zou Xuecheng, Wang Baocun","doi":"10.1109/EDSSC.2017.8126461","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126461","url":null,"abstract":"3D QLC (Quad-Level-Cell) NAND technology with 16 voltage levels per cell will be one of the next generation memory technologies after 3D TLC (Triple Level Cell) NAND flash succeeded. Besides, program algorithm for 16 voltage levels is studied in this paper, the important read algorithms are investigated because the data errors of QLC device will be easily generated due to power loss, program distribute, etc. The read method with offset and soft message generation for Low Density Parity Check (LDPC) Belief Propagation (BP) soft-decision decoding are presented.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123360696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126421
Yang Da-xiang, Li Debajit Basak, K. Pun
A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
{"title":"Reduction of clock jitter effect in 1-bit CT delta-sigma modulators by correlated clocks","authors":"Yang Da-xiang, Li Debajit Basak, K. Pun","doi":"10.1109/EDSSC.2017.8126421","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126421","url":null,"abstract":"A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123264594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126474
S. Zhang, B. Gao, Dong Wu, Huaqiang Wu, H. Qian
FinFET variability, which is a small amplitude deviation caused by process, cannot be ignored with the scaling of CMOS. This work utilizes the variability as the random source of SRAM Physical Unclonable function (PUF). The impact of the variation has been simulated from device-level to circuit-level. Further research has been done with its influence on SRAM static noise margin (SNM) and SRAM PUF reliability, and the trade-off relation between them.
{"title":"Evaluation and optimization of physical unclonable function (PUF) based on the variability of FinFET SRAM","authors":"S. Zhang, B. Gao, Dong Wu, Huaqiang Wu, H. Qian","doi":"10.1109/EDSSC.2017.8126474","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126474","url":null,"abstract":"FinFET variability, which is a small amplitude deviation caused by process, cannot be ignored with the scaling of CMOS. This work utilizes the variability as the random source of SRAM Physical Unclonable function (PUF). The impact of the variation has been simulated from device-level to circuit-level. Further research has been done with its influence on SRAM static noise margin (SNM) and SRAM PUF reliability, and the trade-off relation between them.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125089420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126520
Seung-Geun Jung, Hyun‐Yong Yu
In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10−4 A/um and contact resistivity of 3 × 10−9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.
{"title":"Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure","authors":"Seung-Geun Jung, Hyun‐Yong Yu","doi":"10.1109/EDSSC.2017.8126520","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126520","url":null,"abstract":"In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10−4 A/um and contact resistivity of 3 × 10−9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130913117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126418
Yung-Hui Chung, Hua-Wei Tseng
This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and SFDR are 52.3 and 71 dB, respectively. Measured ENOB is 8.4 bits, equivalent to a FoM of 191 fJ/conversion-step.
{"title":"A 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in 180nm CMOS","authors":"Yung-Hui Chung, Hua-Wei Tseng","doi":"10.1109/EDSSC.2017.8126418","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126418","url":null,"abstract":"This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and SFDR are 52.3 and 71 dB, respectively. Measured ENOB is 8.4 bits, equivalent to a FoM of 191 fJ/conversion-step.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131290520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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