Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126489
Lixia Zheng, Guangchao Zhang, Jin Wu, Huan Hu, Weifeng Sun
An innovative active-quenching circuit for single photon avalanche diode is presented. A differential amplification circuit based on offset control scheme is adopted to realize rapid avalanche signal discrimination. In order to save the die area, a voltage-controlled transistor acting as a sensing resistance is used. Compared with other traditional circuits, the proposed circuit does not need reference voltage and can realize low threshold voltage comparison. Therefore, it preserves the advantages of compact area and rapid detection, which can be applied in array situation.
{"title":"Compact and rapid detection quenching circuit for SPAD arrays","authors":"Lixia Zheng, Guangchao Zhang, Jin Wu, Huan Hu, Weifeng Sun","doi":"10.1109/EDSSC.2017.8126489","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126489","url":null,"abstract":"An innovative active-quenching circuit for single photon avalanche diode is presented. A differential amplification circuit based on offset control scheme is adopted to realize rapid avalanche signal discrimination. In order to save the die area, a voltage-controlled transistor acting as a sensing resistance is used. Compared with other traditional circuits, the proposed circuit does not need reference voltage and can realize low threshold voltage comparison. Therefore, it preserves the advantages of compact area and rapid detection, which can be applied in array situation.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126433
Xiaoyong He, Te-pei Lu, Zhaoxia Jing
This paper presents a design of command queuing engine in eMMC5.1 host system. With the proposed engine, multiple commands can be collected and executed in order of priority instead of executed as they arrive. The proposed engine helps reducing latency on small data transfers so that performance in multitasking scenarios is improved. This design is verified by simulation for various requests and the synthesis results show that it can work at the frequency up to 424 MHz based on 0.13μm CMOS technology.
{"title":"Design of command queuing engine in eMMC5.1 host system","authors":"Xiaoyong He, Te-pei Lu, Zhaoxia Jing","doi":"10.1109/EDSSC.2017.8126433","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126433","url":null,"abstract":"This paper presents a design of command queuing engine in eMMC5.1 host system. With the proposed engine, multiple commands can be collected and executed in order of priority instead of executed as they arrive. The proposed engine helps reducing latency on small data transfers so that performance in multitasking scenarios is improved. This design is verified by simulation for various requests and the synthesis results show that it can work at the frequency up to 424 MHz based on 0.13μm CMOS technology.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126556
Xiaoyang Cao, Milin Zhang, Chun Zhang
This paper proposed the architecture of a linear current-mode CMOS image sensor integrated parallel processing unit enabling various block-level calculation during the read-out procedure. Combinational logic with two scanning DFF chains and global control signals as input generates the output to address the right pixels with high flexibility. Four current conveyors are used to perform CDS function for the chosen pixels. Four digitally programmable scaling units and a TIA based arithmetic unit are integrated for the proposed computation procedure. The 240×200 image sensor was fabricated in 0.18um standard 4T CIS technology with a pixel size of 9um×9um and a fill factor of 30%. One computation operation can be done within 3us with a power consumption of 309uW in average for analog circuits.
{"title":"Design of a high flexible block-based computational CMOS image sensor","authors":"Xiaoyang Cao, Milin Zhang, Chun Zhang","doi":"10.1109/EDSSC.2017.8126556","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126556","url":null,"abstract":"This paper proposed the architecture of a linear current-mode CMOS image sensor integrated parallel processing unit enabling various block-level calculation during the read-out procedure. Combinational logic with two scanning DFF chains and global control signals as input generates the output to address the right pixels with high flexibility. Four current conveyors are used to perform CDS function for the chosen pixels. Four digitally programmable scaling units and a TIA based arithmetic unit are integrated for the proposed computation procedure. The 240×200 image sensor was fabricated in 0.18um standard 4T CIS technology with a pixel size of 9um×9um and a fill factor of 30%. One computation operation can be done within 3us with a power consumption of 309uW in average for analog circuits.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Various thicknesses (0, 5 and 70 nm) TiO2:Nb (TNO) films are used for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with Mo/TNO source-drain (S-D) electrodes. All the as-prepared TFTs show similar electrical performance. However, the on-current of a-IGZO TFT with Mo/TNO(5 nm) S-D electrodes decreases dramatically after 300 °C annealing due to the large S-D parasitic resistance. In contrast, the S-D contact remain low for Mo/TNO(70 nm) S-D electrodes by 300 °C annealing.
{"title":"TiO2:Nb film thickness influences on the amorphous InGaZnO thin film transistors with Mo/TiO2:Nb source-drain electrodes","authors":"Q.P. Lin, Bao-zhu Chang, Letao Zhang, Xiaoliang Zhou, Hongyu He, Shengdong Zhang","doi":"10.1109/EDSSC.2017.8126430","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126430","url":null,"abstract":"Various thicknesses (0, 5 and 70 nm) TiO2:Nb (TNO) films are used for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with Mo/TNO source-drain (S-D) electrodes. All the as-prepared TFTs show similar electrical performance. However, the on-current of a-IGZO TFT with Mo/TNO(5 nm) S-D electrodes decreases dramatically after 300 °C annealing due to the large S-D parasitic resistance. In contrast, the S-D contact remain low for Mo/TNO(70 nm) S-D electrodes by 300 °C annealing.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126503
I. Tseng, Hao-Yu Lan, C. Wu
The electrical and optical characteristics of the three port InGaN/GaN blue quantum-well heterojunction bipolar light-emitting transistors (QW HBLETs) on sapphire substrate are reported. The base-emitter (BE) light-emitting diode and base-collector (BC) diode are demonstrated. Next, the Gummel-poon plot is measured. Moreover, the collector current-voltage (I-V) and light-current-voltage (LI-V) characteristics demonstrate that the InGaN/GaN blue QW HBLETs are unique devices with dual output and have potential in the application of visible light communication (VLC).
{"title":"Characterization of blue InGaN/GaN quantum-well heterojunction bipolar light emitting transistors","authors":"I. Tseng, Hao-Yu Lan, C. Wu","doi":"10.1109/EDSSC.2017.8126503","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126503","url":null,"abstract":"The electrical and optical characteristics of the three port InGaN/GaN blue quantum-well heterojunction bipolar light-emitting transistors (QW HBLETs) on sapphire substrate are reported. The base-emitter (BE) light-emitting diode and base-collector (BC) diode are demonstrated. Next, the Gummel-poon plot is measured. Moreover, the collector current-voltage (I-V) and light-current-voltage (LI-V) characteristics demonstrate that the InGaN/GaN blue QW HBLETs are unique devices with dual output and have potential in the application of visible light communication (VLC).","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126655129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126531
G. Agrawal, S. Aniruddhan
Achieving large low-frequency gain together with low noise and a high unity-gain bandwidth (UGB) imposes conflicting requirement on bias currents in single stage operational transconductance amplifiers (OTA). In this work, we propose a modified biasing scheme for folded cascode OTAs to de-couple the gain versus noise/UGB trade-off. The effectiveness of proposed biasing scheme is illustrated with the aid of an ultra-low noise OTA design achieving 350 pV / √Hz along with 70 dB DC gain in 130nm CMOS process while consuming roughly half the bias current as compared to conventional biasing scheme.
实现大低频增益、低噪声和高单位增益带宽(UGB)对单级运算跨导放大器(OTA)的偏置电流提出了相互矛盾的要求。在这项工作中，我们为折叠级联码ota提出了一种改进的偏置方案，以消除增益与噪声/UGB权衡的耦合。通过超低噪声OTA设计，在130nm CMOS工艺中实现350 pV /√Hz和70 dB DC增益，同时消耗的偏置电流约为传统偏置方案的一半，从而说明了所提出偏置方案的有效性。
{"title":"A modified bias scheme for high-gain low-noise folded cascode OTAs","authors":"G. Agrawal, S. Aniruddhan","doi":"10.1109/EDSSC.2017.8126531","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126531","url":null,"abstract":"Achieving large low-frequency gain together with low noise and a high unity-gain bandwidth (UGB) imposes conflicting requirement on bias currents in single stage operational transconductance amplifiers (OTA). In this work, we propose a modified biasing scheme for folded cascode OTAs to de-couple the gain versus noise/UGB trade-off. The effectiveness of proposed biasing scheme is illustrated with the aid of an ultra-low noise OTA design achieving 350 pV / √Hz along with 70 dB DC gain in 130nm CMOS process while consuming roughly half the bias current as compared to conventional biasing scheme.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126094005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8355947
Yang-Hua Chang, Chien-min Wang
In this study, the characteristics of a double-channel AlGaN/GaN HEMT are improved. Firstly, depletion mode is changed to enhancement mode by changing the thickness of an AlGaN layer, implementing a p-doped region, and changing the material of buffer layer. Secondly, Al ratio in the upper AlGaN layer is optimized to improve the flatness of Gm-VGS curve so that the linearity is improved. Finally, breakdown voltage is increased by using a double-gate structure.
{"title":"Improving breakdown voltage of double-channel E-mode AlGaN/GaN HEMTs using a double-gate structure","authors":"Yang-Hua Chang, Chien-min Wang","doi":"10.1109/EDSSC.2017.8355947","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8355947","url":null,"abstract":"In this study, the characteristics of a double-channel AlGaN/GaN HEMT are improved. Firstly, depletion mode is changed to enhancement mode by changing the thickness of an AlGaN layer, implementing a p-doped region, and changing the material of buffer layer. Secondly, Al ratio in the upper AlGaN layer is optimized to improve the flatness of Gm-VGS curve so that the linearity is improved. Finally, breakdown voltage is increased by using a double-gate structure.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132229805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126504
Y. Liu, Bing Li
Real-time lossless compression can reduce the burden of big data transmission and storage. Hardware compression is faster and more energy saving when compared with software. This paper proposes a novel LZO hardware architecture and various acceleration methods, integrates the compressor module and other IP modules. Finally, test and demonstration are provided on the DE2 development board. The results show that the compression speed increases by about 5 times and compression ratio increases by about 1.4% when compared to software implementation.
{"title":"Implementation of LZO real-time lossless compression on FPGA","authors":"Y. Liu, Bing Li","doi":"10.1109/EDSSC.2017.8126504","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126504","url":null,"abstract":"Real-time lossless compression can reduce the burden of big data transmission and storage. Hardware compression is faster and more energy saving when compared with software. This paper proposes a novel LZO hardware architecture and various acceleration methods, integrates the compressor module and other IP modules. Finally, test and demonstration are provided on the DE2 development board. The results show that the compression speed increases by about 5 times and compression ratio increases by about 1.4% when compared to software implementation.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125613358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126467
Ruirui Liu, Shuguo Li
Toom-Cook algorithm is a well-known method to compute large integer multiplication. In this paper, we propose an implementation of 272 bit multiplier based on Toom-Cook algorithm and finish the hardware implementation. Sythesizing with Synopsys Design Compiler in the SMIC 65nm CMOS process, the result shows that the design based on Toom-Cook can acheive at least 22.9% less on area and 43.4% less on power than the instance of Designware of synthesis tool.
{"title":"A low area ASIC implementation of 272 bit multiplier","authors":"Ruirui Liu, Shuguo Li","doi":"10.1109/EDSSC.2017.8126467","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126467","url":null,"abstract":"Toom-Cook algorithm is a well-known method to compute large integer multiplication. In this paper, we propose an implementation of 272 bit multiplier based on Toom-Cook algorithm and finish the hardware implementation. Sythesizing with Synopsys Design Compiler in the SMIC 65nm CMOS process, the result shows that the design based on Toom-Cook can acheive at least 22.9% less on area and 43.4% less on power than the instance of Designware of synthesis tool.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114072776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A power-on-reset (POR) circuit, which is an important block in mixed-signal integrated circuits, is used for the correct initialization of critical logic states in digital blocks of mixed-signal circuits. A POR circuit with precisely triggered threshold voltages is proposed. The circuit is designed in a 0.18 μm CMOS technology with a maximum 4 μA quiescent current. The output signal of the proposed circuit is also used to precisely detect whether the power supply is power-on or brown-out. The proposed POR circuit is insensitive to the power ramping time and tolerant to process variations. At typical corner, the proposed circuit reduces the quiescent current by more than 10x and layout area by 38% compared to the previously published designs.
POR (power-on-reset)电路是混合信号集成电路中的一个重要模块，用于正确初始化混合信号电路的数字模块中的关键逻辑状态。提出了一种具有精确触发阈值电压的POR电路。电路采用0.18 μm CMOS工艺设计，最大静态电流为4 μA。该电路的输出信号还用于精确检测电源是否上电或断电。所提出的POR电路对功率斜坡时间不敏感，并能容忍工艺变化。在典型的拐角处，与先前发表的设计相比，所提出的电路将静态电流减少了10倍以上，布局面积减少了38%。
{"title":"A power-on-reset circuit with precisely triggered threshold voltages","authors":"Ruibin Xie, Qiang Zhao, Y. Ma, Fengbo Xie, Feng Lin, Shengdong Zhang","doi":"10.1109/EDSSC.2017.8126498","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126498","url":null,"abstract":"A power-on-reset (POR) circuit, which is an important block in mixed-signal integrated circuits, is used for the correct initialization of critical logic states in digital blocks of mixed-signal circuits. A POR circuit with precisely triggered threshold voltages is proposed. The circuit is designed in a 0.18 μm CMOS technology with a maximum 4 μA quiescent current. The output signal of the proposed circuit is also used to precisely detect whether the power supply is power-on or brown-out. The proposed POR circuit is insensitive to the power ramping time and tolerant to process variations. At typical corner, the proposed circuit reduces the quiescent current by more than 10x and layout area by 38% compared to the previously published designs.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122950529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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