Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126411
G. Su, Li-heng Lou, Lingling Sun, Jun Liu, J. Wen, Xiangyu Lv
A five-stage 93.9 GHz-105.6 GHz common-source CMOS amplifier is presented in this paper. The customized on-chip inductor and transmission line (TL) are designed for matching networks. Fabricated in a 65nm bulk CMOS process, this amplifier achieves a peak gain of 9 dB at 100 GHz and 11.7GHz 3-dB bandwidth range from 93.9 GHz to 105.6 GHz, consuming total power of 49.2 mW under 1.2 V voltage supply. The area of this amplifier is 0.5mm2 including pads.
{"title":"A 93.9–105.6 GHz amplifier using customized on-chip inductor","authors":"G. Su, Li-heng Lou, Lingling Sun, Jun Liu, J. Wen, Xiangyu Lv","doi":"10.1109/EDSSC.2017.8126411","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126411","url":null,"abstract":"A five-stage 93.9 GHz-105.6 GHz common-source CMOS amplifier is presented in this paper. The customized on-chip inductor and transmission line (TL) are designed for matching networks. Fabricated in a 65nm bulk CMOS process, this amplifier achieves a peak gain of 9 dB at 100 GHz and 11.7GHz 3-dB bandwidth range from 93.9 GHz to 105.6 GHz, consuming total power of 49.2 mW under 1.2 V voltage supply. The area of this amplifier is 0.5mm2 including pads.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133610742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126526
S. Teja, Mandar S. Bhoir, N. Mohapatra
Conventional Extended gate STI based LDMOS devices often have an overlap between gate and STI resulting in higher impact ionization at the STI left edge. In this work, we have proposed and analyzed a novel split gate architecture to reduce impact ionization and improve off-state breakdown voltage. The underlying physics behind the improved characteristics of the proposed architecture is explained using detailed TCAD simulations. Finally, necessary design guidelines are provided for proper optimization of the split gate architecture.
{"title":"Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors","authors":"S. Teja, Mandar S. Bhoir, N. Mohapatra","doi":"10.1109/EDSSC.2017.8126526","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126526","url":null,"abstract":"Conventional Extended gate STI based LDMOS devices often have an overlap between gate and STI resulting in higher impact ionization at the STI left edge. In this work, we have proposed and analyzed a novel split gate architecture to reduce impact ionization and improve off-state breakdown voltage. The underlying physics behind the improved characteristics of the proposed architecture is explained using detailed TCAD simulations. Finally, necessary design guidelines are provided for proper optimization of the split gate architecture.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127837272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126465
Tuo Xie, H. Hu, Chaoxiang Yang, Chun Zhang, Zhihua Wang
IEEE 802.11b WLAN is widely used to implement Wi-Fi based Time Difference of Arrival (TDoA) indoor localization. This paper presents a novel IEEE 802.11b baseband receiver and the corresponding localization system. Frame detector and phase recovery block are dedicated to frame reception and frequency offset compensation. Baker code re-correlator is specially designed to improve anti-noise performance. Experimental results demonstrate that the proposed system achieves sub-meter range localization precision.
IEEE 802.11b无线局域网被广泛用于实现基于Wi-Fi的TDoA (Time Difference of Arrival)室内定位。提出了一种新型的IEEE 802.11b基带接收机及其定位系统。帧检测器和相位恢复块用于帧接收和频偏补偿。贝克码重相关器是专门为提高抗噪声性能而设计的。实验结果表明，该系统达到了亚米级的距离定位精度。
{"title":"Design of IEEE 802.11b baseband receiver for indoor localization","authors":"Tuo Xie, H. Hu, Chaoxiang Yang, Chun Zhang, Zhihua Wang","doi":"10.1109/EDSSC.2017.8126465","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126465","url":null,"abstract":"IEEE 802.11b WLAN is widely used to implement Wi-Fi based Time Difference of Arrival (TDoA) indoor localization. This paper presents a novel IEEE 802.11b baseband receiver and the corresponding localization system. Frame detector and phase recovery block are dedicated to frame reception and frequency offset compensation. Baker code re-correlator is specially designed to improve anti-noise performance. Experimental results demonstrate that the proposed system achieves sub-meter range localization precision.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124586847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126454
Nupur Navlakha, Jyi-Tsong Lin, A. Kranti
The work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-to-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of ∼3. The front gate responsible for read mechanism can be scaled down to 75 nm while G2 can be scaled until 40 nm. The investigation highlights better scalability and improved retention characteristics.
{"title":"Design optimization of tunnel FET for dynamic memory applications","authors":"Nupur Navlakha, Jyi-Tsong Lin, A. Kranti","doi":"10.1109/EDSSC.2017.8126454","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126454","url":null,"abstract":"The work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-to-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of ∼3. The front gate responsible for read mechanism can be scaled down to 75 nm while G2 can be scaled until 40 nm. The investigation highlights better scalability and improved retention characteristics.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8333239
Linqi Shi, Weixin Gai, Liangxiao Tang, Xiao Xiang
A novel digital loop filter（DLF）for fast-locking bang-bang all-digital PLL (BBADPLL) is proposed. An adaptive locking monitor (ALM) is used in the DLF, which predicts the frequency error and divides the locking process into three steps. A novel DLF based 10 GHz BBADPLL is implemented in a 65 nm CMOS process, which achieves an average locking time of 1.84 μs while consuming 9.48 mW with supply of 1.2 V.
{"title":"A novel digital loop filter with frequency error prediction for fast-locking bang-bang ADPLL","authors":"Linqi Shi, Weixin Gai, Liangxiao Tang, Xiao Xiang","doi":"10.1109/EDSSC.2017.8333239","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8333239","url":null,"abstract":"A novel digital loop filter（DLF）for fast-locking bang-bang all-digital PLL (BBADPLL) is proposed. An adaptive locking monitor (ALM) is used in the DLF, which predicts the frequency error and divides the locking process into three steps. A novel DLF based 10 GHz BBADPLL is implemented in a 65 nm CMOS process, which achieves an average locking time of 1.84 μs while consuming 9.48 mW with supply of 1.2 V.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123709372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126462
R. Das, S. Baishya
In this paper, we study the effects of two important parameters such as work function of gate material and the temperature, on behavior of FinFET device. The investigation is carried out on Germanium based FinFET device. Working device shows improve current drivability in terms of high on current (ION), less leakage current (IOFF), high value of (ION/IOFF), and have good control on short channel effects (SCEs). Most interestingly, a sub-60 mV/dec of Subthreshold Swing value is found for ambient temperature.
{"title":"Investigation of work function and temperature of germanium FinFETs","authors":"R. Das, S. Baishya","doi":"10.1109/EDSSC.2017.8126462","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126462","url":null,"abstract":"In this paper, we study the effects of two important parameters such as work function of gate material and the temperature, on behavior of FinFET device. The investigation is carried out on Germanium based FinFET device. Working device shows improve current drivability in terms of high on current (ION), less leakage current (IOFF), high value of (ION/IOFF), and have good control on short channel effects (SCEs). Most interestingly, a sub-60 mV/dec of Subthreshold Swing value is found for ambient temperature.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126428
Sang-Hui Park, Sang-Han Lee, Se-Hong Park, Yeong H. Sohn, Yeunhee Huh, G. Cho, C. Rim
Precise Hall effect gap sensor with differential and shielding structure for effective reduction of common electrical and magnetic noise is reported. Applied to a transport system with magnetic levitation, resolution of the sensor resulted in 2 μm while with 2 mV/μm sensitivity at main sensing range of 1.5mm. Less than 1 μm variation is observed despite the ambient magnetic field. Levitation error of the transport system with the gap sensor satisfied a given specification of less than 10 μm.
{"title":"Precise and robust hall effect gap sensor with common electrical and magnetic noise reduction technique","authors":"Sang-Hui Park, Sang-Han Lee, Se-Hong Park, Yeong H. Sohn, Yeunhee Huh, G. Cho, C. Rim","doi":"10.1109/EDSSC.2017.8126428","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126428","url":null,"abstract":"Precise Hall effect gap sensor with differential and shielding structure for effective reduction of common electrical and magnetic noise is reported. Applied to a transport system with magnetic levitation, resolution of the sensor resulted in 2 μm while with 2 mV/μm sensitivity at main sensing range of 1.5mm. Less than 1 μm variation is observed despite the ambient magnetic field. Levitation error of the transport system with the gap sensor satisfied a given specification of less than 10 μm.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129399738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126495
Shengqun Zheng, Kai Sheng, Junxi Chen, Weixin Gai, Jianhua Feng
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating at 500MHz sampling speed in 55nm CMOS technology with a 300fF hold capacitor. The bootstrapped switch consumes 27uW power with only 1.5uW in compensation.
{"title":"A clock-feedthrough compensation technique for bootstrapped switch","authors":"Shengqun Zheng, Kai Sheng, Junxi Chen, Weixin Gai, Jianhua Feng","doi":"10.1109/EDSSC.2017.8126495","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126495","url":null,"abstract":"This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating at 500MHz sampling speed in 55nm CMOS technology with a 300fF hold capacitor. The bootstrapped switch consumes 27uW power with only 1.5uW in compensation.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129712207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126509
Baoyi Cen, Yang Jiang, Kwan-Ting Ng, M. Law, Pui-in Mak, R. Martins
This paper presents a wide range high efficiency fully integrated switched-capacitor DC-DC converter with fixed output spectrum targeting for noise-sensitive Internet-of-Things (IoT) applications. In order to alleviate the unpredictable output spectrum and the reduced energy efficiency of the conventional pulse-frequency modulation (PFM) and pulse-width modulation (PWM) schemes, fixed output spectrum (FOS) modulation is proposed to ensure easy noise filtering while achieving wide range high efficiency operation. A 2-phase 3-level gate driver is also proposed to minimize the reversion loss and enhance conduction. Simulation result in a standard 0.18-μm CMOS process shows that up to 88% high energy efficiency can be achieved with a loading range from 75μA to 3mA using a total flying capacitance of 0.96nF.
{"title":"A wide range high efficiency fully integrated switched-capacitor DC-DC converter with fixed output spectrum modulation","authors":"Baoyi Cen, Yang Jiang, Kwan-Ting Ng, M. Law, Pui-in Mak, R. Martins","doi":"10.1109/EDSSC.2017.8126509","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126509","url":null,"abstract":"This paper presents a wide range high efficiency fully integrated switched-capacitor DC-DC converter with fixed output spectrum targeting for noise-sensitive Internet-of-Things (IoT) applications. In order to alleviate the unpredictable output spectrum and the reduced energy efficiency of the conventional pulse-frequency modulation (PFM) and pulse-width modulation (PWM) schemes, fixed output spectrum (FOS) modulation is proposed to ensure easy noise filtering while achieving wide range high efficiency operation. A 2-phase 3-level gate driver is also proposed to minimize the reversion loss and enhance conduction. Simulation result in a standard 0.18-μm CMOS process shows that up to 88% high energy efficiency can be achieved with a loading range from 75μA to 3mA using a total flying capacitance of 0.96nF.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8333233
Yongcheng He, Shuguo Li
The speed of CBC mode is difficult to develop because of its feedback loop. To improve the speed of CBC mode, a method of removing the XOR gate from the critical path by precomputing T-box which merges S-box and MixColumns operation is proposed in this paper. The implementation of T-box is parallel on the basis of twisted BDD including BDD and 5-32 decoder. We merge the XOR gate into both BDD and the decoder by precalculation so as to eliminate it from the critical path. ASIC implementation proves the effectiveness and we can achieve a throughput of 12.4Gbps using a 0.13μm CMOS standard cell library and this is superior to others compared to previous work.
{"title":"A high throughput implementation of AES with improved BDD T-box structure","authors":"Yongcheng He, Shuguo Li","doi":"10.1109/EDSSC.2017.8333233","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8333233","url":null,"abstract":"The speed of CBC mode is difficult to develop because of its feedback loop. To improve the speed of CBC mode, a method of removing the XOR gate from the critical path by precomputing T-box which merges S-box and MixColumns operation is proposed in this paper. The implementation of T-box is parallel on the basis of twisted BDD including BDD and 5-32 decoder. We merge the XOR gate into both BDD and the decoder by precalculation so as to eliminate it from the critical path. ASIC implementation proves the effectiveness and we can achieve a throughput of 12.4Gbps using a 0.13μm CMOS standard cell library and this is superior to others compared to previous work.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128420887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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