Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126442
Chenjie Tang, K. Teo, J. Shi
This paper presents a simulation study to achieve wide-linear-range transconductance of T-gate GaN HEMTs by introducing a δ-doped layer and a p-GaN back barrier. With optimized δ-doping density and location, the transconductance (gm) and current gain cutoff frequencies (fT) are ultra-flat and remain close to their peak values over a wide range of gate-source voltages (Vgs). In addition, a smaller absolute gm3 (third-order derivative of the Ids-Vgs curve) over a wide range of Vgs is obtained in proposed HEMTs. These features are valuable in designing highly linear RF AlGaN/GaN HEMTs.
{"title":"Simulation of GaN HEMT with wide-linear-range transconductance","authors":"Chenjie Tang, K. Teo, J. Shi","doi":"10.1109/EDSSC.2017.8126442","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126442","url":null,"abstract":"This paper presents a simulation study to achieve wide-linear-range transconductance of T-gate GaN HEMTs by introducing a δ-doped layer and a p-GaN back barrier. With optimized δ-doping density and location, the transconductance (g<inf>m</inf>) and current gain cutoff frequencies (f<inf>T</inf>) are ultra-flat and remain close to their peak values over a wide range of gate-source voltages (Vgs). In addition, a smaller absolute g<inf>m3</inf> (third-order derivative of the I<inf>ds</inf>-V<inf>gs</inf> curve) over a wide range of V<inf>gs</inf> is obtained in proposed HEMTs. These features are valuable in designing highly linear RF AlGaN/GaN HEMTs.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126445
Yufei Xing, Shuguo Li
Elliptic curve cryptography(ECC) has gained tremendous popularity and the selection of coordinate systems has a significant impact on basic point doubling and point addition operations. In this paper, we investigate into the best suited coordinate systems corresponding to scalar multiplication with a fixed point as well as with an unfixed point and give out implementation schemes in both cases. Besides, we look into parameter selection involved in both schemes, which impacts both the speed of scalar multiplication and storage requirement.
{"title":"Towards high speed scalar multiplication over GF(p)","authors":"Yufei Xing, Shuguo Li","doi":"10.1109/EDSSC.2017.8126445","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126445","url":null,"abstract":"Elliptic curve cryptography(ECC) has gained tremendous popularity and the selection of coordinate systems has a significant impact on basic point doubling and point addition operations. In this paper, we investigate into the best suited coordinate systems corresponding to scalar multiplication with a fixed point as well as with an unfixed point and give out implementation schemes in both cases. Besides, we look into parameter selection involved in both schemes, which impacts both the speed of scalar multiplication and storage requirement.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121537329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126401
Hyunmyoung Kim, Taehoon Kim, S. Manisankar, Yeonbae Chung
In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage transfer characteristics essential for robust SRAM functionality. In the write access, the boosted wordline facilitates to change the contents of the memory bit. Implementation results in a 180 nm CMOS technology exhibit that the proposed cell remains unaffected by the read disturbance, while achieves 58.7 % higher dummy read stability and 3.68 × better write-ability at 0.4 V supply compared to the standard 6T SRAM cell.
{"title":"Read disturb-free SRAM bit-cell for subthreshold memory applications","authors":"Hyunmyoung Kim, Taehoon Kim, S. Manisankar, Yeonbae Chung","doi":"10.1109/EDSSC.2017.8126401","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126401","url":null,"abstract":"In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage transfer characteristics essential for robust SRAM functionality. In the write access, the boosted wordline facilitates to change the contents of the memory bit. Implementation results in a 180 nm CMOS technology exhibit that the proposed cell remains unaffected by the read disturbance, while achieves 58.7 % higher dummy read stability and 3.68 × better write-ability at 0.4 V supply compared to the standard 6T SRAM cell.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131367850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126458
M. Yadav, Ravi Shankar R. Velampati, D. Mandal, Rohit Sharma
Ethylene glycol and ortho-dichlorobenzene solvents are used for Nickel (Ni) and Cobalt (Co) nanoparticles (NPs) synthesis, respectively. The wettability by these colloidal nanoparticles samples over silicon oxide wafer substrate has been studied to get insight about distribution of nanoparticles over oxide wafer. It has been found that the samples having nanoparticles in ortho-dichlorobenzene and ethylene glycol solvents show average contact angles of 5.40° and 20.10° over silicon oxide wafer, respectively. Further, metal-oxide-semiconductor (MOS) non volatile memory (NVM) capacitors embedded with spin coated nanoparticles using above two nanoparticles solutions are fabricated. Tunnel oxide of SiO2 (∼3 nm) was thermally grown over p-type (100) Si-wafer followed by spin coating of nanoparticles layer (∼2–4 nm) over it. Finally, atomic layer deposition (ALD) of Al2O3(∼10 nm) layer as control dielectric followed by aluminum (Al) contact formations has been done. Our study concludes that NPs solvents severely affect the distribution of nanoparticles over silicon oxide and hence the memory device performance.
{"title":"Colloidal nanoparticles based non-volatile memory device: Role of wettability by nanoparticles solvents","authors":"M. Yadav, Ravi Shankar R. Velampati, D. Mandal, Rohit Sharma","doi":"10.1109/EDSSC.2017.8126458","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126458","url":null,"abstract":"Ethylene glycol and ortho-dichlorobenzene solvents are used for Nickel (Ni) and Cobalt (Co) nanoparticles (NPs) synthesis, respectively. The wettability by these colloidal nanoparticles samples over silicon oxide wafer substrate has been studied to get insight about distribution of nanoparticles over oxide wafer. It has been found that the samples having nanoparticles in ortho-dichlorobenzene and ethylene glycol solvents show average contact angles of 5.40° and 20.10° over silicon oxide wafer, respectively. Further, metal-oxide-semiconductor (MOS) non volatile memory (NVM) capacitors embedded with spin coated nanoparticles using above two nanoparticles solutions are fabricated. Tunnel oxide of SiO2 (∼3 nm) was thermally grown over p-type (100) Si-wafer followed by spin coating of nanoparticles layer (∼2–4 nm) over it. Finally, atomic layer deposition (ALD) of Al2O3(∼10 nm) layer as control dielectric followed by aluminum (Al) contact formations has been done. Our study concludes that NPs solvents severely affect the distribution of nanoparticles over silicon oxide and hence the memory device performance.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"416 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116560319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126541
Meng-Lieh Sheu, L. Tsao, Kai-Chun Liang
This paper presents a single-inductor dual-output (SIDO) DC-DC boost converter with current controlled pulse frequency modulation (PFM) scheme. The SIDO operated in continuous conduction mode (CCM) uses a single inductor for storing energy and alternatively delivers the energy to an output loading terminal and a supply voltage controller terminal. To ensure a stable operation, the supply voltage controller terminal is always charged before the output loading terminal. A start up circuit is utilized for low input voltage operation. The chip designed with TSMC 0.18μm 1P6M CMOS process operates at an input voltage range from 0.5V to 1.8V, and maintains two output voltages of 1.8V and 3V. An efficiency of 80.7% is achieved at 30mA load current and 0.5V input voltage. A maximal efficiency of 88.6% is achieved when the load current is 120mA at the input voltage of 1.5V.
{"title":"A single-inductor dual-output boost DC-DC converter with 0.5V start-up","authors":"Meng-Lieh Sheu, L. Tsao, Kai-Chun Liang","doi":"10.1109/EDSSC.2017.8126541","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126541","url":null,"abstract":"This paper presents a single-inductor dual-output (SIDO) DC-DC boost converter with current controlled pulse frequency modulation (PFM) scheme. The SIDO operated in continuous conduction mode (CCM) uses a single inductor for storing energy and alternatively delivers the energy to an output loading terminal and a supply voltage controller terminal. To ensure a stable operation, the supply voltage controller terminal is always charged before the output loading terminal. A start up circuit is utilized for low input voltage operation. The chip designed with TSMC 0.18μm 1P6M CMOS process operates at an input voltage range from 0.5V to 1.8V, and maintains two output voltages of 1.8V and 3V. An efficiency of 80.7% is achieved at 30mA load current and 0.5V input voltage. A maximal efficiency of 88.6% is achieved when the load current is 120mA at the input voltage of 1.5V.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133004798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126412
Yan Chen, Boling Yu, Jian Wang, Chunxia Li
A novel PWM/PFM hybrid-mode auto-change technique for buck DC-DC converter is proposed. The proposed technique utilizes the comparator propagation delay to decide the mode changing point without adding complicated PMW/PFM hybrid-mode controller. The proposed concept enables compact and simple implementation of hybrid-mode buck DC-DC converter. Simulation results show that the buck DC-DC converter can achieve seamless transition between PWM and PFM mode. The maximum efficiency of PWM and PFM mode are up to 97% and 94% respectively.
{"title":"A buck DC-DC converter with a novel PWM/PFM hybrid-mode auto-change technique","authors":"Yan Chen, Boling Yu, Jian Wang, Chunxia Li","doi":"10.1109/EDSSC.2017.8126412","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126412","url":null,"abstract":"A novel PWM/PFM hybrid-mode auto-change technique for buck DC-DC converter is proposed. The proposed technique utilizes the comparator propagation delay to decide the mode changing point without adding complicated PMW/PFM hybrid-mode controller. The proposed concept enables compact and simple implementation of hybrid-mode buck DC-DC converter. Simulation results show that the buck DC-DC converter can achieve seamless transition between PWM and PFM mode. The maximum efficiency of PWM and PFM mode are up to 97% and 94% respectively.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126502
Ming Wen, Jiqu Xu, L. Liu, Xinyuan Zhao, P. T. Lai, W. Tang
A 6-layer continuous and uniform MoS2 film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS2 transistor are investigated, and enhanced carrier mobility (0.69 cm2/V·s) is achieved by using Ta2O5 as the buffer layer.
{"title":"Fabrication and electrical performance of CVD-grown MoS2 transistor","authors":"Ming Wen, Jiqu Xu, L. Liu, Xinyuan Zhao, P. T. Lai, W. Tang","doi":"10.1109/EDSSC.2017.8126502","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126502","url":null,"abstract":"A 6-layer continuous and uniform MoS<inf>2</inf> film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS<inf>2</inf> transistor are investigated, and enhanced carrier mobility (0.69 cm<sup>2</sup>/V·s) is achieved by using Ta<inf>2</inf>O<inf>5</inf> as the buffer layer.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126569
Huan Wang, R. Knepper, J. Millithaler, P. Marthi, M. Margala
In this paper, a new design of Terahertz (THz) Ring Hybrid Coupler Based on Parallel Plate Dielectric Waveguide with Signal Line inserted (PPDWS) is proposed. The PPDWS is a simple transmission line, easy to fabricate, with a low average loss of 0.45dB/mm at 1–1.4THz, and designed to be implemented into the THz Ring Hybrid Coupler Design. We employ (3N+1.5)λ for the circumference of the Ring Hybrid Coupler for a fundamental mode of TE10. ANSYS HFSS simulations show S21=S41=−4.5dB, S31< −20dB, S11<-20dB at 1.022THz. We obtain an excellent isolation between split ports for signal transmission, and a very good signal cancellation on port3. The coupler and PPDWS line are planned for use in the Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier; however, the design is also capable of being applied to other very high frequency applications.
{"title":"A terahertz ring hybrid coupler based on parallel plate dielectric waveguide with signal line for a ballistic deflection transistor travelling wave amplifier","authors":"Huan Wang, R. Knepper, J. Millithaler, P. Marthi, M. Margala","doi":"10.1109/EDSSC.2017.8126569","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126569","url":null,"abstract":"In this paper, a new design of Terahertz (THz) Ring Hybrid Coupler Based on Parallel Plate Dielectric Waveguide with Signal Line inserted (PPDWS) is proposed. The PPDWS is a simple transmission line, easy to fabricate, with a low average loss of 0.45dB/mm at 1–1.4THz, and designed to be implemented into the THz Ring Hybrid Coupler Design. We employ (3N+1.5)λ for the circumference of the Ring Hybrid Coupler for a fundamental mode of TE10. ANSYS HFSS simulations show S21=S41=−4.5dB, S31< −20dB, S11<-20dB at 1.022THz. We obtain an excellent isolation between split ports for signal transmission, and a very good signal cancellation on port3. The coupler and PPDWS line are planned for use in the Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier; however, the design is also capable of being applied to other very high frequency applications.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133278757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126398
Yuet Ho Woo, K. Mak, K. Leung
A full-load low-dropout regulator (LDO) based on proposed hybrid compensation structure is proposed. The proposed LDO makes use of an NMOSFET power transistor. The LDO is able to be stabilized for 0 to 1-μF capacitive load. Experimental results prove the LDO stability and fast recovery speed.
{"title":"A full-load hybrid compensated ldo with output capacitance range of 0 to 1 μF","authors":"Yuet Ho Woo, K. Mak, K. Leung","doi":"10.1109/EDSSC.2017.8126398","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126398","url":null,"abstract":"A full-load low-dropout regulator (LDO) based on proposed hybrid compensation structure is proposed. The proposed LDO makes use of an NMOSFET power transistor. The LDO is able to be stabilized for 0 to 1-μF capacitive load. Experimental results prove the LDO stability and fast recovery speed.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133384963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126537
A. P. Shah, N. Yadav, A. Beohar, S. Vishvakarma
This paper presents a novel subthreshold Darlington pair based negative bias temperature instability (NBTI) monitoring sensor under the stress conditions. The Darlington pair used in the circuit provides the stability of the circuit and the high input impedance of the circuit makes it less affected by the PVT variations. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The sensitivity of the proposed sensor is 8.15 μV/nA and also the sensor is less affected by the process variation and has the deviation of 0.0011 mV at standby leakage current of 30 nA.
{"title":"Subthreshold darlington pair based NBTI sensor for reliable CMOS circuits","authors":"A. P. Shah, N. Yadav, A. Beohar, S. Vishvakarma","doi":"10.1109/EDSSC.2017.8126537","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126537","url":null,"abstract":"This paper presents a novel subthreshold Darlington pair based negative bias temperature instability (NBTI) monitoring sensor under the stress conditions. The Darlington pair used in the circuit provides the stability of the circuit and the high input impedance of the circuit makes it less affected by the PVT variations. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The sensitivity of the proposed sensor is 8.15 μV/nA and also the sensor is less affected by the process variation and has the deviation of 0.0011 mV at standby leakage current of 30 nA.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125780727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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