Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126444
Yan Tian, Zekun Guo, H. Gan, Jun Chen, N. Xu, Fei Liu, S. Deng
Due to its potential applications in optoelectric area, WS2/graphene heterojunction attracts much attention in past years. But until now, modulation of their working performance is still a big challenge for the researchers. In this work, WS2/graphene heterojunctions have been sucessfully fabricated on Si substrate. Moreover, their surface configuration were researched by STM and AFM techniques. Finally, they are integrated into back-gated MOSFET devices to research their working performances.
{"title":"Fabrication technique and transportation properties of WS2/graphene heterojunction","authors":"Yan Tian, Zekun Guo, H. Gan, Jun Chen, N. Xu, Fei Liu, S. Deng","doi":"10.1109/EDSSC.2017.8126444","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126444","url":null,"abstract":"Due to its potential applications in optoelectric area, WS2/graphene heterojunction attracts much attention in past years. But until now, modulation of their working performance is still a big challenge for the researchers. In this work, WS2/graphene heterojunctions have been sucessfully fabricated on Si substrate. Moreover, their surface configuration were researched by STM and AFM techniques. Finally, they are integrated into back-gated MOSFET devices to research their working performances.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127694077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8355966
Mao Li, Yuxing Zhou, Dengjie Wang, S. Yuan, Wenhuan Luan, Xin Lin, Ziqiang Wang, Chun Zhang, Xiang Xie
This paper proposes a max mode control low-dropout voltage regulator (LDO) with a novel structure, using MOS bias in depth linear region that control digital MOS to achieve a low ripple and a good behavior power supply rejections ratio (PSRR)at 10GHz or even higher frequency depending on load capacitance in a specified range. The LDO is designed on-chip in 40nm CMOS technology. The simulation results shows that the line regulation is 2.8mV/V and load regulation is less than 0.13mV/mA with a 100Pf as load. PSRR is improved from -40dB@10GHz, approximately. The constant output is 1.1V with minimal input voltage decreasing to 1.26V.The quiesent current is 120uA, 151.2uW under 1.26V supply.
{"title":"A max mode control LDO with a good behavior at PSRR and line regulation and load regulation","authors":"Mao Li, Yuxing Zhou, Dengjie Wang, S. Yuan, Wenhuan Luan, Xin Lin, Ziqiang Wang, Chun Zhang, Xiang Xie","doi":"10.1109/EDSSC.2017.8355966","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8355966","url":null,"abstract":"This paper proposes a max mode control low-dropout voltage regulator (LDO) with a novel structure, using MOS bias in depth linear region that control digital MOS to achieve a low ripple and a good behavior power supply rejections ratio (PSRR)at 10GHz or even higher frequency depending on load capacitance in a specified range. The LDO is designed on-chip in 40nm CMOS technology. The simulation results shows that the line regulation is 2.8mV/V and load regulation is less than 0.13mV/mA with a 100Pf as load. PSRR is improved from -40dB@10GHz, approximately. The constant output is 1.1V with minimal input voltage decreasing to 1.26V.The quiesent current is 120uA, 151.2uW under 1.26V supply.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121271247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126488
Tianshu Fu, Shuguo Li
When encrypting a single file in the CBC mode of 3DES, there is a feedback path which brings data dependency. Even much more resources are given, it does not help matters to increase the throughput of 3DES. In this paper, we propose a logic simplifying method to accelerate the throughput in the CBC mode. In the datapath, 15 levels of XORs from the critical path can be moved to the non-critical path. The experiment results show that our ASIC implementation of 3DES in the CBC mode can achieve 3.33Gbps in throughput, which is the fastest in the CBC mode in the reported designs.
{"title":"A 3DES ASIC implementation with feedback path in the CBC mode","authors":"Tianshu Fu, Shuguo Li","doi":"10.1109/EDSSC.2017.8126488","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126488","url":null,"abstract":"When encrypting a single file in the CBC mode of 3DES, there is a feedback path which brings data dependency. Even much more resources are given, it does not help matters to increase the throughput of 3DES. In this paper, we propose a logic simplifying method to accelerate the throughput in the CBC mode. In the datapath, 15 levels of XORs from the critical path can be moved to the non-critical path. The experiment results show that our ASIC implementation of 3DES in the CBC mode can achieve 3.33Gbps in throughput, which is the fastest in the CBC mode in the reported designs.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116898342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126471
Yang-Hua Chang, Lu-Hao Yang
In this study, the threshold voltage and breakdown voltage of a double-channel AlGaN/GaN HEMT is improved. Firstly, depletion mode (D-mode) is changed to enhancement mode (E-mode) by optimizing the depth of the recessed gate, the Al ratio in the AlGaN layer, and the doping concentration of the p-doped region. Secondly, the E-mode device with highest breakdown voltage is selected, and then implemented with an electron-blocking layer (EBL) structure. The EBL structure is optimized to further improve the breakdown voltage.
{"title":"Double-channel E-Mode AlGaN/GaN HEMTs with an electron-blocking-layer structure","authors":"Yang-Hua Chang, Lu-Hao Yang","doi":"10.1109/EDSSC.2017.8126471","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126471","url":null,"abstract":"In this study, the threshold voltage and breakdown voltage of a double-channel AlGaN/GaN HEMT is improved. Firstly, depletion mode (D-mode) is changed to enhancement mode (E-mode) by optimizing the depth of the recessed gate, the Al ratio in the AlGaN layer, and the doping concentration of the p-doped region. Secondly, the E-mode device with highest breakdown voltage is selected, and then implemented with an electron-blocking layer (EBL) structure. The EBL structure is optimized to further improve the breakdown voltage.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117211325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126423
Jianmei Lei, Shengdong Hu, Song Wang, Zhi Lin
A novel SOI trench LDMOS with vertical double-RESURF is studied in this paper. A p-type silicon pillar is inserted beside the oxide trench as a vertical double RESURF layer, which can effectively modulate the electronic field and enhance the doping concentration in the drift region. The drain n+ region extends to the surface of buried oxide layer, shortening the motion-path in the high-resistance n− drift region for the carriers. A significantly optimized dependence of specific on-resistance on breakdown voltage is obtained.
{"title":"A novel SOI trench LDMOS with vertical double-RESRUF layer","authors":"Jianmei Lei, Shengdong Hu, Song Wang, Zhi Lin","doi":"10.1109/EDSSC.2017.8126423","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126423","url":null,"abstract":"A novel SOI trench LDMOS with vertical double-RESURF is studied in this paper. A p-type silicon pillar is inserted beside the oxide trench as a vertical double RESURF layer, which can effectively modulate the electronic field and enhance the doping concentration in the drift region. The drain n+ region extends to the surface of buried oxide layer, shortening the motion-path in the high-resistance n− drift region for the carriers. A significantly optimized dependence of specific on-resistance on breakdown voltage is obtained.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114119169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126432
Cai-Neng Zhou, Yan Wang, Ruifeng Yue, Gang Dai, Jun-tao Li
A novel edge termination, referred to as etched 3-step junction termination extension with 4-space-modulated buffer trench regions (3S-4SMBT-JTE), is presented for ultrahigh voltage silicon carbide (SiC) power devices. In comparison with the traditional 3S-JTE, the 3S-4SMBT-JTE shows greatly reduced peak electric field (EF) around the corners and edges of the device, resulting in a superior breakdown voltage (BV) performance with wide tolerance to etching depth. According to 2-D device simulations based on the 4H-SiC NPN structure with a 90 μm thick drift layer, an optimized 3S-4SMBT-JTE shows that over 14 kV BV is achievable with a wide etching depth window of 1.0 μm, 67% wider than that of 3S-JTE.
{"title":"Improved etched multistep JTE for UHV SiC power devices","authors":"Cai-Neng Zhou, Yan Wang, Ruifeng Yue, Gang Dai, Jun-tao Li","doi":"10.1109/EDSSC.2017.8126432","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126432","url":null,"abstract":"A novel edge termination, referred to as etched 3-step junction termination extension with 4-space-modulated buffer trench regions (3S-4SMBT-JTE), is presented for ultrahigh voltage silicon carbide (SiC) power devices. In comparison with the traditional 3S-JTE, the 3S-4SMBT-JTE shows greatly reduced peak electric field (EF) around the corners and edges of the device, resulting in a superior breakdown voltage (BV) performance with wide tolerance to etching depth. According to 2-D device simulations based on the 4H-SiC NPN structure with a 90 μm thick drift layer, an optimized 3S-4SMBT-JTE shows that over 14 kV BV is achievable with a wide etching depth window of 1.0 μm, 67% wider than that of 3S-JTE.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 27.6 MHz 297 μW relaxation oscillator is presented in this paper by using an 180-nm CMOS technology. The proposed oscillator employs an adjustable temperature compensation feedforward scheme, in which the charging current can be set steady by a four-bit digital trimming signal. We have demonstrated a frequency variation lower than 33.5 ppm/°C which could be close to 0 ppm/°C in theory if the precision is high enough. In practical production, it is effective to calibrate the mismatching and deviation of fabrication because of the novel adjustable temperature compensation scheme.
{"title":"A 27.6 MHz 297 μW 33 ppm/°C CMOS relaxation oscillator with an adjustable temperature compensation scheme","authors":"Qiang Zhao, Ruibin Xie, Y. Ma, Fengbo Xie, Feng Lin, Shengdong Zhang","doi":"10.1109/EDSSC.2017.8126497","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126497","url":null,"abstract":"A 27.6 MHz 297 μW relaxation oscillator is presented in this paper by using an 180-nm CMOS technology. The proposed oscillator employs an adjustable temperature compensation feedforward scheme, in which the charging current can be set steady by a four-bit digital trimming signal. We have demonstrated a frequency variation lower than 33.5 ppm/°C which could be close to 0 ppm/°C in theory if the precision is high enough. In practical production, it is effective to calibrate the mismatching and deviation of fabrication because of the novel adjustable temperature compensation scheme.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114170401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126533
Pradeep Dasari, S. Bhattacharya, S. Karmalkar
High temperature modelling of GaN HEMTs requires a knowledge of the temperature dependency of low field channel mobility and parasitic source / drain resistances. We discuss extraction of this dependency from drain current versus gate voltage curve at small drain-source voltage.
GaN hemt的高温建模需要了解低场通道迁移率和寄生源/漏电阻的温度依赖性。我们讨论了在小漏源极电压下从漏极电流对栅极电压曲线中提取这种依赖关系。
{"title":"DC extraction of the temperature dependency of low field channel mobility and parasitic resistances in a GaN HEMT","authors":"Pradeep Dasari, S. Bhattacharya, S. Karmalkar","doi":"10.1109/EDSSC.2017.8126533","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126533","url":null,"abstract":"High temperature modelling of GaN HEMTs requires a knowledge of the temperature dependency of low field channel mobility and parasitic source / drain resistances. We discuss extraction of this dependency from drain current versus gate voltage curve at small drain-source voltage.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114639663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126492
Chao Zhang, Jiangtao Gu, Lizhao Gao, Tingbing Ouyang, Bo Wang
This paper presents an addition and multiplication computation cell using pulse train time amplifier (TA) and time register (TR), which could be easily extend to large-scale computation. The proposed pulse train TA exploits a delay cell ring to realize large input range. In TR a gated delay line with MOS capacitor is adopted to achieve both large number computation and high resolution. Finally, a 6-bit addition and multiplication computation cell is designed and implemented in 130nm CMOS process. It achieves 313ps of time resolution with varying multiplier and 1.926ps with varying multiplicand. The static power consumption of the chip is 11.09uW and the area is 0.0324mm2.
{"title":"Time-domain computing circuits for addition and multiplication computation","authors":"Chao Zhang, Jiangtao Gu, Lizhao Gao, Tingbing Ouyang, Bo Wang","doi":"10.1109/EDSSC.2017.8126492","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126492","url":null,"abstract":"This paper presents an addition and multiplication computation cell using pulse train time amplifier (TA) and time register (TR), which could be easily extend to large-scale computation. The proposed pulse train TA exploits a delay cell ring to realize large input range. In TR a gated delay line with MOS capacitor is adopted to achieve both large number computation and high resolution. Finally, a 6-bit addition and multiplication computation cell is designed and implemented in 130nm CMOS process. It achieves 313ps of time resolution with varying multiplier and 1.926ps with varying multiplicand. The static power consumption of the chip is 11.09uW and the area is 0.0324mm2.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125333601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126559
X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.
{"title":"A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit","authors":"X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma","doi":"10.1109/EDSSC.2017.8126559","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126559","url":null,"abstract":"In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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