Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126459
L. Tang, Xintian Zhou, Ruifeng Yue, Yan Wang
This paper analyzes the formation energy and electronic structure of Li-N co-doped diamond by the method of the first-principles density-functional theory (DFT). We found that the Li-N co-doped diamond shows the shallow donor level mainly contributed by the N-2s states and N-2p states for the first time. Meanwhile, the doping efficiency of Li in diamond can be improved by the introduction of N atom. As a result, the n-type doping of diamond with practical dopants becomes possible.
{"title":"N-type lithium-nitrogen codoping in diamond from first principles","authors":"L. Tang, Xintian Zhou, Ruifeng Yue, Yan Wang","doi":"10.1109/EDSSC.2017.8126459","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126459","url":null,"abstract":"This paper analyzes the formation energy and electronic structure of Li-N co-doped diamond by the method of the first-principles density-functional theory (DFT). We found that the Li-N co-doped diamond shows the shallow donor level mainly contributed by the N-2s states and N-2p states for the first time. Meanwhile, the doping efficiency of Li in diamond can be improved by the introduction of N atom. As a result, the n-type doping of diamond with practical dopants becomes possible.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131996990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126517
Qian Dong, Bing Li
This paper presents a lossless compression method dealing with the data in real time kinematic (RTK) system, which is an aggregation of frame difference and dictionary compression (AFD). AFD can exert advantage of pipeline hardware; reduce the amount of data transmission as to save energy. Experiment results showed that the compression time of typical RTK data was only 0.2 milliseconds, and the average compression ratio reduced by almost 20% compared with several classical compression methods.
{"title":"A lossless compression method for RTK in hardware compressors","authors":"Qian Dong, Bing Li","doi":"10.1109/EDSSC.2017.8126517","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126517","url":null,"abstract":"This paper presents a lossless compression method dealing with the data in real time kinematic (RTK) system, which is an aggregation of frame difference and dictionary compression (AFD). AFD can exert advantage of pipeline hardware; reduce the amount of data transmission as to save energy. Experiment results showed that the compression time of typical RTK data was only 0.2 milliseconds, and the average compression ratio reduced by almost 20% compared with several classical compression methods.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131124184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126506
Xia Zhao, Bing Li
Data compression technology is the necessary technology in the age of big data. Compared with software compression techniques, hardware compression techniques can improve speed and reduce power consumption. LZMA is a lossless compression technology, and its hardware implementation has broad application prospects. This paper proposes a novel high-performance implementation of the LZMA compression algorithm capable of processing up to 125Mbps on a Virtex-6 FPGA chip. Then presents a typical application and its compression performance for a specific data sample.
{"title":"Implementation of the LZMA compression algorithm on FPGA","authors":"Xia Zhao, Bing Li","doi":"10.1109/EDSSC.2017.8126506","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126506","url":null,"abstract":"Data compression technology is the necessary technology in the age of big data. Compared with software compression techniques, hardware compression techniques can improve speed and reduce power consumption. LZMA is a lossless compression technology, and its hardware implementation has broad application prospects. This paper proposes a novel high-performance implementation of the LZMA compression algorithm capable of processing up to 125Mbps on a Virtex-6 FPGA chip. Then presents a typical application and its compression performance for a specific data sample.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127039950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8333237
Junxi Chen, Shengqun Zheng, Kai Sheng, Weixin Gai, Jianhua Feng
This paper presents a low-power, area-efficient and widerange offset calibration technique for the high-speed and highresolution comparator. The proposed technique with the low power charge pump significantly reduces the offset voltage (one sigma) from 39mV to 380μV. Without the requirements of capacitors array and extra reference voltage or bias currents, power dissipation and area are greatly reduced. Simulated results show that the comparator with calibration achieves 380μV offset operating at 3 GHz in 55nm CMOS technology with only 23.3μ W in calibration.
{"title":"A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator","authors":"Junxi Chen, Shengqun Zheng, Kai Sheng, Weixin Gai, Jianhua Feng","doi":"10.1109/EDSSC.2017.8333237","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8333237","url":null,"abstract":"This paper presents a low-power, area-efficient and widerange offset calibration technique for the high-speed and highresolution comparator. The proposed technique with the low power charge pump significantly reduces the offset voltage (one sigma) from 39mV to 380μV. Without the requirements of capacitors array and extra reference voltage or bias currents, power dissipation and area are greatly reduced. Simulated results show that the comparator with calibration achieves 380μV offset operating at 3 GHz in 55nm CMOS technology with only 23.3μ W in calibration.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126625604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126501
Kun Yu, W. Tang, J. Dai
A three-dimensional MnCo2S4@NiCo(OH)2 (MCS@NCOH) core-shell nanostructure is grown on nickel foam by a simple and facile method which includes a hydrothermal treatment and an electrochemical deposition. The MnCo2S4 (MCS) nanorod arrays not only show excellent electrochemical performance by themselves, but also use as effective scaffolds to load additional active materials for enhancing the capacitance of the electrode. After adding a thin layer of NiCo(OH)2 nanosheet on Ni foam-MnCo2S4 electrode, the mechanical stability of the whole electrode is reinforced with larger electro-active surface area, richer redox reactions and good electrical conductivity to facilitate electron transport and ion diffusion, resulting in higher charge storage capacity. The Ni foam-MnCo2S4-NiCo(OH)2 hybrid electrodes are further assembled into a solid-state supercapacitor (SC) which exhibits a high energy density of 95 mWh/m2, power density of 55.4 W/m2 and good rate capability.
{"title":"A study on MnCo2S4@NiCo(OH)2 core-shell nanocomposite for high-performance solid-state supercapacitor applications","authors":"Kun Yu, W. Tang, J. Dai","doi":"10.1109/EDSSC.2017.8126501","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126501","url":null,"abstract":"A three-dimensional MnCo<inf>2</inf>S<inf>4</inf>@NiCo(OH)<inf>2</inf> (MCS@NCOH) core-shell nanostructure is grown on nickel foam by a simple and facile method which includes a hydrothermal treatment and an electrochemical deposition. The MnCo<inf>2</inf>S<inf>4</inf> (MCS) nanorod arrays not only show excellent electrochemical performance by themselves, but also use as effective scaffolds to load additional active materials for enhancing the capacitance of the electrode. After adding a thin layer of NiCo(OH)<inf>2</inf> nanosheet on Ni foam-MnCo<inf>2</inf>S<inf>4</inf> electrode, the mechanical stability of the whole electrode is reinforced with larger electro-active surface area, richer redox reactions and good electrical conductivity to facilitate electron transport and ion diffusion, resulting in higher charge storage capacity. The Ni foam-MnCo<inf>2</inf>S<inf>4</inf>-NiCo(OH)<inf>2</inf> hybrid electrodes are further assembled into a solid-state supercapacitor (SC) which exhibits a high energy density of 95 mWh/m<sup>2</sup>, power density of 55.4 W/m<sup>2</sup> and good rate capability.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114089938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126455
Yifeng Mo, Shuguo Li
Modular multiplier is the key to implement RSA algorithm. This paper proposes the design of an 8192-bit residue number system (RNS) Montgomery multiplier based on Cox-Rower architecture. To accelerate the reduction unit, we select modulo with a small Hamming weigh, and modulo are grouped by the number of Rowers. Each Rower unit only needs to support the reduction processes of one group of modulo instead of all modulo, thus eliminating the redundancy of the conventional structure and reducing delay and area of reduction units. Our reduction unit is smaller and faster than classic reduction unit. In SMIC μm, one 8192-bit modular multiplication is accomplished in 8056 ns at the cost of 1240 KG.
{"title":"Design of an 8192-bit RNS montgomery multiplier","authors":"Yifeng Mo, Shuguo Li","doi":"10.1109/EDSSC.2017.8126455","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126455","url":null,"abstract":"Modular multiplier is the key to implement RSA algorithm. This paper proposes the design of an 8192-bit residue number system (RNS) Montgomery multiplier based on Cox-Rower architecture. To accelerate the reduction unit, we select modulo with a small Hamming weigh, and modulo are grouped by the number of Rowers. Each Rower unit only needs to support the reduction processes of one group of modulo instead of all modulo, thus eliminating the redundancy of the conventional structure and reducing delay and area of reduction units. Our reduction unit is smaller and faster than classic reduction unit. In SMIC μm, one 8192-bit modular multiplication is accomplished in 8056 ns at the cost of 1240 KG.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124209943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126523
Peng Li, Yuehua Wu, J. Wen, Lei Cui, Chenjing Liu
For the first time, this paper reveals and explains the detailed contribution of the main-junction lateral resistive zone to the ruggedness of high-voltage fast recovery diodes during a harsh reverse recovery. And its optimized width is discussed.
{"title":"The contribution of the main-junction lateral resistive zone to the ruggedness of high-voltage FRDs: A new insight","authors":"Peng Li, Yuehua Wu, J. Wen, Lei Cui, Chenjing Liu","doi":"10.1109/EDSSC.2017.8126523","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126523","url":null,"abstract":"For the first time, this paper reveals and explains the detailed contribution of the main-junction lateral resistive zone to the ruggedness of high-voltage fast recovery diodes during a harsh reverse recovery. And its optimized width is discussed.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116671849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126573
Yang Zhang, D. Basak, Daxiang Li, K. Pun
This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.
{"title":"Active-RC continuous-time DSM with FIR+SCR DAC","authors":"Yang Zhang, D. Basak, Daxiang Li, K. Pun","doi":"10.1109/EDSSC.2017.8126573","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126573","url":null,"abstract":"This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116868302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126534
S. Raju, M. Chan
This paper gives a general overview on the methods to reduce interconnect resistance and capacitance in a standard CMOS technology followed by a discussion on the physical constraints that dictate the minimum achievable loading. A newly demonstrated method that uses carbon-nanotube to assist the formation of vertically aligned porous structure is studied. The method was shown to be able to reduce the dielectric constant of the interlayer dielectric to an extremely low value below 2.0 with reasonable physical strength. The potential of this method to be used in main-stream production technology is investigated.
{"title":"Ultra-Low-k interlayer dielectric for post-moore CMOS interconnect","authors":"S. Raju, M. Chan","doi":"10.1109/EDSSC.2017.8126534","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126534","url":null,"abstract":"This paper gives a general overview on the methods to reduce interconnect resistance and capacitance in a standard CMOS technology followed by a discussion on the physical constraints that dictate the minimum achievable loading. A newly demonstrated method that uses carbon-nanotube to assist the formation of vertically aligned porous structure is studied. The method was shown to be able to reduce the dielectric constant of the interlayer dielectric to an extremely low value below 2.0 with reasonable physical strength. The potential of this method to be used in main-stream production technology is investigated.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115009600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126419
Zhao Gongyuan, Z. Yiqiang, Ye Mao
A new CMOS readout circuit with non-uniformity calibration for diode uncooled infrared focal plane array (IRFPA) is presented in this paper. A new transconductance amplifier with offset cancellation structure is proposed, utilizing output offset voltage storage. The bias current of each pixel is adjusted by a current splitting DAC array, calibrating the mismatch of the current sources and the non-uniformity of the IRFPA. The proposed circuit prototype with 32 readout channels is fabricated using a 0.35 μm standard CMOS process. The measured results show that the average output offset voltage is decreased by 94% after offset cancellation. The current splitting DAC array shows a DNL/INL less than 2 LSB.
{"title":"A ROIC for diode uncooled IRFPA with non-uniformity compensation technique","authors":"Zhao Gongyuan, Z. Yiqiang, Ye Mao","doi":"10.1109/EDSSC.2017.8126419","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126419","url":null,"abstract":"A new CMOS readout circuit with non-uniformity calibration for diode uncooled infrared focal plane array (IRFPA) is presented in this paper. A new transconductance amplifier with offset cancellation structure is proposed, utilizing output offset voltage storage. The bias current of each pixel is adjusted by a current splitting DAC array, calibrating the mismatch of the current sources and the non-uniformity of the IRFPA. The proposed circuit prototype with 32 readout channels is fabricated using a 0.35 μm standard CMOS process. The measured results show that the average output offset voltage is decreased by 94% after offset cancellation. The current splitting DAC array shows a DNL/INL less than 2 LSB.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123706683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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