Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106154
Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike
This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.
{"title":"Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation","authors":"Y. Ogasahara, T. Sekigawa, M. Hioki, T. Nakagawa, T. Tsutsumi, H. Koike","doi":"10.1109/ICMTS.2015.7106154","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106154","url":null,"abstract":"This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131202841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106120
D. Tomaszewski, G. Gluszko, J. Malesinska, K. Domanski, M. Zaborowski, K. Kucharski, D. Szmigiel, A. Sierakowski
A method for a direct extraction of individual serial resistances of MOSFET source/drain electrodes is presented. It is based on the device I-V characteristics in a saturation range measured for two device configurations inverted with respect to source and drain electrodes. A threshold voltage necessary for the saturation range modeling is determined from the non-saturation range I-V characteristics. Based on the measurement data determined for the SOI MOSFETs fabricated in ITE the proposed method has been compared with other techniques.
{"title":"A simple method for characterization of MOSFET serial resistance asymmetry","authors":"D. Tomaszewski, G. Gluszko, J. Malesinska, K. Domanski, M. Zaborowski, K. Kucharski, D. Szmigiel, A. Sierakowski","doi":"10.1109/ICMTS.2015.7106120","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106120","url":null,"abstract":"A method for a direct extraction of individual serial resistances of MOSFET source/drain electrodes is presented. It is based on the device I-V characteristics in a saturation range measured for two device configurations inverted with respect to source and drain electrodes. A threshold voltage necessary for the saturation range modeling is determined from the non-saturation range I-V characteristics. Based on the measurement data determined for the SOI MOSFETs fabricated in ITE the proposed method has been compared with other techniques.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106099
L. Floyd, J. Pike, Jing Tao, N. Jackson
In the course of developing a GaAs Schottky diode membrane technology for millimeter wave applications (viz. THz mixers and multipliers) it was found that subtle changes and variations introduced into the membrane structure can significantly affect the circuit performance. We describe how these effects manifest themselves and, using S-parameter measurements on a variety of substrates, show how they can be explained in terms of conductive or charge layers that are observable through Coplanar Transmission Line Impedance measurements. A modified transmission line model is given.
{"title":"Observations on substrate characterisation through Coplanar Transmission Line Impedance measurements","authors":"L. Floyd, J. Pike, Jing Tao, N. Jackson","doi":"10.1109/ICMTS.2015.7106099","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106099","url":null,"abstract":"In the course of developing a GaAs Schottky diode membrane technology for millimeter wave applications (viz. THz mixers and multipliers) it was found that subtle changes and variations introduced into the membrane structure can significantly affect the circuit performance. We describe how these effects manifest themselves and, using S-parameter measurements on a variety of substrates, show how they can be explained in terms of conductive or charge layers that are observable through Coplanar Transmission Line Impedance measurements. A modified transmission line model is given.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115949308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106125
T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa
An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.
{"title":"Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node","authors":"T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa","doi":"10.1109/ICMTS.2015.7106125","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106125","url":null,"abstract":"An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114923146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106104
Jin-Woong Jeong, Sungkyu Kwon, Jae-Nam Yu, Seong-Yong Jang, Sun-Ho Oh, Choul‐Young Kim, Ga-Won Lee, H. Lee
This paper presents a newly proposed T-model of spiral inductors in 90nm radio frequency (RF) CMOS technology. Inductor modeling is one of the most difficult problems facing silicon-based RF integrated circuit designers, and the inclusion of many parameters of the inductor equivalent circuit consumes a lot of time during circuit simulation. In this paper, two models of spiral inductors were simulated to compare their agreement with the measured data from 100MHz to 10GHz. The proposed T-model had less parameters than the conventional double-π model, and also showed good agreement in the RF performance of the spiral inductors, such as quality factor (Q-factor) and inductance (L). In addition, the proposed T-model had an error rate of less than 5% with the S-parameter of measured data, similar to the double-π model.
{"title":"Modeling of T-model equivalent circuit for spiral inductors in 90 nm CMOS technology","authors":"Jin-Woong Jeong, Sungkyu Kwon, Jae-Nam Yu, Seong-Yong Jang, Sun-Ho Oh, Choul‐Young Kim, Ga-Won Lee, H. Lee","doi":"10.1109/ICMTS.2015.7106104","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106104","url":null,"abstract":"This paper presents a newly proposed T-model of spiral inductors in 90nm radio frequency (RF) CMOS technology. Inductor modeling is one of the most difficult problems facing silicon-based RF integrated circuit designers, and the inclusion of many parameters of the inductor equivalent circuit consumes a lot of time during circuit simulation. In this paper, two models of spiral inductors were simulated to compare their agreement with the measured data from 100MHz to 10GHz. The proposed T-model had less parameters than the conventional double-π model, and also showed good agreement in the RF performance of the spiral inductors, such as quality factor (Q-factor) and inductance (L). In addition, the proposed T-model had an error rate of less than 5% with the S-parameter of measured data, similar to the double-π model.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125519073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106135
L. Qi, L. Nanver
Sheet-resistance test-structures to determine conductance along the interface formed by 400°C pure boron (PureB) deposition on silicon are presented. The structures are straightforward to fabricate and measure for monitoring either directly after deposition or end-of-line. This provides valuable information on the perfection of the deposition and the series resistance of PureB (photo)diodes.
{"title":"Sheet resistance measurement for process monitoring of 400 °C PureB deposition on Si","authors":"L. Qi, L. Nanver","doi":"10.1109/ICMTS.2015.7106135","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106135","url":null,"abstract":"Sheet-resistance test-structures to determine conductance along the interface formed by 400°C pure boron (PureB) deposition on silicon are presented. The structures are straightforward to fabricate and measure for monitoring either directly after deposition or end-of-line. This provides valuable information on the perfection of the deposition and the series resistance of PureB (photo)diodes.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116048652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106123
S. Mori, K. Ogawa, H. Oishi, Tsuyoshi Suzuki, Manabu Tomita, M. Bairo, Y. Fukuzaki, H. Ohnuma
We propose monitoring test structure and measurement technique for plasma process induced charging damage (PID) using charge-based capacitance measurement (CBCM). For evaluating the influence of PID on MOSFET effectively, remarkably small (several tens of fF) gate capacitance of MOSFET can be extracted by eliminating parasitic antenna capacitance. Moreover, we can extract interface trap density from the same CBCM structure using the modified Charge-Pumping measurement.
{"title":"Monitoring test structure for plasma process induced charging damage using charge-based capacitance measurement (PID-CBCM)","authors":"S. Mori, K. Ogawa, H. Oishi, Tsuyoshi Suzuki, Manabu Tomita, M. Bairo, Y. Fukuzaki, H. Ohnuma","doi":"10.1109/ICMTS.2015.7106123","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106123","url":null,"abstract":"We propose monitoring test structure and measurement technique for plasma process induced charging damage (PID) using charge-based capacitance measurement (CBCM). For evaluating the influence of PID on MOSFET effectively, remarkably small (several tens of fF) gate capacitance of MOSFET can be extracted by eliminating parasitic antenna capacitance. Moreover, we can extract interface trap density from the same CBCM structure using the modified Charge-Pumping measurement.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132458157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106110
A. Cros, F. Monsieur, Y. Carminati, P. Normandon, D. Petit, F. Arnaud, J. Rosa
The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring. The second, using the Idsat sensitivity to the Tsi in an addressable transistors array, allows to measure the local variations in the range of few tens of microns.
{"title":"Silicon thickness monitoring strategy for FD-SOI 28nm technology","authors":"A. Cros, F. Monsieur, Y. Carminati, P. Normandon, D. Petit, F. Arnaud, J. Rosa","doi":"10.1109/ICMTS.2015.7106110","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106110","url":null,"abstract":"The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring. The second, using the Idsat sensitivity to the Tsi in an addressable transistors array, allows to measure the local variations in the range of few tens of microns.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134502394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106097
M. Ritter, M. Pfost
DMOS transistors in integrated smart power technologies are often subject to cyclic power dissipation with substantial self-heating. This leads to repetitive thermo-mechanical stress, causing fatigue of the on-chip metallization and limiting the lifetime. Hence, most designs use large devices for lower peak temperatures and thus reduced stress to avoid premature failures. However, significantly smaller DMOS transistors are acceptable if the system reverts to a safer operating condition with lower stress when a failure is expected to occur in the near future. Hence, suitable early-warning sensors are required. This paper proposes a floating metal meander embedded between DMOS source and drain to detect an impending metallization failure. Measurement results of several variants will be presented and discussed, investigating their suitability as early warning indicators.
{"title":"A proposal for early warning indicators to detect impending metallization failure of DMOS transistors in cyclic operation","authors":"M. Ritter, M. Pfost","doi":"10.1109/ICMTS.2015.7106097","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106097","url":null,"abstract":"DMOS transistors in integrated smart power technologies are often subject to cyclic power dissipation with substantial self-heating. This leads to repetitive thermo-mechanical stress, causing fatigue of the on-chip metallization and limiting the lifetime. Hence, most designs use large devices for lower peak temperatures and thus reduced stress to avoid premature failures. However, significantly smaller DMOS transistors are acceptable if the system reverts to a safer operating condition with lower stress when a failure is expected to occur in the near future. Hence, suitable early-warning sensors are required. This paper proposes a floating metal meander embedded between DMOS source and drain to detect an impending metallization failure. Measurement results of several variants will be presented and discussed, investigating their suitability as early warning indicators.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133387236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106155
A. M. Mahfuzul Islam, H. Onodera
We propose an area-efficient and low-cost extraction methodology of Vth variation which utilizes the exponential relationship of gate delay to Vth variation. The exponential relationship is achieved by operating the DUT in the weak inversion region. Utilizing a previously proposed pass-gate based topology-reconfigurable ring oscillator, the weak inversion operation of a specific gate is achieved while maintaining a much higher supply voltage for the overall circuit. Area-efficiency is achieved by altering the individual gate topology and measuring for each topology. Based on a pass-gate inserted inverter delay model, the relationship of delay variation to Vth variation is expressed using the body effect and DIBL coefficients. Thus, the proposed method does not require any sensitivity calculation. Vth variation is then extracted from the measured delay distributions directly. A test chip containing three different sizes of DUTs are fabricated in a 65-nm bulk CMOS process. Vth variation of nMOSFET and pMOSFET for three different DUT sizes are successfully extracted. The methodology is suitable for low-cost, area-efficient and all-digital measurement of Vth variation.
{"title":"Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution","authors":"A. M. Mahfuzul Islam, H. Onodera","doi":"10.1109/ICMTS.2015.7106155","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106155","url":null,"abstract":"We propose an area-efficient and low-cost extraction methodology of Vth variation which utilizes the exponential relationship of gate delay to Vth variation. The exponential relationship is achieved by operating the DUT in the weak inversion region. Utilizing a previously proposed pass-gate based topology-reconfigurable ring oscillator, the weak inversion operation of a specific gate is achieved while maintaining a much higher supply voltage for the overall circuit. Area-efficiency is achieved by altering the individual gate topology and measuring for each topology. Based on a pass-gate inserted inverter delay model, the relationship of delay variation to Vth variation is expressed using the body effect and DIBL coefficients. Thus, the proposed method does not require any sensitivity calculation. Vth variation is then extracted from the measured delay distributions directly. A test chip containing three different sizes of DUTs are fabricated in a 65-nm bulk CMOS process. Vth variation of nMOSFET and pMOSFET for three different DUT sizes are successfully extracted. The methodology is suitable for low-cost, area-efficient and all-digital measurement of Vth variation.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116880887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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