Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106105
Weimin Wu, Suman K. Banerjee, K. Joardar
This paper presents a physics-based compact model for four-terminal (4T) JFETs. It is capable of modeling device characteristics when the top and bottom gates are biased independently. The model is formulated using symmetric linearization technique from the CMC (compact model council) standard MOSFET model PSP, which gives simpler model equations than other reported 4T JFET models. It also includes carrier velocity saturation effect which is important for short channel and/or high voltage devices. The model has been verified on several JFETs (including device with blocking voltage rated > 700V). Good agreement has been achieved between silicon data and simulation. The complete model has been implemented into process design kits (PDKs) for high-voltage power management switcher design.
本文提出了一个基于物理的四端(4T) jfet紧凑模型。它能够在上下门独立偏置时对器件特性进行建模。该模型采用CMC (compact model council)标准MOSFET模型PSP的对称线性化技术，模型方程比其他已有的4T JFET模型更简单。它还包括载波速度饱和效应，这对短通道和/或高压器件很重要。该模型已在多个jfet(包括额定阻断电压> 700V的器件)上进行了验证。实测数据与仿真结果吻合较好。完整的模型已应用于高压电源管理开关设计的过程设计套件(pdk)中。
{"title":"A four-terminal JFET compact model for high-voltage power applications","authors":"Weimin Wu, Suman K. Banerjee, K. Joardar","doi":"10.1109/ICMTS.2015.7106105","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106105","url":null,"abstract":"This paper presents a physics-based compact model for four-terminal (4T) JFETs. It is capable of modeling device characteristics when the top and bottom gates are biased independently. The model is formulated using symmetric linearization technique from the CMC (compact model council) standard MOSFET model PSP, which gives simpler model equations than other reported 4T JFET models. It also includes carrier velocity saturation effect which is important for short channel and/or high voltage devices. The model has been verified on several JFETs (including device with blocking voltage rated > 700V). Good agreement has been achieved between silicon data and simulation. The complete model has been implemented into process design kits (PDKs) for high-voltage power management switcher design.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114054021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106127
H. Tuinhout, N. Wils, P. Huiskamp, Eelco de Koning
A test structure is presented that combines two types of full Kelvin matched resistor pairs in a single 12 pad process control compatible test line. Based on these structures, matching results of SiCr resistors in a BiCMOS RF technology are discussed, demonstrating some of the frequently encountered challenges of interpreting subtle parametric mismatch fluctuation effects.
{"title":"Design and evaluation of an integrated thin film resistor matching test structure","authors":"H. Tuinhout, N. Wils, P. Huiskamp, Eelco de Koning","doi":"10.1109/ICMTS.2015.7106127","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106127","url":null,"abstract":"A test structure is presented that combines two types of full Kelvin matched resistor pairs in a single 12 pad process control compatible test line. Based on these structures, matching results of SiCr resistors in a BiCMOS RF technology are discussed, demonstrating some of the frequently encountered challenges of interpreting subtle parametric mismatch fluctuation effects.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122354392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106126
K. Sawada, G. van der Plas, S. Mori, C. Vladimir, A. Mercha, V. Diederik, Y. Fukuzaki, H. Ammo
CBCM measurements require known clock frequency. We proposed CBCM test structures with an internal start-stop self-pulsing circuit instead of external clock monitoring. The circuit creates 213 pulses in a time-slot defined by SMU pulsed signal, resulting in known clock frequency. We accurately extract MOSFET's gate capacitances of several tens of fF.
{"title":"In-line monitoring test structure for Charge-Based Capacitance Measurement (CBCM) with a start-stop self-pulsing circuit","authors":"K. Sawada, G. van der Plas, S. Mori, C. Vladimir, A. Mercha, V. Diederik, Y. Fukuzaki, H. Ammo","doi":"10.1109/ICMTS.2015.7106126","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106126","url":null,"abstract":"CBCM measurements require known clock frequency. We proposed CBCM test structures with an internal start-stop self-pulsing circuit instead of external clock monitoring. The circuit creates 213 pulses in a time-slot defined by SMU pulsed signal, resulting in known clock frequency. We accurately extract MOSFET's gate capacitances of several tens of fF.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114654059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106108
Cong Gu, C. McAndrew
This paper presents a robust process qualification and monitoring procedure based on the recently developed YAT and YWL process capability indices. Combined with appropriate test structures and measurements the procedure enables rapid process maturity evaluation and on-going loop closure of manufacturing to process specifications. The procedure generates interactive web-based reports and data that provide high-level “scoring” and a time-line of process capability, an ability to quickly dive down and identify the root cause of issues, and capability to compare between fabs.
{"title":"Robust process capability index tracking for process qualification","authors":"Cong Gu, C. McAndrew","doi":"10.1109/ICMTS.2015.7106108","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106108","url":null,"abstract":"This paper presents a robust process qualification and monitoring procedure based on the recently developed YAT and YWL process capability indices. Combined with appropriate test structures and measurements the procedure enables rapid process maturity evaluation and on-going loop closure of manufacturing to process specifications. The procedure generates interactive web-based reports and data that provide high-level “scoring” and a time-line of process capability, an ability to quickly dive down and identify the root cause of issues, and capability to compare between fabs.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106139
N. Jackson, O. Olszewski, L. Keeney, A. Blake, A. Mathewson
Aluminum nitride (AlN) is a piezoelectric material that is commonly used in various MEMS applications. However, determining the properties of the thin film typically requires multiple test structures, and there are various methods for obtaining the piezoelectric properties. This paper highlights the development of a capacitive based test structure that is capable of determining the different material properties. In addition this paper compares various test methods used to determine the piezoelectric properties of AlN.
{"title":"A capacitive based piezoelectric AlN film quality test structure","authors":"N. Jackson, O. Olszewski, L. Keeney, A. Blake, A. Mathewson","doi":"10.1109/ICMTS.2015.7106139","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106139","url":null,"abstract":"Aluminum nitride (AlN) is a piezoelectric material that is commonly used in various MEMS applications. However, determining the properties of the thin film typically requires multiple test structures, and there are various methods for obtaining the piezoelectric properties. This paper highlights the development of a capacitive based test structure that is capable of determining the different material properties. In addition this paper compares various test methods used to determine the piezoelectric properties of AlN.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125120970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106109
Y. Denis, F. Monsieur, G. Ghibaudo, J. Mazurier, E. Josse, D. Rideau, C. Charbuillet, C. Tavernier, H. Jaouen
This paper provides a compact model for performance and process variability assessment in 14nm FDSOI CMOS technology. It is used to investigate MOS performance relation with process parameters. Then production device within wafer variability has been modeled using backward propagation of variance (BPV). This application allows spotting the main model parameter contributing to the total MOS transistor resistance (Ron) variability.
{"title":"New compact model for performance and process variability assessment in 14nm FDSOI CMOS technology","authors":"Y. Denis, F. Monsieur, G. Ghibaudo, J. Mazurier, E. Josse, D. Rideau, C. Charbuillet, C. Tavernier, H. Jaouen","doi":"10.1109/ICMTS.2015.7106109","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106109","url":null,"abstract":"This paper provides a compact model for performance and process variability assessment in 14nm FDSOI CMOS technology. It is used to investigate MOS performance relation with process parameters. Then production device within wafer variability has been modeled using backward propagation of variance (BPV). This application allows spotting the main model parameter contributing to the total MOS transistor resistance (Ron) variability.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106100
K. Takano, K. Katayama, S. Mizukusa, S. Amakawa, T. Yoshida, M. Fujishima
This work proposed the systematic calibration method of process parameters for electromagnetic analysis of CMOS back-end devices in millimeter-wave and THz frequencies. It uses the propagation constants of transmission lines in all the measurement frequency and the RLGC model parameters in low frequency as the objective variables of the parameter fitting. It was showed that the EM simulation results using calibrated process parameters were in good agreement with the measurement results up to 330 GHz.
{"title":"Systematic calibration procedure of process parameters for electromagnetic field analysis of millimeter-wave CMOS devices","authors":"K. Takano, K. Katayama, S. Mizukusa, S. Amakawa, T. Yoshida, M. Fujishima","doi":"10.1109/ICMTS.2015.7106100","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106100","url":null,"abstract":"This work proposed the systematic calibration method of process parameters for electromagnetic analysis of CMOS back-end devices in millimeter-wave and THz frequencies. It uses the propagation constants of transmission lines in all the measurement frequency and the RLGC model parameters in low frequency as the objective variables of the parameter fitting. It was showed that the EM simulation results using calibrated process parameters were in good agreement with the measurement results up to 330 GHz.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121644562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106121
V. Mosser, David Seron, Y. Haddab
We propose a new method suited for the extraction of the threshold voltage in 2D Field-Effect-Transistors. It can be applied to various classes of devices where the mobility exhibits a power-law dependence on carrier concentration, μ ∝ nSα. The result doesn't depend on contact resistance. The method provides a physically sound value: VG-VT is proportional to the channel carrier density as checked with VG-dependent Hall measurements in companion gated Hall devices.
{"title":"Threshold voltage extraction method in field-effect devices with power-law dependence of mobility on carrier density","authors":"V. Mosser, David Seron, Y. Haddab","doi":"10.1109/ICMTS.2015.7106121","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106121","url":null,"abstract":"We propose a new method suited for the extraction of the threshold voltage in 2D Field-Effect-Transistors. It can be applied to various classes of devices where the mobility exhibits a power-law dependence on carrier concentration, μ ∝ n<sub>S</sub><sup>α</sup>. The result doesn't depend on contact resistance. The method provides a physically sound value: V<sub>G</sub>-V<sub>T</sub> is proportional to the channel carrier density as checked with V<sub>G</sub>-dependent Hall measurements in companion gated Hall devices.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106134
J. Lehmann, C. Leroux, G. Reimbold, M. Charles, A. Torres, E. Morvan, Y. Baines, G. Ghibaudo, E. Bano
In this paper, we present a new method of sheet resistance measurement on AlGaN/GaN wafers. Such measurements are useful for an easy monitoring of AlGaN/GaN epitaxy. Measurements were obtained by adapting the four-point probe technique to AlGaN/GaN wafers. This method is used today in the 200mm GaN-on-Si fabrication line at the CEA-LETI with a standard deviation of 2% on the sheet resistance measurement.
{"title":"Novel sheet resistance measurement on AlGaN/GaN HEMT wafer adapted from four-point probe technique","authors":"J. Lehmann, C. Leroux, G. Reimbold, M. Charles, A. Torres, E. Morvan, Y. Baines, G. Ghibaudo, E. Bano","doi":"10.1109/ICMTS.2015.7106134","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106134","url":null,"abstract":"In this paper, we present a new method of sheet resistance measurement on AlGaN/GaN wafers. Such measurements are useful for an easy monitoring of AlGaN/GaN epitaxy. Measurements were obtained by adapting the four-point probe technique to AlGaN/GaN wafers. This method is used today in the 200mm GaN-on-Si fabrication line at the CEA-LETI with a standard deviation of 2% on the sheet resistance measurement.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116973966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106153
Neha Agarwal
This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.
{"title":"Test circuit for accurate measurement of setup/hold and access time of memories","authors":"Neha Agarwal","doi":"10.1109/ICMTS.2015.7106153","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106153","url":null,"abstract":"This paper will examine the latest developments in the field of designing the test circuits for accurate measurement of setup/hold and access time of memory IPs. Measurement across all voltage domain and temperature corners, by way of the architecture discussed, has a fine resolution of just two inverter delay and correlates well with silicon within permissible range.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124421897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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