Pub Date : 2026-05-01Epub Date: 2026-01-05DOI: 10.1016/j.mssp.2025.110391
Mohini Sawane , Mahanth Prasad , Murugan S. , Velmurugan K.
The piezoelectric MEMS sensor's market is experiencing rapid expansion, driven by self-powered operation, compact form factors, and scalable manufacturing. A novel fabrication technique using minimized fabrication processes and clean room resources were developed to produce cost-effective, compact and lightweight sensors. Microtunnel and through-hole cavity are etched into a silicon substrate and sealed with glass via anodic bonding. A PVDF-based diaphragm is bonded at the front side using vacuum-assisted mounting. Designed and developed PVDF based sensor variants (ST501–ST503 and ST1201–ST1203) were benchmarked against a Brüel & Kjær 4944A reference microphone using a B&K 4292-L loudspeaker and Noise Generator Type 1405. Their output closely matched the calibrated reference microphone tested for 1/3rd octave frequency range from 125Hz to 2 kHz, indicating high accuracy and reproducibility. Overall, the fabricated sensors exhibit reliable SPL measurement performance comparable to industry-standard microphone.
压电MEMS传感器的市场正在经历快速扩张，受自供电操作，紧凑的外形因素和可扩展的制造驱动。利用最小化的制造工艺和洁净室资源，开发了一种新型的制造技术，以生产成本低、结构紧凑、重量轻的传感器。微隧道和通孔腔蚀刻在硅衬底上，并通过阳极键合用玻璃密封。使用真空辅助安装的pvdf基隔膜粘合在前部。设计和开发的基于PVDF的传感器变体（ST501-ST503和ST1201-ST1203）与使用B&；K 4292-L扬声器和1405型噪声发生器的br el &；K ær 4944A参考麦克风进行基准测试。它们的输出与校准的参考麦克风在1/3倍频频率范围内（125Hz至2khz）进行测试，显示出高精度和再现性。总体而言，制造的传感器具有可靠的声压级测量性能，可与行业标准麦克风相媲美。
{"title":"Development of self-powered PVDF based MEMS sensors for sound pressure level measurements","authors":"Mohini Sawane , Mahanth Prasad , Murugan S. , Velmurugan K.","doi":"10.1016/j.mssp.2025.110391","DOIUrl":"10.1016/j.mssp.2025.110391","url":null,"abstract":"<div><div>The piezoelectric MEMS sensor's market is experiencing rapid expansion, driven by self-powered operation, compact form factors, and scalable manufacturing. A novel fabrication technique using minimized fabrication processes and clean room resources were developed to produce cost-effective, compact and lightweight sensors. Microtunnel and through-hole cavity are etched into a silicon substrate and sealed with glass via anodic bonding. A PVDF-based diaphragm is bonded at the front side using vacuum-assisted mounting. Designed and developed PVDF based sensor variants (ST501–ST503 and ST1201–ST1203) were benchmarked against a Brüel & Kjær 4944A reference microphone using a B&K 4292-L loudspeaker and Noise Generator Type 1405. Their output closely matched the calibrated reference microphone tested for 1/3rd octave frequency range from 125Hz to 2 kHz, indicating high accuracy and reproducibility. Overall, the fabricated sensors exhibit reliable SPL measurement performance comparable to industry-standard microphone.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110391"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-09DOI: 10.1016/j.mssp.2026.110420
Qinlong Zhao, Wei Wei, Xiaojie Li, Jingcheng Liu
In this study, amino-functionalized core-shell silica abrasives for silicon wafer Chemical mechanical polishing (CMP) were synthesized via a UV-initiated thiol-ene click reaction. The structures of the abrasives were characterized using Scanning electron microscopy (SEM), Thermogravimetric analysis (TGA) and Fourier transform infrared spectroscopy (FTIR). The effect of abrasives with different acrylamide addition amounts on polishing was investigated. When the acrylamide addition was 50 %, the maximum polishing rate reached 0.33 μm/min, with a corresponding surface roughness of 0.34 nm. Subsequently, the effects of different pH values and polishing rate accelerators on polishing performance were explored. The results revealed the optimal polishing performance when using a slurry with a pH of 11 and a tetramethylammonium hydroxide (TMAH) concentration of 2 %, the maximum polishing rate reached 0.44 μm/min. Experimental results demonstrated that the prepared abrasives achieved high material removal rate and ultra-low surface roughness. X-ray photoelectron spectroscopy (XPS) analysis and density functional theory (DFT) calculations confirmed that amino modification enhanced the adsorption capacity of the abrasives on the silicon wafer surface, while the soft shell effectively reduced mechanical damage to the wafer surface.
{"title":"Preparation of amino-functionalized silica abrasives for chemical mechanical polishing based on Photoinitiated Polymerization","authors":"Qinlong Zhao, Wei Wei, Xiaojie Li, Jingcheng Liu","doi":"10.1016/j.mssp.2026.110420","DOIUrl":"10.1016/j.mssp.2026.110420","url":null,"abstract":"<div><div>In this study, amino-functionalized core-shell silica abrasives for silicon wafer Chemical mechanical polishing (CMP) were synthesized via a UV-initiated thiol-ene click reaction. The structures of the abrasives were characterized using Scanning electron microscopy (SEM), Thermogravimetric analysis (TGA) and Fourier transform infrared spectroscopy (FTIR). The effect of abrasives with different acrylamide addition amounts on polishing was investigated. When the acrylamide addition was 50 %, the maximum polishing rate reached 0.33 μm/min, with a corresponding surface roughness of 0.34 nm. Subsequently, the effects of different pH values and polishing rate accelerators on polishing performance were explored. The results revealed the optimal polishing performance when using a slurry with a pH of 11 and a tetramethylammonium hydroxide (TMAH) concentration of 2 %, the maximum polishing rate reached 0.44 μm/min. Experimental results demonstrated that the prepared abrasives achieved high material removal rate and ultra-low surface roughness. X-ray photoelectron spectroscopy (XPS) analysis and density functional theory (DFT) calculations confirmed that amino modification enhanced the adsorption capacity of the abrasives on the silicon wafer surface, while the soft shell effectively reduced mechanical damage to the wafer surface.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110420"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-13DOI: 10.1016/j.mssp.2025.110397
Mariano Aceves -Mijares , Jorge Pedraza-Chávez , J.Félix Aguilar , J.E. Zamudio-Interian , Oscar Pérez-Díaz , Rubén Manuel López-Guardado
The characterization of integrated electrophotonic circuits—comprising silicon light sources, waveguides, and photodetectors—requires specific metrics for each component. Once integrated, these elements cannot be measured independently. This work proposes a cut-back-like method to estimate optical losses in seamless, all silicon electrophotonic circuits. The integrated transceiver studied here includes a silicon compatible light emitting capacitor (LEC), a silicon nitride waveguide, and a silicon PN photodetector, all fabricated simultaneously to ensure permanent optical alignment. Light emitted from the LEC is coupled into the waveguide and detected as photocurrent at the output. Six seamless chips, each containing identical LECs and photodetectors but waveguides of different lengths, were measured. Using only the experimentally recorded photocurrents, we estimate both the waveguide propagation loss and the LEC's emitted optical power.
{"title":"A cut-back like method to measure the losses in integrated silicon nitride waveguides","authors":"Mariano Aceves -Mijares , Jorge Pedraza-Chávez , J.Félix Aguilar , J.E. Zamudio-Interian , Oscar Pérez-Díaz , Rubén Manuel López-Guardado","doi":"10.1016/j.mssp.2025.110397","DOIUrl":"10.1016/j.mssp.2025.110397","url":null,"abstract":"<div><div>The characterization of integrated electrophotonic circuits—comprising silicon light sources, waveguides, and photodetectors—requires specific metrics for each component. Once integrated, these elements cannot be measured independently. This work proposes a cut-back-like method to estimate optical losses in seamless, all silicon electrophotonic circuits. The integrated transceiver studied here includes a silicon compatible light emitting capacitor (LEC), a silicon nitride waveguide, and a silicon PN photodetector, all fabricated simultaneously to ensure permanent optical alignment. Light emitted from the LEC is coupled into the waveguide and detected as photocurrent at the output. Six seamless chips, each containing identical LECs and photodetectors but waveguides of different lengths, were measured. Using only the experimentally recorded photocurrents, we estimate both the waveguide propagation loss and the LEC's emitted optical power.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110397"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145979469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the post-Moore era, in-memory computing has emerged as a promising approach to overcoming the bottlenecks of the von Neumann architecture. Optoelectronic synaptic devices hold great potential in this field. In this work, we report a gate-tunable three-terminal optoelectronic synaptic device based on an AlGaN/GaN heterostructure, enabling low-power and high-fidelity neuromorphic computing. By exploiting a polarization-engineered two-dimensional electron gas (2DEG) channel and gate-controlled band modulation, the device exhibits essential synaptic functions such as excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and the transition from short-term to long-term memory. Systematic investigations reveal that both optical stimulation and gate bias collaboratively regulate synaptic plasticity. Importantly, the device achieves a potential for low energy consumption per synaptic event and demonstrates robust neuromorphic performance under synaptic weights controlled by different gate bias voltages, reaching an accuracy of 93.4 %. These results highlight the potential of gate-voltage engineering in AlGaN/GaN optoelectronic synapses for next-generation brain-inspired computing systems.
{"title":"Gate-tunable synaptic weight modulation in AlGaN/GaN HEMT optoelectronic synapses for neuromorphic computing","authors":"Leyang Qian , Xuekun Hong , Weiying Qian , Xiangyang Zhang , Guofeng Yang , Jun-Ge Liang , Jian Guo , Xinyi Shan","doi":"10.1016/j.mssp.2026.110446","DOIUrl":"10.1016/j.mssp.2026.110446","url":null,"abstract":"<div><div>In the post-Moore era, in-memory computing has emerged as a promising approach to overcoming the bottlenecks of the von Neumann architecture. Optoelectronic synaptic devices hold great potential in this field. In this work, we report a gate-tunable three-terminal optoelectronic synaptic device based on an AlGaN/GaN heterostructure, enabling low-power and high-fidelity neuromorphic computing. By exploiting a polarization-engineered two-dimensional electron gas (2DEG) channel and gate-controlled band modulation, the device exhibits essential synaptic functions such as excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and the transition from short-term to long-term memory. Systematic investigations reveal that both optical stimulation and gate bias collaboratively regulate synaptic plasticity. Importantly, the device achieves a potential for low energy consumption per synaptic event and demonstrates robust neuromorphic performance under synaptic weights controlled by different gate bias voltages, reaching an accuracy of 93.4 %. These results highlight the potential of gate-voltage engineering in AlGaN/GaN optoelectronic synapses for next-generation brain-inspired computing systems.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110446"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146035055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-11DOI: 10.1016/j.mssp.2026.110419
Linfeng Xie , Fei Wang , Zhe Dou , Jiaqi Liu , Kuan Luo , Yuyao Li
To address the unclear interaction effects of process parameters on the machining quality of silicon carbide (4H-SiC) blind holes during picosecond laser processing, this study conducted a process investigation and optimization using a picosecond laser system, combining single-factor experiments with response surface methodology (RSM). Through single-factor experiments, the effects of single-pulse energy, scanning speed, hatch spacing, and the number of scans on blind hole depth, over-etching groove depth, bottom surface roughness, and material removal rate (MRR) were systematically investigated. Based on the Box-Behnken design (BBD) method, multiple regression models were established, and the interaction effects of process parameters on the machining quality were analyzed in depth. The mean deviations between the predicted and experimental results for four regression models are all below 11 %. Through multi-objective optimization of process parameters using Response Surface Methodology, blind holes with a depth of 252.517 μm and bottom surface roughness of 0.261 μm were successfully fabricated. This research establishes both a theoretical foundation and methodological support for high-precision laser micromachining of 4H-SiC devices.
{"title":"Modeling and multi-objective optimization of picosecond laser machining of blind holes in 4H-SiC using response surface methodology","authors":"Linfeng Xie , Fei Wang , Zhe Dou , Jiaqi Liu , Kuan Luo , Yuyao Li","doi":"10.1016/j.mssp.2026.110419","DOIUrl":"10.1016/j.mssp.2026.110419","url":null,"abstract":"<div><div>To address the unclear interaction effects of process parameters on the machining quality of silicon carbide (4H-SiC) blind holes during picosecond laser processing, this study conducted a process investigation and optimization using a picosecond laser system, combining single-factor experiments with response surface methodology (RSM). Through single-factor experiments, the effects of single-pulse energy, scanning speed, hatch spacing, and the number of scans on blind hole depth, over-etching groove depth, bottom surface roughness, and material removal rate (MRR) were systematically investigated. Based on the Box-Behnken design (BBD) method, multiple regression models were established, and the interaction effects of process parameters on the machining quality were analyzed in depth. The mean deviations between the predicted and experimental results for four regression models are all below 11 %. Through multi-objective optimization of process parameters using Response Surface Methodology, blind holes with a depth of 252.517 μm and bottom surface roughness of 0.261 μm were successfully fabricated. This research establishes both a theoretical foundation and methodological support for high-precision laser micromachining of 4H-SiC devices.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110419"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145979475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Harvesting mechanical energy from ambient environments has emerged as a promising approach to power personal electronic devices and remote sensor networks. Piezoelectric materials, capable of interconverting mechanical strain and electrical energy, demonstrate exceptional potential for energy harvesting applications. Over recent decades, research on energy harvesting through piezoelectric ceramics has garnered significant attention, accompanied by encouraging advancements. Owing to their superior piezoelectric properties and mechanical stability, piezoelectric ceramics exhibit remarkable implementation prospects in practical scenarios. In this review, the mainstream working modes will first be systematically discussed. Subsequently, from a material perspective, substantial efforts have been devoted to tailoring the electrical characteristics of piezoelectric ceramics to further enhance power generation performance. The correlation between processing parameters and the figure of merit (FoM) of piezoelectric ceramics is elucidated in detail. Furthermore, a series of representative applications are highlighted to encapsulate recent progress in this field. Finally, concise commentaries and forward-looking perspectives are provided and overall conclusion. It is anticipated that this comprehensive review will deliver timely updates to researchers in the field and offer strategic guidance for shaping their future investigations.
{"title":"Advances in mechanical energy harvesting using piezoelectric ceramics","authors":"Jihong Liao , Zheyi Tang , Hongjian Zhang , Xiaodong Yan , Yong Zhang","doi":"10.1016/j.mssp.2026.110431","DOIUrl":"10.1016/j.mssp.2026.110431","url":null,"abstract":"<div><div>Harvesting mechanical energy from ambient environments has emerged as a promising approach to power personal electronic devices and remote sensor networks. Piezoelectric materials, capable of interconverting mechanical strain and electrical energy, demonstrate exceptional potential for energy harvesting applications. Over recent decades, research on energy harvesting through piezoelectric ceramics has garnered significant attention, accompanied by encouraging advancements. Owing to their superior piezoelectric properties and mechanical stability, piezoelectric ceramics exhibit remarkable implementation prospects in practical scenarios. In this review, the mainstream working modes will first be systematically discussed. Subsequently, from a material perspective, substantial efforts have been devoted to tailoring the electrical characteristics of piezoelectric ceramics to further enhance power generation performance. The correlation between processing parameters and the figure of merit (FoM) of piezoelectric ceramics is elucidated in detail. Furthermore, a series of representative applications are highlighted to encapsulate recent progress in this field. Finally, concise commentaries and forward-looking perspectives are provided and overall conclusion. It is anticipated that this comprehensive review will deliver timely updates to researchers in the field and offer strategic guidance for shaping their future investigations.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110431"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145979541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-19DOI: 10.1016/j.mssp.2026.110433
Han He , Zijun Chen , Boxi Ye , Liting Liu , Honglong Ning , Xinpeng Wang , Bingsuo Zou , Hao Huang
A trade-off between mobility and stability fundamentally restricts the performance of IGZO thin-film transistor (TFT). Here, a magnetron sputtering-based bilayer IGO/IGZO TFT is designed. The performance of the bilayer IGO/IGZO TFT exhibits significant improvement compared to the IGZO TFT, including a high field-effect mobility that increases from 20.5 to 51.6 cm2/Vs, a low threshold voltage that decreases from 3.0 to −0.1 V, a high on/off current ratio that increases from 1.6×107 to 7.7×107, and a small subthreshold swing that decreases from 0.37 to 0.21 V/dec. This improvement can be attributed to the ultra-thin IGO thin film, which provides a high-speed electron transport channel and reduces the interface defect state density. Additionally, the bilayer IGO/IGZO TFT demonstrates threshold voltage shifts of +1.0 V and −5.9 V under positive and negative bias stress, respectively, which are significantly lower than the +4.6 V and −11.3 V observed in IGZO TFT under identical conditions. The results presented here provide a simple path to design high-performance oxide-based TFT.
{"title":"High-performance bilayer IGO/IGZO thin-film transistors based on defect self-compensation","authors":"Han He , Zijun Chen , Boxi Ye , Liting Liu , Honglong Ning , Xinpeng Wang , Bingsuo Zou , Hao Huang","doi":"10.1016/j.mssp.2026.110433","DOIUrl":"10.1016/j.mssp.2026.110433","url":null,"abstract":"<div><div>A trade-off between mobility and stability fundamentally restricts the performance of IGZO thin-film transistor (TFT). Here, a magnetron sputtering-based bilayer IGO/IGZO TFT is designed. The performance of the bilayer IGO/IGZO TFT exhibits significant improvement compared to the IGZO TFT, including a high field-effect mobility that increases from 20.5 to 51.6 cm<sup>2</sup>/Vs, a low threshold voltage that decreases from 3.0 to −0.1 V, a high on/off current ratio that increases from 1.6×10<sup>7</sup> to 7.7×10<sup>7</sup>, and a small subthreshold swing that decreases from 0.37 to 0.21 V/dec. This improvement can be attributed to the ultra-thin IGO thin film, which provides a high-speed electron transport channel and reduces the interface defect state density. Additionally, the bilayer IGO/IGZO TFT demonstrates threshold voltage shifts of +1.0 V and −5.9 V under positive and negative bias stress, respectively, which are significantly lower than the +4.6 V and −11.3 V observed in IGZO TFT under identical conditions. The results presented here provide a simple path to design high-performance oxide-based TFT.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110433"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146035056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-19DOI: 10.1016/j.mssp.2026.110439
Peter G. Naguib , Ulrike Roesler , Matthias Knapp , Katherine Aristizabal , Jonas Bartsch , Constantin A. Walenta , Tomasz Jewula , Gregor Feiertag
Charge trapping layers suppress parasitic surface conduction on high-resistivity silicon substrates for radiofrequency (RF) applications. This work investigates silicon nitride (SixNy) as a charge trapping layer, using variants deposited by physical vapor deposition (PVD) and plasma-enhanced chemical vapor deposition (PECVD). Coplanar waveguide (CPW) insertion loss is measured to assess RF suitability. Layers are characterized by spectroscopic ellipsometry, Time-of-Flight Secondary-Ion-Mass-Spectroscopy, and Fourier transform infrared spectroscopy. Insertion loss is low for wafers with PVD SixNy and high for PECVD SixNy. CPW measurements at different temperatures show insertion loss increases for PVD SixNy but decreases for PECVD SixNy. Chemical and physical analysis reveals negligible hydrogen in PVD SixNy, while PECVD layers contain hydrogen at least an order of magnitude higher. Finite Element Method (FEM) simulations calculate insertion loss for high and low parasitic surface conductivity scenarios. Hydrogen presence appears to dominate insertion loss differences: traps in SixNy saturate with hydrogen, preventing suppression of parasitic surface conduction. The hypothesized mechanism involves changes in sheet conductivity in the Si carrier's space charge region. Simulations using varying conductivity values show 450 S/m matches PECVD SixNy measurements, while 2 S/m aligns with PVD SixNy. Variations in SixNy thickness do not significantly affect CPW insertion loss in simulations or measurements. Overall, hydrogen-free PVD SixNy is well suited as a charge trapping layer to reduce parasitic surface conduction on high-resistivity Si substrates.
{"title":"A charge trapping layer to suppress RF losses using silicon nitride on high resistivity silicon substrates","authors":"Peter G. Naguib , Ulrike Roesler , Matthias Knapp , Katherine Aristizabal , Jonas Bartsch , Constantin A. Walenta , Tomasz Jewula , Gregor Feiertag","doi":"10.1016/j.mssp.2026.110439","DOIUrl":"10.1016/j.mssp.2026.110439","url":null,"abstract":"<div><div>Charge trapping layers suppress parasitic surface conduction on high-resistivity silicon substrates for radiofrequency (RF) applications. This work investigates silicon nitride (Si<sub>x</sub>N<sub>y</sub>) as a charge trapping layer, using variants deposited by physical vapor deposition (PVD) and plasma-enhanced chemical vapor deposition (PECVD). Coplanar waveguide (CPW) insertion loss is measured to assess RF suitability. Layers are characterized by spectroscopic ellipsometry, Time-of-Flight Secondary-Ion-Mass-Spectroscopy, and Fourier transform infrared spectroscopy. Insertion loss is low for wafers with PVD Si<sub>x</sub>N<sub>y</sub> and high for PECVD Si<sub>x</sub>N<sub>y</sub>. CPW measurements at different temperatures show insertion loss increases for PVD Si<sub>x</sub>N<sub>y</sub> but decreases for PECVD Si<sub>x</sub>N<sub>y</sub>. Chemical and physical analysis reveals negligible hydrogen in PVD Si<sub>x</sub>N<sub>y</sub>, while PECVD layers contain hydrogen at least an order of magnitude higher. Finite Element Method (FEM) simulations calculate insertion loss for high and low parasitic surface conductivity scenarios. Hydrogen presence appears to dominate insertion loss differences: traps in Si<sub>x</sub>N<sub>y</sub> saturate with hydrogen, preventing suppression of parasitic surface conduction. The hypothesized mechanism involves changes in sheet conductivity in the Si carrier's space charge region. Simulations using varying conductivity values show 450 S/m matches PECVD Si<sub>x</sub>N<sub>y</sub> measurements, while 2 S/m aligns with PVD Si<sub>x</sub>N<sub>y</sub>. Variations in Si<sub>x</sub>N<sub>y</sub> thickness do not significantly affect CPW insertion loss in simulations or measurements. Overall, hydrogen-free PVD Si<sub>x</sub>N<sub>y</sub> is well suited as a charge trapping layer to reduce parasitic surface conduction on high-resistivity Si substrates.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110439"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146035053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-09DOI: 10.1016/j.mssp.2026.110408
Seungin Song , Taesu Choi , Youjin Reo, Yong-Young Noh
Transparent semiconductors are in demand for the development of flexible and large-area displays. Copper iodide is a promising p-type semiconductor with high optical transparency and electrical conductivity, where suitable zinc doping can effectively tune the carrier concentration for high-performance thin film transistors. This study proposes a CuI/Zn-doped CuI heterojunction structure for p-type metal halide TFTs. The industry-compatible vapor-deposited heterojunction structure composed of CuI/Zn-doped CuI TFTs offers effective hole transport and a reasonable off-state current through the low conductive Zn-doped CuI channel layer and efficient carrier supply from the highly conductive CuI upper layer. The optimized heterojunction p-type TFTs exhibited a linear field-effect mobility of ∼5 cm2 V−1 s−1 and on/off current ratio of ∼106. This novel heterojunction structure of metal halide TFTs offers a promising pathway for the development of next-generation transparent electronics and displays, incorporating possible vertical-stack integrations and complementary circuits with n-type metal oxide semiconductors.
{"title":"Vapor-deposited transparent copper iodide (CuI)/Zn-doped CuI heterojunction thin film transistors","authors":"Seungin Song , Taesu Choi , Youjin Reo, Yong-Young Noh","doi":"10.1016/j.mssp.2026.110408","DOIUrl":"10.1016/j.mssp.2026.110408","url":null,"abstract":"<div><div>Transparent semiconductors are in demand for the development of flexible and large-area displays. Copper iodide is a promising <em>p</em>-type semiconductor with high optical transparency and electrical conductivity, where suitable zinc doping can effectively tune the carrier concentration for high-performance thin film transistors. This study proposes a CuI/Zn-doped CuI heterojunction structure for <em>p</em>-type metal halide TFTs. The industry-compatible vapor-deposited heterojunction structure composed of CuI/Zn-doped CuI TFTs offers effective hole transport and a reasonable off-state current through the low conductive Zn-doped CuI channel layer and efficient carrier supply from the highly conductive CuI upper layer. The optimized heterojunction <em>p</em>-type TFTs exhibited a linear field-effect mobility of ∼5 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup> and on/off current ratio of ∼10<sup>6</sup>. This novel heterojunction structure of metal halide TFTs offers a promising pathway for the development of next-generation transparent electronics and displays, incorporating possible vertical-stack integrations and complementary circuits with <em>n</em>-type metal oxide semiconductors.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110408"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-05-01Epub Date: 2026-01-06DOI: 10.1016/j.mssp.2026.110406
Liudan Kong, Jiuyang Tang, Jiaying Cao, Yifei Chang, Qingchun Jon Zhang, Pan Liu
With the widespread application of SiC devices in electric vehicles, high-frequency power supplies, and industrial systems, their long-term reliability under dynamic switching stress has attracted increasing attention. This paper investigates the reliability of 1200 V SiC MOSFETs under Dynamic Reverse Bias (DRB) stress, analyzing the impact of structural design and dV/dt on device degradation and failure behavior. Four commercial devices with different gate and termination structures were tested under dV/dt gradients ranging from 25 to 100 V/ns for 1000 h. Firstly, the active region structure influence for device degradation under DRB was investigated. Planar gate and trench gate structures exhibited distinct degradation behaviors, as reflected by different evolutions of the transfer characteristics. Secondly, termination design also plays an important role. The single junction termination extension (JTE) termination failed catastrophically under high-dV/dt. Further failure analysis and TCAD simulations revealed that the electric-field crowding caused localized breakdown. It is found that deep p-type injection or the improved termination with field limiting ring (FLR) added outside the JTE could effectively extend the depletion region, reduce field concentration, thus improving the dynamic robustness. It is concluded that a uniform potential distribution in the termination is essential to suppress local field enhancement and ensure reliable high-dV/dt operation in high-voltage SiC MOSFETs.
随着SiC器件在电动汽车、高频电源和工业系统中的广泛应用，其在动态开关应力下的长期可靠性越来越受到人们的关注。本文研究了1200v SiC mosfet在动态反向偏置（DRB）应力下的可靠性，分析了结构设计和dV/dt对器件退化和失效行为的影响。在25 ~ 100 V/ns的dV/dt梯度下，对4种具有不同栅极和端部结构的商用器件进行了1000 h的测试。首先，研究了有源区结构对器件在DRB下退化的影响。平面栅极和沟槽栅极结构表现出不同的退化行为，这反映在其传递特性的不同演化上。其次，终端设计也起着重要的作用。在高dv /dt条件下，单结端接延伸（JTE）端接失效。进一步的故障分析和TCAD仿真表明，电场拥挤导致局部击穿。研究发现，深p型注入或在JTE外添加场限制环（FLR）的改进端接可以有效地扩大耗尽区，降低场浓度，从而提高动态鲁棒性。结果表明，在高压SiC mosfet中，端部均匀的电位分布对于抑制局部场增强和确保可靠的高dv /dt工作至关重要。
{"title":"DV/dt-Induced degradation and failure mechanisms in 1200 V SiC MOSFETs under dynamic reverse bias stress","authors":"Liudan Kong, Jiuyang Tang, Jiaying Cao, Yifei Chang, Qingchun Jon Zhang, Pan Liu","doi":"10.1016/j.mssp.2026.110406","DOIUrl":"10.1016/j.mssp.2026.110406","url":null,"abstract":"<div><div>With the widespread application of SiC devices in electric vehicles, high-frequency power supplies, and industrial systems, their long-term reliability under dynamic switching stress has attracted increasing attention. This paper investigates the reliability of 1200 V SiC MOSFETs under Dynamic Reverse Bias (DRB) stress, analyzing the impact of structural design and <em>dV/dt</em> on device degradation and failure behavior. Four commercial devices with different gate and termination structures were tested under <em>dV/dt</em> gradients ranging from 25 to 100 V/ns for 1000 h. Firstly, the active region structure influence for device degradation under DRB was investigated. Planar gate and trench gate structures exhibited distinct degradation behaviors, as reflected by different evolutions of the transfer characteristics. Secondly, termination design also plays an important role. The single junction termination extension (JTE) termination failed catastrophically under high-<em>dV/dt</em>. Further failure analysis and TCAD simulations revealed that the electric-field crowding caused localized breakdown. It is found that deep p-type injection or the improved termination with field limiting ring (FLR) added outside the JTE could effectively extend the depletion region, reduce field concentration, thus improving the dynamic robustness. It is concluded that a uniform potential distribution in the termination is essential to suppress local field enhancement and ensure reliable high-<em>dV/dt</em> operation in high-voltage SiC MOSFETs.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"206 ","pages":"Article 110406"},"PeriodicalIF":4.6,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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