Fully Depleted Silicon-On-Insulator (FD-SOI) technology continues to evolve, driven by the need to enhance carrier mobility through innovative channel engineering. This involves, in particular, replacing silicon with SiGe alloys, and introducing controlled compressive strain to improve the performances of both nMOS and pMOS transistors. However, conventional approaches employing pseudo-substrates on silicon remain constrained by Ge concentrations not exceeding 30 % and dislocation densities typically around which limit further performance gains. In this study, we address these limitations by developing a methodology aimed at increasing the Ge concentration in SiGe layers while suppressing defect formation. Our approach combines epitaxial growth with subsequent Ge condensation on SOI substrates, implemented on 300 mm wafer and under industrial process conditions. We demonstrate that initiating the process with a ∼20 nm-thick epitaxial SiGe layer containing ∼20 % Ge is critical for ensuring high structural quality during the high temperature condensation step. This optimized strategy leads to the formation of Ge-rich SiGe pseudo-substrates exhibiting drastically reduced dislocation densities. These layers are fully strained and are able to support high temperature annealing (∼1060 °C needed for the subsequent CMOS fabrication step) without any relaxation.
The resulting ultra-thin, defect-free, and fully strained SiGe layers exhibit high Ge content and superior optoelectronic quality, opening new opportunities for the integration of advanced SiGe channels in next-generation FD-SOI technology.
{"title":"Advanced process for the fabrication of defect-free Ge-rich SiGe on insulator layers","authors":"Anne-Flore Mallet , Olivier Gourhant , Adam Arette-Hourquet , Mansour Aouassa , Christophe Duluard , Romain Duru , Luc Favre , Isabelle Berbezier","doi":"10.1016/j.mssp.2026.110442","DOIUrl":"10.1016/j.mssp.2026.110442","url":null,"abstract":"<div><div>Fully Depleted Silicon-On-Insulator (FD-SOI) technology continues to evolve, driven by the need to enhance carrier mobility through innovative channel engineering. This involves, in particular, replacing silicon with SiGe alloys, and introducing controlled compressive strain to improve the performances of both nMOS and pMOS transistors. However, conventional approaches employing <span><math><mrow><msub><mrow><mi>S</mi><mi>i</mi></mrow><mrow><mn>1</mn><mo>−</mo><mi>x</mi></mrow></msub><msub><mrow><mi>G</mi><mi>e</mi></mrow><mi>x</mi></msub></mrow></math></span> pseudo-substrates on silicon remain constrained by Ge concentrations not exceeding 30 % and dislocation densities typically around <span><math><mrow><msup><mn>10</mn><mn>6</mn></msup><msup><mrow><mi>c</mi><mi>m</mi></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup></mrow></math></span> which limit further performance gains. In this study, we address these limitations by developing a methodology aimed at increasing the Ge concentration in SiGe layers while suppressing defect formation. Our approach combines epitaxial growth with subsequent Ge condensation on SOI substrates, implemented on 300 mm wafer and under industrial process conditions. We demonstrate that initiating the process with a ∼20 nm-thick epitaxial SiGe layer containing ∼20 % Ge is critical for ensuring high structural quality during the high temperature condensation step. This optimized strategy leads to the formation of Ge-rich SiGe pseudo-substrates exhibiting drastically reduced dislocation densities. These layers are fully strained and are able to support high temperature annealing (∼1060 °C needed for the subsequent CMOS fabrication step) without any relaxation.</div><div>The resulting ultra-thin, defect-free, and fully strained SiGe layers exhibit high Ge content and superior optoelectronic quality, opening new opportunities for the integration of advanced SiGe channels in next-generation FD-SOI technology.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110442"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146190623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-02-05DOI: 10.1016/j.mssp.2026.110499
Xiaoyu Fan , Ziwei Chen , Yue Yao
NO2 is a pervasive pollutant gas that poses significant threats to both crop growth and human health. MoS2 gas sensors are still plagued by insufficient sensitivity in room-temperature (RT), complex environments, such as greenhouses and industrial settings. The construction of heterojunction composites has been demonstrated to be an effective strategy for enhancing the performance of MoS2. This study successfully fabricated MoS2/MoO2 and MoS2/MoO3 multiphase heterojunctions (labeled MoO-20) with three-dimensional nanoflower structures via a simple air calcination method. In dynamic testing, the material achieved an actual detection limit of 2.2 ppb for NO2 (with a response value of 8.79%), while its theoretical detection limit reached as low as 0.82 ppb. Concurrently, MoO-20 has the advantage of rapid response/recovery, with the response and recovery times of 17/11 s to 5 ppm NO2. Furthermore, the sensor exhibits noteworthy repeatability, selectivity, and long-term stability. Analyses using HRTEM-elemental mapping, XPS, UV-vis DRS, Raman, and UPS reveal that the enhanced gas-sensing performance is due to the multiphase heterojunction's abundant active sites and optimized internal electric field. The multiphase heterojunction retains both the high conductivity and reaction activity of the MoS2 component and the strong gas adsorption and catalytic ability of the MoO3 component. DFT calculations confirm that multiphase heterojunction interfacial charge redistribution and optimized adsorption geometry significantly enhance the adsorption strength and charge transfer capability for NO2. This progress has good application prospects in the next-generation intelligent greenhouses and industrial monitoring systems.
{"title":"A high-performance room-temperature NO2 gas sensor based on MoS2/MoOx multiphase heterojunction: Achieving fast response and low detection limit","authors":"Xiaoyu Fan , Ziwei Chen , Yue Yao","doi":"10.1016/j.mssp.2026.110499","DOIUrl":"10.1016/j.mssp.2026.110499","url":null,"abstract":"<div><div>NO<sub>2</sub> is a pervasive pollutant gas that poses significant threats to both crop growth and human health. MoS<sub>2</sub> gas sensors are still plagued by insufficient sensitivity in room-temperature (RT), complex environments, such as greenhouses and industrial settings. The construction of heterojunction composites has been demonstrated to be an effective strategy for enhancing the performance of MoS<sub>2</sub>. This study successfully fabricated MoS<sub>2</sub>/MoO<sub>2</sub> and MoS<sub>2</sub>/MoO<sub>3</sub> multiphase heterojunctions (labeled MoO-20) with three-dimensional nanoflower structures via a simple air calcination method. In dynamic testing, the material achieved an actual detection limit of 2.2 ppb for NO<sub>2</sub> (with a response value of 8.79%), while its theoretical detection limit reached as low as 0.82 ppb. Concurrently, MoO-20 has the advantage of rapid response/recovery, with the response and recovery times of 17/11 s to 5 ppm NO<sub>2</sub>. Furthermore, the sensor exhibits noteworthy repeatability, selectivity, and long-term stability. Analyses using HRTEM-elemental mapping, XPS, UV-vis DRS, Raman, and UPS reveal that the enhanced gas-sensing performance is due to the multiphase heterojunction's abundant active sites and optimized internal electric field. The multiphase heterojunction retains both the high conductivity and reaction activity of the MoS<sub>2</sub> component and the strong gas adsorption and catalytic ability of the MoO<sub>3</sub> component. DFT calculations confirm that multiphase heterojunction interfacial charge redistribution and optimized adsorption geometry significantly enhance the adsorption strength and charge transfer capability for NO<sub>2</sub>. This progress has good application prospects in the next-generation intelligent greenhouses and industrial monitoring systems.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110499"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146190692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-02-01DOI: 10.1016/j.mssp.2026.110479
Peipei Xue , Chong Wu , Yong Zhang , Xueping Zhao , Hai Zhang , Pucun Bai
Amorphous Ga2O3 (a-Ga2O3) films have a wide bandgap and can be fabricated at room temperature, making them ideal for constructing heterojunctions with p-type conductive films to achieve broadband ultraviolet (UV) photodetection. However, the performance of single-component a-Ga2O3 devices is often constrained by high dark current and slow response. In this work, a high-performance self-powered UV γ-CuI/a-Ga2O3 heterojunction photodetector was fabricated using physical vapor transport and magnetron sputtering techniques. The obtained epitaxial γ-CuI (111) film exhibits a step-like surface morphology and a bandgap of 3.01 eV. Additionally, the a-Ga2O3 layer forms uniform nanoclusters with a bandgap of 4.93 eV. The combination of epitaxial γ-CuI (111) film and a-Ga2O3 layer enables broadband UV absorption. More importantly, under self-powered operation (0 V), the device achieves an ultralow dark current of 1.18 × 10−12 A. Under 254-nm illumination, it exhibits a high photocurrent-to-dark current ratio of 2.19 × 103, a responsivity of 9.63 × 10−2 mA/W, a specific detectivity of 2.35 × 1010 Jones, and rapid response times, with rise and decay times of 2.20 and 0.21 s, respectively. This work not only verifies the feasibility of integrating epitaxial γ-CuI with a-Ga2O3 for high-performance photodetectors but also provides an effective strategy for developing a-Ga2O3-based self-powered UV photodetectors with ultralow dark current.
{"title":"Fabrication of amorphous Ga2O3 and epitaxial γ-CuI heterojunctions for broadband self-powered ultraviolet photodetectors","authors":"Peipei Xue , Chong Wu , Yong Zhang , Xueping Zhao , Hai Zhang , Pucun Bai","doi":"10.1016/j.mssp.2026.110479","DOIUrl":"10.1016/j.mssp.2026.110479","url":null,"abstract":"<div><div>Amorphous Ga<sub>2</sub>O<sub>3</sub> (a-Ga<sub>2</sub>O<sub>3</sub>) films have a wide bandgap and can be fabricated at room temperature, making them ideal for constructing heterojunctions with p-type conductive films to achieve broadband ultraviolet (UV) photodetection. However, the performance of single-component a-Ga<sub>2</sub>O<sub>3</sub> devices is often constrained by high dark current and slow response. In this work, a high-performance self-powered UV γ-CuI/a-Ga<sub>2</sub>O<sub>3</sub> heterojunction photodetector was fabricated using physical vapor transport and magnetron sputtering techniques. The obtained epitaxial γ-CuI (111) film exhibits a step-like surface morphology and a bandgap of 3.01 eV. Additionally, the a-Ga<sub>2</sub>O<sub>3</sub> layer forms uniform nanoclusters with a bandgap of 4.93 eV. The combination of epitaxial γ-CuI (111) film and a-Ga<sub>2</sub>O<sub>3</sub> layer enables broadband UV absorption. More importantly, under self-powered operation (0 V), the device achieves an ultralow dark current of 1.18 × 10<sup>−12</sup> A. Under 254-nm illumination, it exhibits a high photocurrent-to-dark current ratio of 2.19 × 10<sup>3</sup>, a responsivity of 9.63 × 10<sup>−2</sup> mA/W, a specific detectivity of 2.35 × 10<sup>10</sup> Jones, and rapid response times, with rise and decay times of 2.20 and 0.21 s, respectively. This work not only verifies the feasibility of integrating epitaxial γ-CuI with a-Ga<sub>2</sub>O<sub>3</sub> for high-performance photodetectors but also provides an effective strategy for developing a-Ga<sub>2</sub>O<sub>3</sub>-based self-powered UV photodetectors with ultralow dark current.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110479"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146190699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-02-09DOI: 10.1016/j.mssp.2026.110493
Atsuki Morimoto , Linyu Huang , Kota Igura , Takamitsu Ishiyama , Dong Wang , Kaoru Toko , Keisuke Yamamoto
Fabrication of germanium (Ge) thin-film transistors (TFTs) at low temperature on an insulator is essential for the realization of monolithic three-dimensional large-scale integration and flexible electronic devices. We investigated a complementary metal-oxide semiconductor (CMOS) inverter comprising an accumulation-mode p-channel (p-) TFT and inversion-mode n-channel (n-) TFT on poly-crystalline Ge formed on a glass substrate by solid-phase crystallization. We successfully fabricated accumulation-mode p-TFT and inversion-mode n-TFT on the same chip at low temperature (<500 °C). We also confirmed inverter operation with DC and pulse signals up to 10 kHz. Hydrogen (H) introduction was carried out to improve the CMOS characteristics. The on/off ratios of the p- and n-channel TFTs with forming gas (H2/Ar) annealing were up to five times those with nitrogen (N2) annealing, and supply voltage (VDD) loss in the output signal (VOUT) was suppressed. We suggested that this improvement is due to a reduction in hole density through the influence of hydrogen annealing. These results pave the way for monolithic three-dimensional large-scale integration and flexible device applications on poly-crystalline Ge.
{"title":"Demonstration of CMOS inverter on poly-crystalline Ge on glass","authors":"Atsuki Morimoto , Linyu Huang , Kota Igura , Takamitsu Ishiyama , Dong Wang , Kaoru Toko , Keisuke Yamamoto","doi":"10.1016/j.mssp.2026.110493","DOIUrl":"10.1016/j.mssp.2026.110493","url":null,"abstract":"<div><div>Fabrication of germanium (Ge) thin-film transistors (TFTs) at low temperature on an insulator is essential for the realization of monolithic three-dimensional large-scale integration and flexible electronic devices. We investigated a complementary metal-oxide semiconductor (CMOS) inverter comprising an accumulation-mode p-channel (p-) TFT and inversion-mode n-channel (n-) TFT on poly-crystalline Ge formed on a glass substrate by solid-phase crystallization. We successfully fabricated accumulation-mode p-TFT and inversion-mode n-TFT on the same chip at low temperature (<500 °C). We also confirmed inverter operation with DC and pulse signals up to 10 kHz. Hydrogen (H) introduction was carried out to improve the CMOS characteristics. The on/off ratios of the p- and n-channel TFTs with forming gas (H<sub>2</sub>/Ar) annealing were up to five times those with nitrogen (N<sub>2</sub>) annealing, and supply voltage (<em>V</em><sub>DD</sub>) loss in the output signal (<em>V</em><sub>OUT</sub>) was suppressed. We suggested that this improvement is due to a reduction in hole density through the influence of hydrogen annealing. These results pave the way for monolithic three-dimensional large-scale integration and flexible device applications on poly-crystalline Ge.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110493"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of flexible light-emitting devices with reliable colour tunability, mechanical durability, and high-voltage stability remains a significant challenge due to complex fabrication routes, inefficient thermal management, and limited control over emission characteristics in existing device architectures. In this work, we address these limitations by fabricating the flexible colour-tunable LED devices on indium tin oxide (ITO)-coated polyethylene terephthalate (PET) substrates, namely Device D1 (ITO/ZnO NRs/Ag), Device D2 (ITO/ZnO NRs–CdS/Ag), Device D3 (ITO/ZnO NRs–CuO/Ag), and Device D4 (ITO/ZnO NRs–CdS–CuO/Ag). Vertically aligned ZnO NRs were synthesized using hydrothermal method, while CdS and CuO nanoparticles were prepared via sol–gel processes, enabling a simple, cost-effective, and scalable fabrication strategy. Structural and compositional investigations using FESEM, EDX, AFM, UV–Vis, XRD, FTIR, XPS, and PL techniques confirmed the formation of ZnO–CdS–CuO heterostructures, revealing their crystallinity, chemical structure and bonding, elemental composition, and the presence of various defect states. The current–voltage (I–V) characteristics were performed for different LED devices D1, D2, D3, and D4 and their corresponding turn-on voltages were found to be 3.11 V, 2.45 V, 2.19 V, and 1.87 V, respectively. Multicolour electroluminescence was obtained by selectively combining ZnO, CdS, and CuO semiconductors. Under a forward bias ranging from 4 V to 50 V, the EL spectra displayed distinct emission peaks at ∼381 nm (UV-violet), ∼523 nm (green), ∼613 nm (orange), and ∼671 nm (deep red) corresponding to devices D1, D2, D3, and D4, respectively, spanning a wide UV–visible spectral range. The maximum EL intensities recorded at 35 V were ∼2123 a.u., ∼4359 a.u., ∼6572 a.u., and ∼10900 a.u. for D1, D2, D3, and D4, respectively. Device D4 showed excellent mechanical flexibility and operational stability, retaining stable red emission at bending angles of 30°, 60°, 90°, 120°, and 180° (flat condition) and after 1000 repeated bending cycles at a fixed 30° angle, with no significant change in emission intensity or peak position, and also withstanding high operating voltages up to 35 V without failure. Overall, the demonstrated colour tunability, mechanical flexibility, and high-voltage stability suggest that Device D4 is highly competitive with existing flexible LED technologies and holds strong potential for industrial applications in flexible, colour-tunable LED devices.
{"title":"Flexible multi-colour LEDs and junction-free emission","authors":"Neetu Verma , Manisha , Garima Poply , Tanmoy Majumder , Jugal Bori , Deepak Kumar , Jehova Jire L. Hmar","doi":"10.1016/j.mssp.2026.110481","DOIUrl":"10.1016/j.mssp.2026.110481","url":null,"abstract":"<div><div>The development of flexible light-emitting devices with reliable colour tunability, mechanical durability, and high-voltage stability remains a significant challenge due to complex fabrication routes, inefficient thermal management, and limited control over emission characteristics in existing device architectures. In this work, we address these limitations by fabricating the flexible colour-tunable LED devices on indium tin oxide (ITO)-coated polyethylene terephthalate (PET) substrates, namely Device D1 (ITO/ZnO NRs/Ag), Device D2 (ITO/ZnO NRs–CdS/Ag), Device D3 (ITO/ZnO NRs–CuO/Ag), and Device D4 (ITO/ZnO NRs–CdS–CuO/Ag). Vertically aligned ZnO NRs were synthesized using hydrothermal method, while CdS and CuO nanoparticles were prepared via sol–gel processes, enabling a simple, cost-effective, and scalable fabrication strategy. Structural and compositional investigations using FESEM, EDX, AFM, UV–Vis, XRD, FTIR, XPS, and PL techniques confirmed the formation of ZnO–CdS–CuO heterostructures, revealing their crystallinity, chemical structure and bonding, elemental composition, and the presence of various defect states. The current–voltage (I–V) characteristics were performed for different LED devices D1, D2, D3, and D4 and their corresponding turn-on voltages were found to be 3.11 V, 2.45 V, 2.19 V, and 1.87 V, respectively. Multicolour electroluminescence was obtained by selectively combining ZnO, CdS, and CuO semiconductors. Under a forward bias ranging from 4 V to 50 V, the EL spectra displayed distinct emission peaks at ∼381 nm (UV-violet), ∼523 nm (green), ∼613 nm (orange), and ∼671 nm (deep red) corresponding to devices D1, D2, D3, and D4, respectively, spanning a wide UV–visible spectral range. The maximum EL intensities recorded at 35 V were ∼2123 a.u., ∼4359 a.u., ∼6572 a.u., and ∼10900 a.u. for D1, D2, D3, and D4, respectively. Device D4 showed excellent mechanical flexibility and operational stability, retaining stable red emission at bending angles of 30°, 60°, 90°, 120°, and 180° (flat condition) and after 1000 repeated bending cycles at a fixed 30° angle, with no significant change in emission intensity or peak position, and also withstanding high operating voltages up to 35 V without failure. Overall, the demonstrated colour tunability, mechanical flexibility, and high-voltage stability suggest that Device D4 is highly competitive with existing flexible LED technologies and holds strong potential for industrial applications in flexible, colour-tunable LED devices.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110481"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146081128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pad conditioning is a key process for maintaining a stable material removal rate (MRR) in chemical mechanical polishing (CMP) by regenerating the microtexture of degraded polishing pad surfaces. However, the complex and nonlinear relationship between pad surface microtexture evolution and MRR keeps pad conditioning dependent on empirical approaches. Therefore, this study quantitatively investigates the spatiotemporal evolution of surface texture throughout the pad lifecycle and its impact on MRR, using a composite roughness parameter (Rq/Rp) that directly correlates with the material removal function. The results revealed that once sufficient pad conditioning aggressiveness was ensured, the pad reached a steady state characterized by uniform surface texture across the entire radius. Subsequently, both the texture and MRR remained constant even with increases in pad conditioning downforce and time. Notably, the decoupling behavior of Rp observed within the Rq/Rp convergence regime implies that independent control of asperity height is achievable without compromising the MRR. Furthermore, long-term pad conditioning experiments demonstrated that although the pad cut rate exhibited up to a sixfold difference depending on the pad conditioning disc type, the terminal surface texture converged to the same steady state response governed by intrinsic pad properties. This paper establishes quantitative guidelines for the conditioning endpoint and provides new insights into polishing pad surface microtexture control.
{"title":"Convergence behavior of pad surface microtexture under CMP conditioning","authors":"Jongmin Jeong, Yeongil Shin, Jiho Shin, Haedo Jeong","doi":"10.1016/j.mssp.2026.110512","DOIUrl":"10.1016/j.mssp.2026.110512","url":null,"abstract":"<div><div>Pad conditioning is a key process for maintaining a stable material removal rate (MRR) in chemical mechanical polishing (CMP) by regenerating the microtexture of degraded polishing pad surfaces. However, the complex and nonlinear relationship between pad surface microtexture evolution and MRR keeps pad conditioning dependent on empirical approaches. Therefore, this study quantitatively investigates the spatiotemporal evolution of surface texture throughout the pad lifecycle and its impact on MRR, using a composite roughness parameter (Rq/Rp) that directly correlates with the material removal function. The results revealed that once sufficient pad conditioning aggressiveness was ensured, the pad reached a steady state characterized by uniform surface texture across the entire radius. Subsequently, both the texture and MRR remained constant even with increases in pad conditioning downforce and time. Notably, the decoupling behavior of Rp observed within the Rq/Rp convergence regime implies that independent control of asperity height is achievable without compromising the MRR. Furthermore, long-term pad conditioning experiments demonstrated that although the pad cut rate exhibited up to a sixfold difference depending on the pad conditioning disc type, the terminal surface texture converged to the same steady state response governed by intrinsic pad properties. This paper establishes quantitative guidelines for the conditioning endpoint and provides new insights into polishing pad surface microtexture control.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110512"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-02-04DOI: 10.1016/j.mssp.2026.110494
Yudong Li , Han Gao , Xuanling Zhou, Xinbo Zou
{"title":"GaN-based high output voltage binary and ternary digital components achieved by neutral beam etching","authors":"Yudong Li , Han Gao , Xuanling Zhou, Xinbo Zou","doi":"10.1016/j.mssp.2026.110494","DOIUrl":"10.1016/j.mssp.2026.110494","url":null,"abstract":"","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110494"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-01-29DOI: 10.1016/j.mssp.2026.110476
Pin-Hong He , Ching-Ting Lee , Jone-Fang Chen , Hsin-Ying Lee
In this study, the monolithic inverters with complementary metal-oxide-semiconductor (CMOS) structure were fabricated by integrating depletion-mode (D-mode) and enhancement-mode (E-mode) GaN-based fin-gated multichannel metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). The gate oxide layer of the D-mode devices was directly grown using a photoelectrochemical (PEC) oxidation method, while the gate oxide layers of the E-mode devices were fabricated using the PEC etching method and the ferroelectric charge trap gate-stacked Al2O3/HfO2/LiNbO3 oxide layers. To achieve unskewed inverter operation, the drain-source current of the D-mode devices was controlled by modulating the depth of gate-recessed regions created simultaneously during gate oxide layer growth. To study the impact of source field plates in D-mode and E-mode GaN-based fin-gated multichannel MOSHEMTs and the resulting monolithic inverters, source field plates with various lengths were incorporated. Their associated drain-source breakdown voltage increased, while the other characteristics were almost unaffected by the incorporation of the source field plate. However, the enhanced drain-source breakdown voltage was influenced by the length of the source field plate. It was found that the maximum drain-source breakdown voltage was obtained by placing the source field plate edge on the midpoint between the drain and gate. However, the high-frequency performance of the monolithic inverters was degraded by incorporating a long source field plate due to the induced additional parasitic capacitance.
{"title":"Monolithic inverters using GaN-based fin-gated multichannel complementary metal-oxide-semiconductor high-electron mobility transistors with source field plate","authors":"Pin-Hong He , Ching-Ting Lee , Jone-Fang Chen , Hsin-Ying Lee","doi":"10.1016/j.mssp.2026.110476","DOIUrl":"10.1016/j.mssp.2026.110476","url":null,"abstract":"<div><div>In this study, the monolithic inverters with complementary metal-oxide-semiconductor (CMOS) structure were fabricated by integrating depletion-mode (D-mode) and enhancement-mode (E-mode) GaN-based fin-gated multichannel metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). The gate oxide layer of the D-mode devices was directly grown using a photoelectrochemical (PEC) oxidation method, while the gate oxide layers of the E-mode devices were fabricated using the PEC etching method and the ferroelectric charge trap gate-stacked Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/LiNbO<sub>3</sub> oxide layers. To achieve unskewed inverter operation, the drain-source current of the D-mode devices was controlled by modulating the depth of gate-recessed regions created simultaneously during gate oxide layer growth. To study the impact of source field plates in D-mode and E-mode GaN-based fin-gated multichannel MOSHEMTs and the resulting monolithic inverters, source field plates with various lengths were incorporated. Their associated drain-source breakdown voltage increased, while the other characteristics were almost unaffected by the incorporation of the source field plate. However, the enhanced drain-source breakdown voltage was influenced by the length of the source field plate. It was found that the maximum drain-source breakdown voltage was obtained by placing the source field plate edge on the midpoint between the drain and gate. However, the high-frequency performance of the monolithic inverters was degraded by incorporating a long source field plate due to the induced additional parasitic capacitance.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110476"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146081130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-01-30DOI: 10.1016/j.mssp.2026.110471
Nianshun Zhao , Sha Lu , Juan Hu , Qin Gao , Li Wang , Taiming Sun , Jie Bao , Xiaofan Zheng , Zheng li
Dielectric ceramics have advantages such as high power density and fast charge-discharge speed, but their limited energy storage performance (ESP) under moderate electric fields limits their applications. In this study, Ba0.6Ag0.4Mg0.2Nb0.8O3 (BAMN) was introduced into 0.6Na0.5Bi0.5TiO3-0.4Sr0.7Bi0.2TiO3 (NBT-SBT) matrix. A systematic investigation was conducted into how BAMN affected the crystal structure, micromorphology, and electrical properties. Results indicate that BAMN addition decreases grain dimensions and enhances the development of polar nanodomains (PNRs). The sample with x = 0.09 demonstrates a recoverable energy storage density (Wrec) of 3.25 J/cm3 and an efficiency (η) of 82.15 % under an electric field of 230 kV/cm, along with outstanding thermal stability across the temperature range of 20–160 °C, stable performance over frequencies from 1 to 500 Hz, and robust fatigue resistance up to 105 cycles. Additionally, the ceramic with x = 0.09 exhibits short discharge time (t0.9 = 49.2 ns), large current density (CD = 1078.6 A/cm2), and power density (PD = 86.3 MW/cm3) at 160 kV/cm. The findings open up new avenues for innovating novel lead-free ceramics with superior ESP.
{"title":"Enhanced energy storage properties achieved in (1-x)(0.6Na0.5Bi0.5TiO3-0.4Sr0.7Bi0.2TiO3)-xBa0.6Ag0.4Mg0.2Nb0.8O3 ceramics at moderate electric field","authors":"Nianshun Zhao , Sha Lu , Juan Hu , Qin Gao , Li Wang , Taiming Sun , Jie Bao , Xiaofan Zheng , Zheng li","doi":"10.1016/j.mssp.2026.110471","DOIUrl":"10.1016/j.mssp.2026.110471","url":null,"abstract":"<div><div>Dielectric ceramics have advantages such as high power density and fast charge-discharge speed, but their limited energy storage performance (ESP) under moderate electric fields limits their applications. In this study, Ba<sub>0.6</sub>Ag<sub>0.4</sub>Mg<sub>0.2</sub>Nb<sub>0.8</sub>O<sub>3</sub> (BAMN) was introduced into 0.6Na<sub>0.5</sub>Bi<sub>0.5</sub>TiO<sub>3</sub>-0.4Sr<sub>0.7</sub>Bi<sub>0.2</sub>TiO<sub>3</sub> (NBT-SBT) matrix. A systematic investigation was conducted into how BAMN affected the crystal structure, micromorphology, and electrical properties. Results indicate that BAMN addition decreases grain dimensions and enhances the development of polar nanodomains (PNRs). The sample with <em>x</em> = 0.09 demonstrates a recoverable energy storage density (<em>W</em><sub>rec</sub>) of 3.25 J/cm<sup>3</sup> and an efficiency (<em>η</em>) of 82.15 % under an electric field of 230 kV/cm, along with outstanding thermal stability across the temperature range of 20–160 °C, stable performance over frequencies from 1 to 500 Hz, and robust fatigue resistance up to 10<sup>5</sup> cycles. Additionally, the ceramic with <em>x</em> = 0.09 exhibits short discharge time (<em>t</em><sub>0.9</sub> = 49.2 ns), large current density (<em>C</em><sub>D</sub> = 1078.6 A/cm<sup>2</sup>), and power density (<em>P</em><sub>D</sub> = 86.3 MW/cm<sup>3</sup>) at 160 kV/cm. The findings open up new avenues for innovating novel lead-free ceramics with superior ESP.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110471"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146081132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-06-01Epub Date: 2026-02-09DOI: 10.1016/j.mssp.2026.110482
Chaofan Pan , Xi Jiang , Hao Niu , Song Yuan , Xiangdong Li , Shuzhen You , Xiaowu Gong , Jun Wang
Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) frequently encounter overcurrent stress that can exceed their rated current during abnormal operating conditions, such as system short-circuit faults or motor-drive stalls. Such events induce severe self-heating and intensified electric-field stress, which may degrade device performance or even trigger catastrophic failure. However, the underlying failure mechanisms of Schottky-gate GaN HEMTs (SP-HEMTs) and Ohmic-gate hybrid-drain gate-injection transistors (HD-GITs) under overcurrent conditions are not yet fully clarified. This work investigates and compares their failure mechanisms under controlled overcurrent stress. The influence of device structure is analyzed to understand the underlying physical failure mechanisms. The results indicate that the source field plate, drain P-GaN structure, overcurrent peak amplitude and pulse duration are the main factors determining the failure modes. Experimental characterization combined with TCAD simulation reveals that localized thermal accumulation and electric-field crowding in the access region serve as the main cause of device failure. In HD-GITs, the hole injection from the drain P-GaN is identified as the main mechanism that leads to the breakdown between the drain and the substrate.
{"title":"Comparative study on the overcurrent failure mechanisms of ohmic-gate and Schottky-gate GaN HEMTs","authors":"Chaofan Pan , Xi Jiang , Hao Niu , Song Yuan , Xiangdong Li , Shuzhen You , Xiaowu Gong , Jun Wang","doi":"10.1016/j.mssp.2026.110482","DOIUrl":"10.1016/j.mssp.2026.110482","url":null,"abstract":"<div><div>Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) frequently encounter overcurrent stress that can exceed their rated current during abnormal operating conditions, such as system short-circuit faults or motor-drive stalls. Such events induce severe self-heating and intensified electric-field stress, which may degrade device performance or even trigger catastrophic failure. However, the underlying failure mechanisms of Schottky-gate GaN HEMTs (SP-HEMTs) and Ohmic-gate hybrid-drain gate-injection transistors (HD-GITs) under overcurrent conditions are not yet fully clarified. This work investigates and compares their failure mechanisms under controlled overcurrent stress. The influence of device structure is analyzed to understand the underlying physical failure mechanisms. The results indicate that the source field plate, drain P-GaN structure, overcurrent peak amplitude and pulse duration are the main factors determining the failure modes. Experimental characterization combined with TCAD simulation reveals that localized thermal accumulation and electric-field crowding in the access region serve as the main cause of device failure. In HD-GITs, the hole injection from the drain P-GaN is identified as the main mechanism that leads to the breakdown between the drain and the substrate.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"207 ","pages":"Article 110482"},"PeriodicalIF":4.6,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146190344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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