Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838362
Abdullah G. Alharbi, B. Nasri, Ting Wu, Davood Shahrjerdi
We discuss two emerging technologies that are central for realizing an optically powered flexible bioelectronic system. First, we discuss layer transfer through controlled spalling technology for producing high-performance flexible electronics. We present three examples: (1) advanced-node ultra-thin body silicon integrated circuits on plastic, (2) strain engineering in flexible electronics, and (3) flexible GaAs photovoltaic energy harvesters. Second, a 4-terminal biosensor is presented that is compatible with ultra-thin body silicon CMOS technology. Through in vitro glucose sensing, we demonstrate that the 4-terminal integrated biosensor enables the amplification of biochemical signals at the device level. These advanced technologies can give rise to an unprecedented boost in the performance and functionality of next-generation wearable devices.
{"title":"Advanced integrated sensor and layer transfer technologies for wearable bioelectronics","authors":"Abdullah G. Alharbi, B. Nasri, Ting Wu, Davood Shahrjerdi","doi":"10.1109/IEDM.2016.7838362","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838362","url":null,"abstract":"We discuss two emerging technologies that are central for realizing an optically powered flexible bioelectronic system. First, we discuss layer transfer through controlled spalling technology for producing high-performance flexible electronics. We present three examples: (1) advanced-node ultra-thin body silicon integrated circuits on plastic, (2) strain engineering in flexible electronics, and (3) flexible GaAs photovoltaic energy harvesters. Second, a 4-terminal biosensor is presented that is compatible with ultra-thin body silicon CMOS technology. Through in vitro glucose sensing, we demonstrate that the 4-terminal integrated biosensor enables the amplification of biochemical signals at the device level. These advanced technologies can give rise to an unprecedented boost in the performance and functionality of next-generation wearable devices.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114063645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838407
A. Dzurak
This paper reviews the current state of development of spin-based quantum bits (qubits) based on silicon metal-oxide-semiconductor (SiMOS) devices, including both single phosphorus donor qubits in silicon and gate-defined quantum dot qubits that are compatible with CMOS manufacturing.
{"title":"Spin-based quantum computing in silicon CMOS-compatible platforms","authors":"A. Dzurak","doi":"10.1109/IEDM.2016.7838407","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838407","url":null,"abstract":"This paper reviews the current state of development of spin-based quantum bits (qubits) based on silicon metal-oxide-semiconductor (SiMOS) devices, including both single phosphorus donor qubits in silicon and gate-defined quantum dot qubits that are compatible with CMOS manufacturing.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116727216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838527
M. Trifunovic, P. Sberna, T. Shimoda, R. Ishihara
Solution-processing has gained widespread attention over the past years due to their potential low-cost advantage in terms of fabrication of electronics as well as application to flexible electronics. Cyclopentasilane is used for the solution-based processing of silicon. As a liquid, the material has the potential to be applied directly on low-cost flexible substrates that generally have a low thermal budget, by annealing the liquid using an excimer laser treatment. So far, electronics based on this material have only been demonstrated on rigid and high cost substrates. In this work, silicon has been applied as a solution on top of a paper substrate and processed into PMOS and NMOS thin-film transistors (TFTs). The maximum fabrication temperature was limited to approximately 100° C. By being able to fabricate devices on top of a paper substrate, a pathway opens towards new applications that combine the true low-cost and biodegradability with the high performance of silicon electronics.
{"title":"Polycrystalline silicon TFTs on a paper substrate using solution-processed silicon","authors":"M. Trifunovic, P. Sberna, T. Shimoda, R. Ishihara","doi":"10.1109/IEDM.2016.7838527","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838527","url":null,"abstract":"Solution-processing has gained widespread attention over the past years due to their potential low-cost advantage in terms of fabrication of electronics as well as application to flexible electronics. Cyclopentasilane is used for the solution-based processing of silicon. As a liquid, the material has the potential to be applied directly on low-cost flexible substrates that generally have a low thermal budget, by annealing the liquid using an excimer laser treatment. So far, electronics based on this material have only been demonstrated on rigid and high cost substrates. In this work, silicon has been applied as a solution on top of a paper substrate and processed into PMOS and NMOS thin-film transistors (TFTs). The maximum fabrication temperature was limited to approximately 100° C. By being able to fabricate devices on top of a paper substrate, a pathway opens towards new applications that combine the true low-cost and biodegradability with the high performance of silicon electronics.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129298676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838483
Yanfeng Jiang, Yisong Zhang, A. Klemm, Jianping Wang
A novel thermal sensor is designed and fabricated based on spin-transfer torque operated magnetic tunnel junction (STT-MTJ) device. It can fulfill thermal detection and overheat protection on integrated circuit. Moreover, it shows over 10 times faster thermal transit response speed than that of traditional CMOS thermal sensor. The unique property is really helpful for controlling integrated circuit's temperature due to heating by leakage current. A power driver at full loading situation is used to demonstrate this design. It shows that the sensor can be adopted as adaptive manner in a power source scaling strategy to cool down the IC in an effective way, showing a promising potential application not only as discrete sensor, but also as power solution for IC driver.
{"title":"Fast spintronic thermal sensor for IC power driver cooling down","authors":"Yanfeng Jiang, Yisong Zhang, A. Klemm, Jianping Wang","doi":"10.1109/IEDM.2016.7838483","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838483","url":null,"abstract":"A novel thermal sensor is designed and fabricated based on spin-transfer torque operated magnetic tunnel junction (STT-MTJ) device. It can fulfill thermal detection and overheat protection on integrated circuit. Moreover, it shows over 10 times faster thermal transit response speed than that of traditional CMOS thermal sensor. The unique property is really helpful for controlling integrated circuit's temperature due to heating by leakage current. A power driver at full loading situation is used to demonstrate this design. It shows that the sensor can be adopted as adaptive manner in a power source scaling strategy to cool down the IC in an effective way, showing a promising potential application not only as discrete sensor, but also as power solution for IC driver.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838432
C. Liao, Meng-Yin Hsu, Y. Chih, Jonathan Chang, Y. King, C. Lin
A full logic compatible 4T2R nonvolatile Static Random Access Memory (nv-SRAM) is successfully demonstrated in pure 40nm CMOS logic process. This non-volatile SRAM consists of two STI RRAMs embedded inside the 4T SRAM with minimal area penalty and full logic compatibility. Data is accessed through SRAM cells, and stored by switching one of the loading RRAMs by an unique self-inhibit feature. With this embedded STI RRAM storage nodes, data can be held under power-off mode with zero static power.
{"title":"Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process","authors":"C. Liao, Meng-Yin Hsu, Y. Chih, Jonathan Chang, Y. King, C. Lin","doi":"10.1109/IEDM.2016.7838432","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838432","url":null,"abstract":"A full logic compatible 4T2R nonvolatile Static Random Access Memory (nv-SRAM) is successfully demonstrated in pure 40nm CMOS logic process. This non-volatile SRAM consists of two STI RRAMs embedded inside the 4T SRAM with minimal area penalty and full logic compatibility. Data is accessed through SRAM cells, and stored by switching one of the loading RRAMs by an unique self-inhibit feature. With this embedded STI RRAM storage nodes, data can be held under power-off mode with zero static power.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125470424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838405
R. Zhang, J. Li, Z. Zheng, X. Yu, W. Dong, Y. Zhao
The effective masses of hole and electron in the inversion layers have been quantitatively characterized for Ge p- and n-MOSFETs, for the first time, with Shubnikov-de Haas (SdH) oscillations measurements at ultra low temperatures. It was found that the effective mass clearly increased with a larger Ns for both hole and electron in (100)/(110)/(111) Ge p and n-MOSFETs. The effectiveness and necessity of considering the effective mass change with the inversion layer charge density have also been confirmed for Ge MOSFETs performance modeling and simulation.
{"title":"Experimental study on hole and electron effective masses in inversion layers of Ge (100), (110) and (111) p- and n-MOSFETs","authors":"R. Zhang, J. Li, Z. Zheng, X. Yu, W. Dong, Y. Zhao","doi":"10.1109/IEDM.2016.7838405","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838405","url":null,"abstract":"The effective masses of hole and electron in the inversion layers have been quantitatively characterized for Ge p- and n-MOSFETs, for the first time, with Shubnikov-de Haas (SdH) oscillations measurements at ultra low temperatures. It was found that the effective mass clearly increased with a larger Ns for both hole and electron in (100)/(110)/(111) Ge p and n-MOSFETs. The effectiveness and necessity of considering the effective mass change with the inversion layer charge density have also been confirmed for Ge MOSFETs performance modeling and simulation.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125615030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838441
S. Barraud, V. Lapras, M. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Possémé, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet
We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.
{"title":"Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain","authors":"S. Barraud, V. Lapras, M. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Possémé, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet","doi":"10.1109/IEDM.2016.7838441","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838441","url":null,"abstract":"We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131957890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838519
X. Yu, B. Chen, R. Cheng, Y. Qu, J. Han, R. Zhang, Y. Zhao
Ge p- and n-MOSFETs with Al2O3/GeOx/Ge gate stack were fabricated and characterized using a novel sub-1 ns ultra-fast measurement system. Devices operation under the conditions, that applying Vg with the ultra-fast rise edge down to less than 1 ns are confirmed. It is found that the current degradation within the first 10 ns is much more significant than that from 100 ns to longer time due to the fast trapping effect. In additions, the trap density distributions in Ge MOSFETs inside Ec and Ev are measured and calculated.
{"title":"Fast-trap characterization in Ge CMOS using Sub-1 ns ultra-fast measurement system","authors":"X. Yu, B. Chen, R. Cheng, Y. Qu, J. Han, R. Zhang, Y. Zhao","doi":"10.1109/IEDM.2016.7838519","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838519","url":null,"abstract":"Ge p- and n-MOSFETs with Al2O3/GeOx/Ge gate stack were fabricated and characterized using a novel sub-1 ns ultra-fast measurement system. Devices operation under the conditions, that applying Vg with the ultra-fast rise edge down to less than 1 ns are confirmed. It is found that the current degradation within the first 10 ns is much more significant than that from 100 ns to longer time due to the fast trapping effect. In additions, the trap density distributions in Ge MOSFETs inside Ec and Ev are measured and calculated.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130087040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838335
B. Heinemann, Holger Rücker, R. Barth, F. Barwolf, J. Drews, G. Fischer, A. Fox, O. Fursenko, T. Grabolla, Frank Herzel, J. Katzer, J. Korn, A. Kruger, P. Kulse, T. Lenke, M. Lisker, S. Marschmeyer, A. Scheit, D. Schmidt, J. Schmidt, Markus Andreas Schubert, A. Trusch, Ch. Wipf, D. Wolansky
An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.
{"title":"SiGe HBT with fx/fmax of 505 GHz/720 GHz","authors":"B. Heinemann, Holger Rücker, R. Barth, F. Barwolf, J. Drews, G. Fischer, A. Fox, O. Fursenko, T. Grabolla, Frank Herzel, J. Katzer, J. Korn, A. Kruger, P. Kulse, T. Lenke, M. Lisker, S. Marschmeyer, A. Scheit, D. Schmidt, J. Schmidt, Markus Andreas Schubert, A. Trusch, Ch. Wipf, D. Wolansky","doi":"10.1109/IEDM.2016.7838335","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838335","url":null,"abstract":"An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130427208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838348
A. Grossi, E. Nowak, C. Zambelli, C. Pellissier, S. Bernasconi, G. Cibrario, K. E. Hajjam, R. Crochemore, J. Nodin, P. Olivo, L. Perniola
While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors. As a result, the fundamental variability limits of filament-based RRAM in the full resistance range are identified.
{"title":"Fundamental variability limits of filament-based RRAM","authors":"A. Grossi, E. Nowak, C. Zambelli, C. Pellissier, S. Bernasconi, G. Cibrario, K. E. Hajjam, R. Crochemore, J. Nodin, P. Olivo, L. Perniola","doi":"10.1109/IEDM.2016.7838348","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838348","url":null,"abstract":"While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors. As a result, the fundamental variability limits of filament-based RRAM in the full resistance range are identified.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"38 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134529239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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