Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838419
W. Cao, W. Liu, K. Banerjee
Although 2D semiconductor based FETs have been predicted to be very promising for the ultimate scaling (sub-10 nm nodes) of CMOS technology [1],[2], they face two major challenges in the pathway to commercialization. One is the growth of ultra-thin and high-quality gate dielectrics (preferably high-k) on top of the pristine surfaces of 2D semiconductors, which is a fundamentally difficult task. The other involves formation of ultra-short channel/gate using advanced lithography techniques, which are, however, usually expensive and/or of low yield. Using synthesized ultra-thin core/shell nanowire to gate the 2D semiconductors could be a promising approach, which not only facilitates a lithography-free ultra-short channel formation with relative ease, but also avoids the direct growth of dielectrics on 2D materials, which can help preserve the pristine nature of the 2D channel and its outstanding properties. In this work, aided by rigorous quantum simulations, we attempt to understand and optimize this nonconventional FET structure, guided by a prototype demonstration of this device. It is found that this unique FET structure offers 2D semiconductors a promising platform, in terms of manufacturability and device performance, for next-generation CMOS technology.
{"title":"Prospects of ultra-thin nanowire gated 2D-FETs for next-generation CMOS technology","authors":"W. Cao, W. Liu, K. Banerjee","doi":"10.1109/IEDM.2016.7838419","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838419","url":null,"abstract":"Although 2D semiconductor based FETs have been predicted to be very promising for the ultimate scaling (sub-10 nm nodes) of CMOS technology [1],[2], they face two major challenges in the pathway to commercialization. One is the growth of ultra-thin and high-quality gate dielectrics (preferably high-k) on top of the pristine surfaces of 2D semiconductors, which is a fundamentally difficult task. The other involves formation of ultra-short channel/gate using advanced lithography techniques, which are, however, usually expensive and/or of low yield. Using synthesized ultra-thin core/shell nanowire to gate the 2D semiconductors could be a promising approach, which not only facilitates a lithography-free ultra-short channel formation with relative ease, but also avoids the direct growth of dielectrics on 2D materials, which can help preserve the pristine nature of the 2D channel and its outstanding properties. In this work, aided by rigorous quantum simulations, we attempt to understand and optimize this nonconventional FET structure, guided by a prototype demonstration of this device. It is found that this unique FET structure offers 2D semiconductors a promising platform, in terms of manufacturability and device performance, for next-generation CMOS technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838334
R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, Xin He Miao, J. Sporre, J. Fronheiser, N. Loubet, M. Sung, S. Sieg, S. Mochizuki, C. Prindle, S. Seo, A. Greene, J. Shearer, A. Labonté, S. Fan, L. Liebmann, R. Chao, A. Arceo, K. Chung, K. Cheon, P. Adusumilli, H. Amanapu, Z. Bi, J. Cha, H. Chen, R. Conti, R. Galatage, O. Gluschenkov, V. Kamineni, K. Kim, C. Lee, F. Lie, Z. Liu, S. Mehta, E. Miller, H. Niimi, C. Niu, C. Park, D. Park, M. Raymond, B. Sahu, M. Sankarapandian, S. Siddiqui, R. Southwick, L. Sun, C. Surisetty, S. Tsai, S. Whang, P. Xu, Y. Xu, C. Yeh, P. Zeitzoff, J. Zhang, J. Li, J. Demarest, J. Arnold, D. Canaperi, D. Dunn, N. Felix, D. Gupta, H. Jagannathan, S. Kanakasabapathy, W. Kleemeier, C. Labelle, M. Mottura, P. Oldiges, S. Skordas, T. Standaert, T. Yamashita, M. Colburn, M. Na, V. Paruchuri, S. Lian, R. Divakaruni, T. Gow, S. Lee, A. Knorr, H. Bu, M. Khare
We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.
{"title":"A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels","authors":"R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, Xin He Miao, J. Sporre, J. Fronheiser, N. Loubet, M. Sung, S. Sieg, S. Mochizuki, C. Prindle, S. Seo, A. Greene, J. Shearer, A. Labonté, S. Fan, L. Liebmann, R. Chao, A. Arceo, K. Chung, K. Cheon, P. Adusumilli, H. Amanapu, Z. Bi, J. Cha, H. Chen, R. Conti, R. Galatage, O. Gluschenkov, V. Kamineni, K. Kim, C. Lee, F. Lie, Z. Liu, S. Mehta, E. Miller, H. Niimi, C. Niu, C. Park, D. Park, M. Raymond, B. Sahu, M. Sankarapandian, S. Siddiqui, R. Southwick, L. Sun, C. Surisetty, S. Tsai, S. Whang, P. Xu, Y. Xu, C. Yeh, P. Zeitzoff, J. Zhang, J. Li, J. Demarest, J. Arnold, D. Canaperi, D. Dunn, N. Felix, D. Gupta, H. Jagannathan, S. Kanakasabapathy, W. Kleemeier, C. Labelle, M. Mottura, P. Oldiges, S. Skordas, T. Standaert, T. Yamashita, M. Colburn, M. Na, V. Paruchuri, S. Lian, R. Divakaruni, T. Gow, S. Lee, A. Knorr, H. Bu, M. Khare","doi":"10.1109/IEDM.2016.7838334","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838334","url":null,"abstract":"We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838498
Chi-Shuen Lee, B. Cline, Saurabh Sinha, G. Yeric, H. Wong
A 32-bit commercial processor core is implemented at 5-nm design rules to study transistor and interconnect technology options and the impact of increasing interconnect resistance on system performance. Insights obtained are: 1) The major benefit of downscaling FET gate length is reducing MEOL parasitics instead of the intrinsic gate capacitance. 2) 2D-material-based FETs can achieve ∼2∗ better core-level energy-delay-product in theory compared to the projected Si FinFET; contact resistivity <6∗10−8 Ω-μm2 is required for 2D-FETs to match the core performance using Si FinFET. 3) Signal routing optimization can mitigate the impact of BEOL resistance such it contributes to 15%–35% of the total delay at the cost of using more cells and vias, which is not manifest if a ring oscillator with fixed wire load is used without performing full place-and-route. 4) Thinning Cu diffusion barrier can improve system performance up to 11% and alleviate BEOL variation impact.
{"title":"32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance","authors":"Chi-Shuen Lee, B. Cline, Saurabh Sinha, G. Yeric, H. Wong","doi":"10.1109/IEDM.2016.7838498","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838498","url":null,"abstract":"A 32-bit commercial processor core is implemented at 5-nm design rules to study transistor and interconnect technology options and the impact of increasing interconnect resistance on system performance. Insights obtained are: 1) The major benefit of downscaling FET gate length is reducing MEOL parasitics instead of the intrinsic gate capacitance. 2) 2D-material-based FETs can achieve ∼2∗ better core-level energy-delay-product in theory compared to the projected Si FinFET; contact resistivity <6∗10−8 Ω-μm2 is required for 2D-FETs to match the core performance using Si FinFET. 3) Signal routing optimization can mitigate the impact of BEOL resistance such it contributes to 15%–35% of the total delay at the cost of using more cells and vias, which is not manifest if a ring oscillator with fixed wire load is used without performing full place-and-route. 4) Thinning Cu diffusion barrier can improve system performance up to 11% and alleviate BEOL variation impact.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134615186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838516
M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. Karner, G. Rzepa, T. Grasset
Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.
{"title":"Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations","authors":"M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. Karner, G. Rzepa, T. Grasset","doi":"10.1109/IEDM.2016.7838516","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838516","url":null,"abstract":"Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134647673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/iedm.2016.7838029
R. Carter, J. Mazurier, L. Pirro, J.-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub, J. Hoentschel, M. Vinet, J. Schaeffer, B. Rice
22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V Vmin for 8T logic libraries, as well as 0.62V and 0.52V Vmin for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm Ioff, and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high fT/fMAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high fMAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.
{"title":"22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications","authors":"R. Carter, J. Mazurier, L. Pirro, J.-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub, J. Hoentschel, M. Vinet, J. Schaeffer, B. Rice","doi":"10.1109/iedm.2016.7838029","DOIUrl":"https://doi.org/10.1109/iedm.2016.7838029","url":null,"abstract":"22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V<inf>min</inf> for 8T logic libraries, as well as 0.62V and 0.52V V<inf>min</inf> for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I<inf>off</inf>, and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f<inf>T</inf>/f<inf>MAx</inf> of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f<inf>MAx</inf> extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122340143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838358
K. Takei
Macroscale, flexible, and/or stretchable electronics enable to collect a variety of information by attaching it on diverse objects including nonplanar surfaces such as human body. To realize the devices, there are several technical challenges such as (1) low-cost, macroscale sensor network formation, (2) low power and high performance flexible circuits, and (3) other flexible components including battery and wireless communications. In this study, we propose and develop a low power flexible circuit platform using inorganic material-based complementary metal-oxide-semiconductor (CMOS) on a flexible substrate and printed macro-scale, multi-functional sensor networks to address the challenges.
{"title":"High performance, flexible CMOS circuits and sensors toward wearable healthcare applications","authors":"K. Takei","doi":"10.1109/IEDM.2016.7838358","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838358","url":null,"abstract":"Macroscale, flexible, and/or stretchable electronics enable to collect a variety of information by attaching it on diverse objects including nonplanar surfaces such as human body. To realize the devices, there are several technical challenges such as (1) low-cost, macroscale sensor network formation, (2) low power and high performance flexible circuits, and (3) other flexible components including battery and wireless communications. In this study, we propose and develop a low power flexible circuit platform using inorganic material-based complementary metal-oxide-semiconductor (CMOS) on a flexible substrate and printed macro-scale, multi-functional sensor networks to address the challenges.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122840570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838382
T. Ando, E. Cartier, P. Jamison, A. Pyzyna, S. Kim, J. Bruley, K. Chung, H. Shobha, I. Estrada-Raygoza, H. Tang, S. Kanakasabapathy, T. Spooner, L. Clevenger, G. Bonilla, H. Jagannathan, V. Narayanan
We demonstrate a record-low EOT (equivalent oxide thickness) of 0.8 nm for a metal-insulator-metal (MIM) decoupling capacitor, which is compatible with back-end-of-line (BEOL) processing. This results in 2-plate MIM capacitance density of 43 fF/um2, and leakage current density (Jg) of 5 fA/um2 at 1V, 125 oC. Moreover, we identify that symmetry of CV/IV/TDDB characteristics for both positive and negative bias polarities is a key consideration for stacking more than one MIM capacitor for further capacitance density increase. We develop a novel tri-layer high-k stack with buffer layers between HfO2 and metal electrodes, which substantially improves the electrical bias symmetry, and achieve Vuse = 1.32 V (10 yr/1 ppm/1 cm2/125 oC) at EOT = 0.8 nm. These results should support record stacked-MIM (> 2-plate) capacitance densities, with sub-nm EOT, for the 7 nm node and beyond.
{"title":"CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond","authors":"T. Ando, E. Cartier, P. Jamison, A. Pyzyna, S. Kim, J. Bruley, K. Chung, H. Shobha, I. Estrada-Raygoza, H. Tang, S. Kanakasabapathy, T. Spooner, L. Clevenger, G. Bonilla, H. Jagannathan, V. Narayanan","doi":"10.1109/IEDM.2016.7838382","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838382","url":null,"abstract":"We demonstrate a record-low EOT (equivalent oxide thickness) of 0.8 nm for a metal-insulator-metal (MIM) decoupling capacitor, which is compatible with back-end-of-line (BEOL) processing. This results in 2-plate MIM capacitance density of 43 fF/um2, and leakage current density (Jg) of 5 fA/um2 at 1V, 125 oC. Moreover, we identify that symmetry of CV/IV/TDDB characteristics for both positive and negative bias polarities is a key consideration for stacking more than one MIM capacitor for further capacitance density increase. We develop a novel tri-layer high-k stack with buffer layers between HfO2 and metal electrodes, which substantially improves the electrical bias symmetry, and achieve Vuse = 1.32 V (10 yr/1 ppm/1 cm2/125 oC) at EOT = 0.8 nm. These results should support record stacked-MIM (> 2-plate) capacitance densities, with sub-nm EOT, for the 7 nm node and beyond.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128741508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838493
J. Kan, C. Park, C. Ching, J. Ahn, L. Xue, R. Wang, A. Kontos, S. Liang, M. Bangar, H. Chen, S. Hassan, S. Kim, M. Pakala, S. H. Kang
We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.
我们提出了一个全面的STT-MRAM器件和可扩展性验证，用于sub- 10nm CMOS的高性能应用，提供了垂直磁隧道结(pMTJs)在1gbit阵列中从70到25nm直径的势垒可靠性的第一个统计说明。我们通过实验研究了时间相关的介质击穿(TDDB)特性以及pMTJ寿命对电压、极性、占空比和温度的依赖关系。45nm的pMTJs具有> 1 V (> 20 σavg)的大写入击穿电压窗，并且具有> 1015个周期的击穿时间，保证了几乎无限的写入周期。我们还发现，当pMTJ尺寸缩小到25 nm直径时，势垒可靠性显著增强，进一步扩大了深度缩放节点的操作窗口。
{"title":"Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance","authors":"J. Kan, C. Park, C. Ching, J. Ahn, L. Xue, R. Wang, A. Kontos, S. Liang, M. Bangar, H. Chen, S. Hassan, S. Kim, M. Pakala, S. H. Kang","doi":"10.1109/IEDM.2016.7838493","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838493","url":null,"abstract":"We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129094715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838378
Tomohiro Yamazaki, Yasushi Maruyama, Yusuke Uesaka, Motoaki Nakamura, Y. Matoba, T. Terada, K. Komori, Y. Ohba, S. Arakawa, Yasutaka Hirasawa, Yuhi Kondo, J. Murayama, Kentaro Akiyama, Y. Oike, Shuzo Sato, T. Ezaki
Polarization information is useful in highly functional imaging. This paper presents a four-directional pixel-wise polarization CMOS image sensor using an air-gap wire grid on 2.5-μm back-illuminated pixels. The fabricated air-gap wire grid polarizer achieved a transmittance of 63.3 % and an extinction ratio of 85 at 550 nm, outperforming conventional polarization sensors. The pixel-wise polarizers fabricated with the wafer process on back-illuminated image sensors exhibit good oblique-incidence characteristics, even with small polarization pixels of 2.5 μm. The proposed image sensor realizes mega-pixel various fusion-imaging applications, such as surface reflection reduction, highly accurate depth mapping, and condition-robust surveillance.
{"title":"Four-directional pixel-wise polarization CMOS image sensor using air-gap wire grid on 2.5-μm back-illuminated pixels","authors":"Tomohiro Yamazaki, Yasushi Maruyama, Yusuke Uesaka, Motoaki Nakamura, Y. Matoba, T. Terada, K. Komori, Y. Ohba, S. Arakawa, Yasutaka Hirasawa, Yuhi Kondo, J. Murayama, Kentaro Akiyama, Y. Oike, Shuzo Sato, T. Ezaki","doi":"10.1109/IEDM.2016.7838378","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838378","url":null,"abstract":"Polarization information is useful in highly functional imaging. This paper presents a four-directional pixel-wise polarization CMOS image sensor using an air-gap wire grid on 2.5-μm back-illuminated pixels. The fabricated air-gap wire grid polarizer achieved a transmittance of 63.3 % and an extinction ratio of 85 at 550 nm, outperforming conventional polarization sensors. The pixel-wise polarizers fabricated with the wafer process on back-illuminated image sensors exhibit good oblique-incidence characteristics, even with small polarization pixels of 2.5 μm. The proposed image sensor realizes mega-pixel various fusion-imaging applications, such as surface reflection reduction, highly accurate depth mapping, and condition-robust surveillance.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116124810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838451
Mingda Li, R. Yan, D. Jena, H. Xing
We review the conception and development of two-dimensional heterojunction interlayer field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) and a high on-current are estimated theoretically. The Thin-TFET has been experimentally demonstrated using WSe2/SnSe2 stacked heterostructures, where the SS is mostly likely limited by the interfacial trap density of states and the parasitic MOSFET. Due to its vertical stacking structure, Thin-TFET intrinsically has a smaller gate-drain capacitance compared to the conventional lateral pin-TFET. In turn, this results in mitigated Miller Effect in Thin-TFET thus reducing dynamic energy dissipation in circuits.
{"title":"Two-dimensional heterojunction interlayer tunnel FET (Thin-TFET): From theory to applications","authors":"Mingda Li, R. Yan, D. Jena, H. Xing","doi":"10.1109/IEDM.2016.7838451","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838451","url":null,"abstract":"We review the conception and development of two-dimensional heterojunction interlayer field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) and a high on-current are estimated theoretically. The Thin-TFET has been experimentally demonstrated using WSe2/SnSe2 stacked heterostructures, where the SS is mostly likely limited by the interfacial trap density of states and the parasitic MOSFET. Due to its vertical stacking structure, Thin-TFET intrinsically has a smaller gate-drain capacitance compared to the conventional lateral pin-TFET. In turn, this results in mitigated Miller Effect in Thin-TFET thus reducing dynamic energy dissipation in circuits.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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