Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838457
A. Huang
Wide bandgap (WBG) power semiconductor devices have the capability to reach higher voltage, higher frequency and higher temperature compared with silicon based power devices. These capabilities have the potentials to revolutionize the way we deliver and manage power in the future. This paper reviews the WBG progress and their potential transformative impacts on low voltage, medium voltage and high voltage power delivery systems.
{"title":"Wide bandgap (WBG) power devices and their impacts on power delivery systems","authors":"A. Huang","doi":"10.1109/IEDM.2016.7838457","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838457","url":null,"abstract":"Wide bandgap (WBG) power semiconductor devices have the capability to reach higher voltage, higher frequency and higher temperature compared with silicon based power devices. These capabilities have the potentials to revolutionize the way we deliver and manage power in the future. This paper reviews the WBG progress and their potential transformative impacts on low voltage, medium voltage and high voltage power delivery systems.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838470
H. Oka, M. Koyama, T. Tomita, T. Amamoto, K. Tominaga, S. Tanaka, T. Hosoi, T. Shimura, H. Watanabe
Record-high mobility Ge-based TFT (μfe: 423 cm2/Vs) and significant enhancement of near-infrared (NIR) luminescence (×54 Ge bulk) were demonstrated with single-crystalline GeSn layer on transparent substrate grown by a novel liquid-phase crystallization technique. Our GeSn growth scheme is fully compatible with the conventional CMOS process and can provide high-quality tensile-strained p- and n-type GeSn layers, thus paving the way for monolithic optoelectronic integration available not only for optical communications but also for NIR imaging and biochemical sensing with wide wavelength range.
采用新型液相结晶技术在透明衬底上生长单晶GeSn层，证明了创纪录的高迁移率(μfe: 423 cm2/Vs)和近红外(NIR)发光(×54 Ge bulk)的显著增强。我们的GeSn生长方案与传统的CMOS工艺完全兼容，可以提供高质量的拉伸应变p型和n型GeSn层，从而为单片光电集成铺平了道路，不仅可用于光通信，还可用于近红外成像和宽波长范围的生化传感。
{"title":"High-mobility TFT and enhanced luminescence utilizing nucleation-controlled GeSn growth on transparent substrate for monolithic optoelectronic integration","authors":"H. Oka, M. Koyama, T. Tomita, T. Amamoto, K. Tominaga, S. Tanaka, T. Hosoi, T. Shimura, H. Watanabe","doi":"10.1109/IEDM.2016.7838470","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838470","url":null,"abstract":"Record-high mobility Ge-based TFT (μfe: 423 cm2/Vs) and significant enhancement of near-infrared (NIR) luminescence (×54 Ge bulk) were demonstrated with single-crystalline GeSn layer on transparent substrate grown by a novel liquid-phase crystallization technique. Our GeSn growth scheme is fully compatible with the conventional CMOS process and can provide high-quality tensile-strained p- and n-type GeSn layers, thus paving the way for monolithic optoelectronic integration available not only for optical communications but also for NIR imaging and biochemical sensing with wide wavelength range.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125201682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838498
Chi-Shuen Lee, B. Cline, Saurabh Sinha, G. Yeric, H. Wong
A 32-bit commercial processor core is implemented at 5-nm design rules to study transistor and interconnect technology options and the impact of increasing interconnect resistance on system performance. Insights obtained are: 1) The major benefit of downscaling FET gate length is reducing MEOL parasitics instead of the intrinsic gate capacitance. 2) 2D-material-based FETs can achieve ∼2∗ better core-level energy-delay-product in theory compared to the projected Si FinFET; contact resistivity <6∗10−8 Ω-μm2 is required for 2D-FETs to match the core performance using Si FinFET. 3) Signal routing optimization can mitigate the impact of BEOL resistance such it contributes to 15%–35% of the total delay at the cost of using more cells and vias, which is not manifest if a ring oscillator with fixed wire load is used without performing full place-and-route. 4) Thinning Cu diffusion barrier can improve system performance up to 11% and alleviate BEOL variation impact.
{"title":"32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance","authors":"Chi-Shuen Lee, B. Cline, Saurabh Sinha, G. Yeric, H. Wong","doi":"10.1109/IEDM.2016.7838498","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838498","url":null,"abstract":"A 32-bit commercial processor core is implemented at 5-nm design rules to study transistor and interconnect technology options and the impact of increasing interconnect resistance on system performance. Insights obtained are: 1) The major benefit of downscaling FET gate length is reducing MEOL parasitics instead of the intrinsic gate capacitance. 2) 2D-material-based FETs can achieve ∼2∗ better core-level energy-delay-product in theory compared to the projected Si FinFET; contact resistivity <6∗10−8 Ω-μm2 is required for 2D-FETs to match the core performance using Si FinFET. 3) Signal routing optimization can mitigate the impact of BEOL resistance such it contributes to 15%–35% of the total delay at the cost of using more cells and vias, which is not manifest if a ring oscillator with fixed wire load is used without performing full place-and-route. 4) Thinning Cu diffusion barrier can improve system performance up to 11% and alleviate BEOL variation impact.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134615186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838516
M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. Karner, G. Rzepa, T. Grasset
Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.
{"title":"Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations","authors":"M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. Karner, G. Rzepa, T. Grasset","doi":"10.1109/IEDM.2016.7838516","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838516","url":null,"abstract":"Using an advanced simulation framework we analyze a recent sub-10 nm technology demonstration based on stacked nanowire transistors (NW-FETs). The study encompasses (i) topography simulation which realistically reproduces the fabricated device, (ii) device simulation based on the subband Boltzmann transport equation (iii) a comprehensive set of scattering models for the gate stack, (iv) physical models for time-zero variability and BTI device degradation. We find that (i) the fabrication process introduces parasitic capacitances not present in a comparable FinFET, (ii) the device performance is significantly affected by interface-charge-induced Coulomb scattering resulting in up to 50% reduction in drain current compared to an ideal device, (iii) device time-zero variability is increased due to a lower amount of dopant atoms per device, (iv) the device is more affected by BTI than a comparable FinFET. Using physics-based TCAD for technology path-finding and device optimization, we are able to point out critical improvements required for the stacked NW-FET to surpass current FinFET technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134647673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838334
R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, Xin He Miao, J. Sporre, J. Fronheiser, N. Loubet, M. Sung, S. Sieg, S. Mochizuki, C. Prindle, S. Seo, A. Greene, J. Shearer, A. Labonté, S. Fan, L. Liebmann, R. Chao, A. Arceo, K. Chung, K. Cheon, P. Adusumilli, H. Amanapu, Z. Bi, J. Cha, H. Chen, R. Conti, R. Galatage, O. Gluschenkov, V. Kamineni, K. Kim, C. Lee, F. Lie, Z. Liu, S. Mehta, E. Miller, H. Niimi, C. Niu, C. Park, D. Park, M. Raymond, B. Sahu, M. Sankarapandian, S. Siddiqui, R. Southwick, L. Sun, C. Surisetty, S. Tsai, S. Whang, P. Xu, Y. Xu, C. Yeh, P. Zeitzoff, J. Zhang, J. Li, J. Demarest, J. Arnold, D. Canaperi, D. Dunn, N. Felix, D. Gupta, H. Jagannathan, S. Kanakasabapathy, W. Kleemeier, C. Labelle, M. Mottura, P. Oldiges, S. Skordas, T. Standaert, T. Yamashita, M. Colburn, M. Na, V. Paruchuri, S. Lian, R. Divakaruni, T. Gow, S. Lee, A. Knorr, H. Bu, M. Khare
We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.
{"title":"A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels","authors":"R. Xie, P. Montanini, K. Akarvardar, N. Tripathi, B. Haran, S. Johnson, T. Hook, B. Hamieh, D. Corliss, J. Wang, Xin He Miao, J. Sporre, J. Fronheiser, N. Loubet, M. Sung, S. Sieg, S. Mochizuki, C. Prindle, S. Seo, A. Greene, J. Shearer, A. Labonté, S. Fan, L. Liebmann, R. Chao, A. Arceo, K. Chung, K. Cheon, P. Adusumilli, H. Amanapu, Z. Bi, J. Cha, H. Chen, R. Conti, R. Galatage, O. Gluschenkov, V. Kamineni, K. Kim, C. Lee, F. Lie, Z. Liu, S. Mehta, E. Miller, H. Niimi, C. Niu, C. Park, D. Park, M. Raymond, B. Sahu, M. Sankarapandian, S. Siddiqui, R. Southwick, L. Sun, C. Surisetty, S. Tsai, S. Whang, P. Xu, Y. Xu, C. Yeh, P. Zeitzoff, J. Zhang, J. Li, J. Demarest, J. Arnold, D. Canaperi, D. Dunn, N. Felix, D. Gupta, H. Jagannathan, S. Kanakasabapathy, W. Kleemeier, C. Labelle, M. Mottura, P. Oldiges, S. Skordas, T. Standaert, T. Yamashita, M. Colburn, M. Na, V. Paruchuri, S. Lian, R. Divakaruni, T. Gow, S. Lee, A. Knorr, H. Bu, M. Khare","doi":"10.1109/IEDM.2016.7838334","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838334","url":null,"abstract":"We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838468
R. Carboni, S. Ambrogio, Wei Chen, M. Siddik, J. Harms, Andy Lyle, Witold Kula, Gurtej S. Sandhu, Daniele Ielmini
Perpendicular spin-transfer torque (p-STT) memory is attracting an increasing interest as storage class memory (SCM) or static/dynamic RAM replacement. In these applications, high speed and extended endurance are essential and sometimes conflicting requirements. This work addresses cycling endurance of p-STT devices by pulsed experiments and modeling of the dielectric breakdown. We present a new endurance model able to predict the STT endurance as a function of applied voltage, pulse width, pulse polarity and delay time. The trade-off between write time and endurance for RAM replacement is finally addressed.
{"title":"Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory","authors":"R. Carboni, S. Ambrogio, Wei Chen, M. Siddik, J. Harms, Andy Lyle, Witold Kula, Gurtej S. Sandhu, Daniele Ielmini","doi":"10.1109/IEDM.2016.7838468","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838468","url":null,"abstract":"Perpendicular spin-transfer torque (p-STT) memory is attracting an increasing interest as storage class memory (SCM) or static/dynamic RAM replacement. In these applications, high speed and extended endurance are essential and sometimes conflicting requirements. This work addresses cycling endurance of p-STT devices by pulsed experiments and modeling of the dielectric breakdown. We present a new endurance model able to predict the STT endurance as a function of applied voltage, pulse width, pulse polarity and delay time. The trade-off between write time and endurance for RAM replacement is finally addressed.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133726783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838338
Xiaowei Cai, Jianqiang Lin, D. Antoniadis, J. D. del Alamo
We report, for the first time, a prominent but fully reversible enhancement in transconductance after applying positive gate stress to self-aligned InGaAs MOSFETs. We attribute this to electric-field-induced migration of fluorine ions (F−) introduced during the RIE gate recess process. F− is known to passivate Si donors in InAlAs. In our device structure, an n-InAlAs ledge facilitates the link from the contacts to the intrinsic device. We use secondary ion mass spectroscopy (SIMS) to independently confirm that our process leads to F pile up at the n-InAlAs layer. Transmission line model (TLM) structures confirm F−-induced donor passivation. The understanding derived has lead us to redesign our InGaAs MOSFETs by eliminating n-InAlAs layers and instead use an n-InP ledge. The new device design not only exhibits greatly improved electrical stability but also record performance.
{"title":"Electric-field induced F− migration in self-aligned InGaAs MOSFETs and mitigation","authors":"Xiaowei Cai, Jianqiang Lin, D. Antoniadis, J. D. del Alamo","doi":"10.1109/IEDM.2016.7838338","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838338","url":null,"abstract":"We report, for the first time, a prominent but fully reversible enhancement in transconductance after applying positive gate stress to self-aligned InGaAs MOSFETs. We attribute this to electric-field-induced migration of fluorine ions (F−) introduced during the RIE gate recess process. F− is known to passivate Si donors in InAlAs. In our device structure, an n-InAlAs ledge facilitates the link from the contacts to the intrinsic device. We use secondary ion mass spectroscopy (SIMS) to independently confirm that our process leads to F pile up at the n-InAlAs layer. Transmission line model (TLM) structures confirm F−-induced donor passivation. The understanding derived has lead us to redesign our InGaAs MOSFETs by eliminating n-InAlAs layers and instead use an n-InP ledge. The new device design not only exhibits greatly improved electrical stability but also record performance.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115080815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838419
W. Cao, W. Liu, K. Banerjee
Although 2D semiconductor based FETs have been predicted to be very promising for the ultimate scaling (sub-10 nm nodes) of CMOS technology [1],[2], they face two major challenges in the pathway to commercialization. One is the growth of ultra-thin and high-quality gate dielectrics (preferably high-k) on top of the pristine surfaces of 2D semiconductors, which is a fundamentally difficult task. The other involves formation of ultra-short channel/gate using advanced lithography techniques, which are, however, usually expensive and/or of low yield. Using synthesized ultra-thin core/shell nanowire to gate the 2D semiconductors could be a promising approach, which not only facilitates a lithography-free ultra-short channel formation with relative ease, but also avoids the direct growth of dielectrics on 2D materials, which can help preserve the pristine nature of the 2D channel and its outstanding properties. In this work, aided by rigorous quantum simulations, we attempt to understand and optimize this nonconventional FET structure, guided by a prototype demonstration of this device. It is found that this unique FET structure offers 2D semiconductors a promising platform, in terms of manufacturability and device performance, for next-generation CMOS technology.
{"title":"Prospects of ultra-thin nanowire gated 2D-FETs for next-generation CMOS technology","authors":"W. Cao, W. Liu, K. Banerjee","doi":"10.1109/IEDM.2016.7838419","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838419","url":null,"abstract":"Although 2D semiconductor based FETs have been predicted to be very promising for the ultimate scaling (sub-10 nm nodes) of CMOS technology [1],[2], they face two major challenges in the pathway to commercialization. One is the growth of ultra-thin and high-quality gate dielectrics (preferably high-k) on top of the pristine surfaces of 2D semiconductors, which is a fundamentally difficult task. The other involves formation of ultra-short channel/gate using advanced lithography techniques, which are, however, usually expensive and/or of low yield. Using synthesized ultra-thin core/shell nanowire to gate the 2D semiconductors could be a promising approach, which not only facilitates a lithography-free ultra-short channel formation with relative ease, but also avoids the direct growth of dielectrics on 2D materials, which can help preserve the pristine nature of the 2D channel and its outstanding properties. In this work, aided by rigorous quantum simulations, we attempt to understand and optimize this nonconventional FET structure, guided by a prototype demonstration of this device. It is found that this unique FET structure offers 2D semiconductors a promising platform, in terms of manufacturability and device performance, for next-generation CMOS technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838396
V. Kottler
This work describes a holistic approach to the application of the Robustness Validation methodology to the qualification of non-volatile memories (NVM) for automotive applications, as well as the resulting requirements to the NVM supplier and to the NVM design and technology.
{"title":"Automotive requirements to non-volatile memories — A holistic approach to qualification","authors":"V. Kottler","doi":"10.1109/IEDM.2016.7838396","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838396","url":null,"abstract":"This work describes a holistic approach to the application of the Robustness Validation methodology to the qualification of non-volatile memories (NVM) for automotive applications, as well as the resulting requirements to the NVM supplier and to the NVM design and technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838515
M. Rau, E. Caruso, D. Lizzit, P. Palestri, D. Esseni, A. Schenk, L. Selmi, M. Luisier
Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thin-body (DG-UTB), a triple-gate FinFET, and a gate-all-around nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of Lg=15 nm and 10.4 nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for Lg=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50–60%.
{"title":"Performance projection of III-V ultra-thin-body, FinFET, and nanowire MOSFETs for two next-generation technology nodes","authors":"M. Rau, E. Caruso, D. Lizzit, P. Palestri, D. Esseni, A. Schenk, L. Selmi, M. Luisier","doi":"10.1109/IEDM.2016.7838515","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838515","url":null,"abstract":"Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thin-body (DG-UTB), a triple-gate FinFET, and a gate-all-around nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of Lg=15 nm and 10.4 nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for Lg=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50–60%.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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