Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838338
Xiaowei Cai, Jianqiang Lin, D. Antoniadis, J. D. del Alamo
We report, for the first time, a prominent but fully reversible enhancement in transconductance after applying positive gate stress to self-aligned InGaAs MOSFETs. We attribute this to electric-field-induced migration of fluorine ions (F−) introduced during the RIE gate recess process. F− is known to passivate Si donors in InAlAs. In our device structure, an n-InAlAs ledge facilitates the link from the contacts to the intrinsic device. We use secondary ion mass spectroscopy (SIMS) to independently confirm that our process leads to F pile up at the n-InAlAs layer. Transmission line model (TLM) structures confirm F−-induced donor passivation. The understanding derived has lead us to redesign our InGaAs MOSFETs by eliminating n-InAlAs layers and instead use an n-InP ledge. The new device design not only exhibits greatly improved electrical stability but also record performance.
{"title":"Electric-field induced F− migration in self-aligned InGaAs MOSFETs and mitigation","authors":"Xiaowei Cai, Jianqiang Lin, D. Antoniadis, J. D. del Alamo","doi":"10.1109/IEDM.2016.7838338","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838338","url":null,"abstract":"We report, for the first time, a prominent but fully reversible enhancement in transconductance after applying positive gate stress to self-aligned InGaAs MOSFETs. We attribute this to electric-field-induced migration of fluorine ions (F−) introduced during the RIE gate recess process. F− is known to passivate Si donors in InAlAs. In our device structure, an n-InAlAs ledge facilitates the link from the contacts to the intrinsic device. We use secondary ion mass spectroscopy (SIMS) to independently confirm that our process leads to F pile up at the n-InAlAs layer. Transmission line model (TLM) structures confirm F−-induced donor passivation. The understanding derived has lead us to redesign our InGaAs MOSFETs by eliminating n-InAlAs layers and instead use an n-InP ledge. The new device design not only exhibits greatly improved electrical stability but also record performance.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115080815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838515
M. Rau, E. Caruso, D. Lizzit, P. Palestri, D. Esseni, A. Schenk, L. Selmi, M. Luisier
Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thin-body (DG-UTB), a triple-gate FinFET, and a gate-all-around nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of Lg=15 nm and 10.4 nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for Lg=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50–60%.
{"title":"Performance projection of III-V ultra-thin-body, FinFET, and nanowire MOSFETs for two next-generation technology nodes","authors":"M. Rau, E. Caruso, D. Lizzit, P. Palestri, D. Esseni, A. Schenk, L. Selmi, M. Luisier","doi":"10.1109/IEDM.2016.7838515","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838515","url":null,"abstract":"Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thin-body (DG-UTB), a triple-gate FinFET, and a gate-all-around nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of Lg=15 nm and 10.4 nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for Lg=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50–60%.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838350
Jianshi Tang, Q. Cao, D. Farmer, G. Tulevski, Shu-Jen Han
CNT-based complementary logic using low-temperature processed end-boned metal contacts are demonstrated. This new form of end-bonded contact is made by carbon dissolution into metal contacts with high carbon solubility (e.g., Ni and Co), which requires only low annealing temperature (400−600 °C). As-fabricated end-bonded Ni contacts serve as robust p-type contacts to CNTs and perform better than standard Pd side-bonded contacts at scaled dimensions. In addition, stable NFETs are converted from PFETs using Al2O3 as an n-type physicochemical doping layer. CMOS inverters are further built with end-bonded contacts for both PFETs and NFETs, featuring the smallest contact size thus far for CNT inverters. These new findings could pave the way to realizing CNT-based scalable CMOS technology.
{"title":"Carbon nanotube complementary logic with low-temperature processed end-bonded metal contacts","authors":"Jianshi Tang, Q. Cao, D. Farmer, G. Tulevski, Shu-Jen Han","doi":"10.1109/IEDM.2016.7838350","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838350","url":null,"abstract":"CNT-based complementary logic using low-temperature processed end-boned metal contacts are demonstrated. This new form of end-bonded contact is made by carbon dissolution into metal contacts with high carbon solubility (e.g., Ni and Co), which requires only low annealing temperature (400−600 °C). As-fabricated end-bonded Ni contacts serve as robust p-type contacts to CNTs and perform better than standard Pd side-bonded contacts at scaled dimensions. In addition, stable NFETs are converted from PFETs using Al2O3 as an n-type physicochemical doping layer. CMOS inverters are further built with end-bonded contacts for both PFETs and NFETs, featuring the smallest contact size thus far for CNT inverters. These new findings could pave the way to realizing CNT-based scalable CMOS technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"52 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122107985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838375
Y. Kagawa, N. Fujii, K. Aoyagi, Y. Kobayashi, S. Nishi, N. Todaka, S. Takeshita, J. Taura, H. Takahashi, Y. Nishimura, K. Tatani, M. Kawamura, H. Nakayama, T. Nagano, K. Ohno, H. Iwamoto, S. Kadomura, T. Hirayama
We have successfully mass-produced novel stacked back-illuminated CMOS image sensors (BI-CIS). In the new CIS, we introduced advanced Cu2Cu hybrid bonding that we had developed. The electrical test results showed that our highly robust Cu2Cu hybrid bonding achieved remarkable connectivity and reliability. The performance of image sensor was also investigated and our novel stacked BI-CIS showed favorable results.
{"title":"Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding","authors":"Y. Kagawa, N. Fujii, K. Aoyagi, Y. Kobayashi, S. Nishi, N. Todaka, S. Takeshita, J. Taura, H. Takahashi, Y. Nishimura, K. Tatani, M. Kawamura, H. Nakayama, T. Nagano, K. Ohno, H. Iwamoto, S. Kadomura, T. Hirayama","doi":"10.1109/IEDM.2016.7838375","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838375","url":null,"abstract":"We have successfully mass-produced novel stacked back-illuminated CMOS image sensors (BI-CIS). In the new CIS, we introduced advanced Cu2Cu hybrid bonding that we had developed. The electrical test results showed that our highly robust Cu2Cu hybrid bonding achieved remarkable connectivity and reliability. The performance of image sensor was also investigated and our novel stacked BI-CIS showed favorable results.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838457
A. Huang
Wide bandgap (WBG) power semiconductor devices have the capability to reach higher voltage, higher frequency and higher temperature compared with silicon based power devices. These capabilities have the potentials to revolutionize the way we deliver and manage power in the future. This paper reviews the WBG progress and their potential transformative impacts on low voltage, medium voltage and high voltage power delivery systems.
{"title":"Wide bandgap (WBG) power devices and their impacts on power delivery systems","authors":"A. Huang","doi":"10.1109/IEDM.2016.7838457","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838457","url":null,"abstract":"Wide bandgap (WBG) power semiconductor devices have the capability to reach higher voltage, higher frequency and higher temperature compared with silicon based power devices. These capabilities have the potentials to revolutionize the way we deliver and manage power in the future. This paper reviews the WBG progress and their potential transformative impacts on low voltage, medium voltage and high voltage power delivery systems.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838470
H. Oka, M. Koyama, T. Tomita, T. Amamoto, K. Tominaga, S. Tanaka, T. Hosoi, T. Shimura, H. Watanabe
Record-high mobility Ge-based TFT (μfe: 423 cm2/Vs) and significant enhancement of near-infrared (NIR) luminescence (×54 Ge bulk) were demonstrated with single-crystalline GeSn layer on transparent substrate grown by a novel liquid-phase crystallization technique. Our GeSn growth scheme is fully compatible with the conventional CMOS process and can provide high-quality tensile-strained p- and n-type GeSn layers, thus paving the way for monolithic optoelectronic integration available not only for optical communications but also for NIR imaging and biochemical sensing with wide wavelength range.
采用新型液相结晶技术在透明衬底上生长单晶GeSn层，证明了创纪录的高迁移率(μfe: 423 cm2/Vs)和近红外(NIR)发光(×54 Ge bulk)的显著增强。我们的GeSn生长方案与传统的CMOS工艺完全兼容，可以提供高质量的拉伸应变p型和n型GeSn层，从而为单片光电集成铺平了道路，不仅可用于光通信，还可用于近红外成像和宽波长范围的生化传感。
{"title":"High-mobility TFT and enhanced luminescence utilizing nucleation-controlled GeSn growth on transparent substrate for monolithic optoelectronic integration","authors":"H. Oka, M. Koyama, T. Tomita, T. Amamoto, K. Tominaga, S. Tanaka, T. Hosoi, T. Shimura, H. Watanabe","doi":"10.1109/IEDM.2016.7838470","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838470","url":null,"abstract":"Record-high mobility Ge-based TFT (μfe: 423 cm2/Vs) and significant enhancement of near-infrared (NIR) luminescence (×54 Ge bulk) were demonstrated with single-crystalline GeSn layer on transparent substrate grown by a novel liquid-phase crystallization technique. Our GeSn growth scheme is fully compatible with the conventional CMOS process and can provide high-quality tensile-strained p- and n-type GeSn layers, thus paving the way for monolithic optoelectronic integration available not only for optical communications but also for NIR imaging and biochemical sensing with wide wavelength range.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125201682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838522
S. Lombardo, E. Wu, J. Stathis
Through comparison with a large data set, we show that progressive breakdown (PBD) of gate oxides is described by a physical model coupling carrier energy dissipation to electromigration producing the PBD growth. Dependence on temperature, voltage, carrier type, oxide thickness, and the statistics are well described in a consistent framework.
{"title":"Comprehensive model for progressive breakdown in nFETs and pFETs","authors":"S. Lombardo, E. Wu, J. Stathis","doi":"10.1109/IEDM.2016.7838522","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838522","url":null,"abstract":"Through comparison with a large data set, we show that progressive breakdown (PBD) of gate oxides is described by a physical model coupling carrier energy dissipation to electromigration producing the PBD growth. Dependence on temperature, voltage, carrier type, oxide thickness, and the statistics are well described in a consistent framework.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838438
Qingzhu Zhang, H. Yin, Jun Luo, Hong Yang, Lingkuan Meng, Yudong Li, Zhenhua Wu, Yanbo Zhang, Yongkui Zhang, Changliang Qin, Junjie Li, Jianfeng Gao, Guilei Wang, W. Xiong, J. Xiang, Zhangyu Zhou, S. Mao, Gaobo Xu, Jinbiao Liu, Y. Qu, Tao Yang, Junfeng Li, Qiuxia Xu, Jiang Yan, Huilong Zhu, Chao Zhao, Tianchun Ye
The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.
{"title":"FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin","authors":"Qingzhu Zhang, H. Yin, Jun Luo, Hong Yang, Lingkuan Meng, Yudong Li, Zhenhua Wu, Yanbo Zhang, Yongkui Zhang, Changliang Qin, Junjie Li, Jianfeng Gao, Guilei Wang, W. Xiong, J. Xiang, Zhangyu Zhou, S. Mao, Gaobo Xu, Jinbiao Liu, Y. Qu, Tao Yang, Junfeng Li, Qiuxia Xu, Jiang Yan, Huilong Zhu, Chao Zhao, Tianchun Ye","doi":"10.1109/IEDM.2016.7838438","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838438","url":null,"abstract":"The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123785726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838468
R. Carboni, S. Ambrogio, Wei Chen, M. Siddik, J. Harms, Andy Lyle, Witold Kula, Gurtej S. Sandhu, Daniele Ielmini
Perpendicular spin-transfer torque (p-STT) memory is attracting an increasing interest as storage class memory (SCM) or static/dynamic RAM replacement. In these applications, high speed and extended endurance are essential and sometimes conflicting requirements. This work addresses cycling endurance of p-STT devices by pulsed experiments and modeling of the dielectric breakdown. We present a new endurance model able to predict the STT endurance as a function of applied voltage, pulse width, pulse polarity and delay time. The trade-off between write time and endurance for RAM replacement is finally addressed.
{"title":"Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory","authors":"R. Carboni, S. Ambrogio, Wei Chen, M. Siddik, J. Harms, Andy Lyle, Witold Kula, Gurtej S. Sandhu, Daniele Ielmini","doi":"10.1109/IEDM.2016.7838468","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838468","url":null,"abstract":"Perpendicular spin-transfer torque (p-STT) memory is attracting an increasing interest as storage class memory (SCM) or static/dynamic RAM replacement. In these applications, high speed and extended endurance are essential and sometimes conflicting requirements. This work addresses cycling endurance of p-STT devices by pulsed experiments and modeling of the dielectric breakdown. We present a new endurance model able to predict the STT endurance as a function of applied voltage, pulse width, pulse polarity and delay time. The trade-off between write time and endurance for RAM replacement is finally addressed.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133726783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838504
M. Asada, S. Suzuki
We report on our recent results of resonant tunneling diodes oscillating in the terahertz frequency range, including the structures for high frequency oscillation up to 1.92 THz at room temperature, high output power, high-speed direct modulation for wireless communication, and frequency tenability for spectroscopy.
{"title":"Resonant-tunneling-diode terahertz oscillators and applications","authors":"M. Asada, S. Suzuki","doi":"10.1109/IEDM.2016.7838504","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838504","url":null,"abstract":"We report on our recent results of resonant tunneling diodes oscillating in the terahertz frequency range, including the structures for high frequency oscillation up to 1.92 THz at room temperature, high output power, high-speed direct modulation for wireless communication, and frequency tenability for spectroscopy.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130486730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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