Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838336
C. Zota, Fredrik Lindelow, L. Wernersson, E. Lind
We demonstrate InGaAs tri-gate MOSFETs with an on-current of ION = 650 μA/μm at VDD = 0.5 V and IOFF = 100 nA/μm, enabled by an inverse subthreshold slope of SS = 66 mV/decade and transconductance of gm = 3 mS/μm, a Q-factor of 45. This is the highest reported Ion for both Si-based and III-V MOSFETs. These results continue to push III-V MOSFET experimental performance towards its theoretical limit. We find an improvement in SS from 81 to 75 mV/dec. as the effective oxide thickness (EOT) is scaled down from 1.4 to 1 nm, as well as improvements in SS, gd and DIBL from reducing the nanowire width. We also find that electron mobility remains constant as the width is scaled to 18 nm.
{"title":"InGaAs tri-gate MOSFETs with record on-current","authors":"C. Zota, Fredrik Lindelow, L. Wernersson, E. Lind","doi":"10.1109/IEDM.2016.7838336","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838336","url":null,"abstract":"We demonstrate InGaAs tri-gate MOSFETs with an on-current of I<inf>ON</inf> = 650 μA/μm at V<inf>DD</inf> = 0.5 V and I<inf>OFF</inf> = 100 nA/μm, enabled by an inverse subthreshold slope of SS = 66 mV/decade and transconductance of gm = 3 mS/μm, a Q-factor of 45. This is the highest reported Ion for both Si-based and III-V MOSFETs. These results continue to push III-V MOSFET experimental performance towards its theoretical limit. We find an improvement in SS from 81 to 75 mV/dec. as the effective oxide thickness (EOT) is scaled down from 1.4 to 1 nm, as well as improvements in SS, gd and DIBL from reducing the nanowire width. We also find that electron mobility remains constant as the width is scaled to 18 nm.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130645932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838490
Sung-Woong Chung, T. Kishi, Jeongsoo Park, M. Yoshikawa, Kyoung-Hwan Park, T. Nagase, K. Sunouchi, H. Kanaya, G. Kim, K. Noma, Mun-Haeng Lee, A. Yamamoto, KwangMyoung Rho, K. Tsuchida, Suock Chung, J. Yi, Hyeongon Kim, Chun Yun-Seok, H. Oyamatsu, Sung-Kee Hong
For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance control process, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.
{"title":"4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure","authors":"Sung-Woong Chung, T. Kishi, Jeongsoo Park, M. Yoshikawa, Kyoung-Hwan Park, T. Nagase, K. Sunouchi, H. Kanaya, G. Kim, K. Noma, Mun-Haeng Lee, A. Yamamoto, KwangMyoung Rho, K. Tsuchida, Suock Chung, J. Yi, Hyeongon Kim, Chun Yun-Seok, H. Oyamatsu, Sung-Kee Hong","doi":"10.1109/IEDM.2016.7838490","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838490","url":null,"abstract":"For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance control process, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838445
L. Tao, Dan-Yang Wang, H. Tian, Zhenyi Ju, Y. Liu, Yuan-Quan Chen, Qian‐Yi Xie, Haiming Zhao, Yi Yang, T. Ren
Tunable and wearable strain sensors with high gauge factor (GF) and large strain range based on laser patterned graphene flakes (LPGF) are demonstrated in this paper. The performance can be adjusted by laser patterning, resulting in a preferable GF (up to 457) or strain range (over 100%), both of which are significantly higher than most of the state-of-the-art graphene strain sensors. Most importantly, the tunable strain sensors with high GF and large strain range can be fabricated simultaneously by a one-step laser patterning. These tunable strain sensors can meet the demands of monitoring both subtle and large human motions, indicating that they will have great potentials in health care, voice recognition, gesture control and many other areas.
{"title":"Tunable and wearable high performance strain sensors based on laser patterned graphene flakes","authors":"L. Tao, Dan-Yang Wang, H. Tian, Zhenyi Ju, Y. Liu, Yuan-Quan Chen, Qian‐Yi Xie, Haiming Zhao, Yi Yang, T. Ren","doi":"10.1109/IEDM.2016.7838445","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838445","url":null,"abstract":"Tunable and wearable strain sensors with high gauge factor (GF) and large strain range based on laser patterned graphene flakes (LPGF) are demonstrated in this paper. The performance can be adjusted by laser patterning, resulting in a preferable GF (up to 457) or strain range (over 100%), both of which are significantly higher than most of the state-of-the-art graphene strain sensors. Most importantly, the tunable strain sensors with high GF and large strain range can be fabricated simultaneously by a one-step laser patterning. These tunable strain sensors can meet the demands of monitoring both subtle and large human motions, indicating that they will have great potentials in health care, voice recognition, gesture control and many other areas.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125173024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838351
Dongil Lee, Byung-Hyun Lee, J. Yoon, Bongsik Choi, Jun-Y. Park, Dae-Chul Ahn, C. Kim, Byeong-Woon Hwang, Seung‐Bae Jeon, Hyun Jun Ahn, Myeong-Lok Seol, Min-Ho Kang, B. Cho, Sung-Jin Choi, Yang‐Kyu Choi
Fully wrap-gated carbon nanotube (CNT) transistors with vertically suspended (VS) semiconducting single-walled CNTs, purified up to 99.9%, are demonstrated for the first time. Without a sacrifice of scalability, remarkably enhanced gate controllability and charge transport capabilities were achieved due to the geometrical advantage of the gate-all-around (GAA) structure with multiple channels. The VS channels were formed with the aid of a silicon-processed vertically integrated nanowire frame, offering high completeness and compatibility with silicon processes. This approach will increase the applicability of CNTs toward high-performance emerging materials.
{"title":"First demonstration of a wrap-gated CNT-FET with vertically-suspended channels","authors":"Dongil Lee, Byung-Hyun Lee, J. Yoon, Bongsik Choi, Jun-Y. Park, Dae-Chul Ahn, C. Kim, Byeong-Woon Hwang, Seung‐Bae Jeon, Hyun Jun Ahn, Myeong-Lok Seol, Min-Ho Kang, B. Cho, Sung-Jin Choi, Yang‐Kyu Choi","doi":"10.1109/IEDM.2016.7838351","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838351","url":null,"abstract":"Fully wrap-gated carbon nanotube (CNT) transistors with vertically suspended (VS) semiconducting single-walled CNTs, purified up to 99.9%, are demonstrated for the first time. Without a sacrifice of scalability, remarkably enhanced gate controllability and charge transport capabilities were achieved due to the geometrical advantage of the gate-all-around (GAA) structure with multiple channels. The VS channels were formed with the aid of a silicon-processed vertically integrated nanowire frame, offering high completeness and compatibility with silicon processes. This approach will increase the applicability of CNTs toward high-performance emerging materials.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838402
M. Kobayashi, Nozomu Ueyama, Kyungmin Jang, T. Hiramoto
We have experimentally investigated the polarization-limited operation speed of Negative Capacitance FET (NCFET) through direct measurement of negative capacitance in transient behavior of ferroelectric HfO2 capacitor and physics-based modeling, for the first time. Systematic analysis of frequency dependence and transient characteristics of ferroelectric HfO2 capacitor enabled accurate parameter extraction. With extracted parameters, our newly developed time-dependent NCFET model provided the evidence that NCFET can operate at >MHz, which is suitable for ultralow power IoT application.
{"title":"Experimental study on polarization-limited operation speed of negative capacitance FET with ferroelectric HfO2","authors":"M. Kobayashi, Nozomu Ueyama, Kyungmin Jang, T. Hiramoto","doi":"10.1109/IEDM.2016.7838402","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838402","url":null,"abstract":"We have experimentally investigated the polarization-limited operation speed of Negative Capacitance FET (NCFET) through direct measurement of negative capacitance in transient behavior of ferroelectric HfO2 capacitor and physics-based modeling, for the first time. Systematic analysis of frequency dependence and transient characteristics of ferroelectric HfO2 capacitor enabled accurate parameter extraction. With extracted parameters, our newly developed time-dependent NCFET model provided the evidence that NCFET can operate at >MHz, which is suitable for ultralow power IoT application.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131368636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838486
K. Kim, D. English, S. McKenzie, F. Wu, E. Stark, J. Seymour, P. Ku, K. Wise, G. Buzsáki, E. Yoon
We present the micromachined GaN-on-Si μLED optoelectrodes with neuron-sized LEDs monolithically integrated on a thin narrow silicon shank for optical stimulation and electrical recording in a behaving animal. The fabricated μLEDs show an optical power of 1.9 μW at 4 V from a small size of 15 μm × 10 μm with a peak plug efficiency of 0.6 %. This allows high spatial and temporal resolution optogenetic studies from the μLED array in a small pitch of 60 μm along with the integrated recording electrodes in 20-μm pitch. Stimulation artifacts were significantly mitigated by two-metal-layer shielding topology. In vivo validation of the fabricated optoelectrode confirmed the successful light-induced modulation of neuronal activities in hippocampus with square optical pulses of 100-ms duration.
{"title":"GaN-on-Si μLED optoelectrodes for high-spatiotemporal-accuracy optogenetics in freely behaving animals","authors":"K. Kim, D. English, S. McKenzie, F. Wu, E. Stark, J. Seymour, P. Ku, K. Wise, G. Buzsáki, E. Yoon","doi":"10.1109/IEDM.2016.7838486","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838486","url":null,"abstract":"We present the micromachined GaN-on-Si μLED optoelectrodes with neuron-sized LEDs monolithically integrated on a thin narrow silicon shank for optical stimulation and electrical recording in a behaving animal. The fabricated μLEDs show an optical power of 1.9 μW at 4 V from a small size of 15 μm × 10 μm with a peak plug efficiency of 0.6 %. This allows high spatial and temporal resolution optogenetic studies from the μLED array in a small pitch of 60 μm along with the integrated recording electrodes in 20-μm pitch. Stimulation artifacts were significantly mitigated by two-metal-layer shielding topology. In vivo validation of the fabricated optoelectrode confirmed the successful light-induced modulation of neuronal activities in hippocampus with square optical pulses of 100-ms duration.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132572792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838509
Z. Ahmad, W. Choi, N. Sharma, J. Zhang, Q. Zhong, D. Kim, Z. Chen, Y. Zhang, R. Han, D. Shim, S. Sankaran, E. Seok, C. Cao, C. Mao, R. Schueler, I. Medvedev, David John Lary, Hyun-Joo Nam, P. Raskin, F. Delucia, J. P. McMillan, C. Neese, I. Kim, I. Momson, P. Yellswarapu, S. Dong, B.-K. Kim
Recent advances of CMOS technology and circuits have made it an alternative for realizing capable and affordable THz systems. With process and circuit optimization, it should be possible to generate useful power and coherently detect signals at frequencies beyond 1THz, and incoherently detect signals at 40THz in CMOS.
{"title":"Devices and circuits in CMOS for THz applications","authors":"Z. Ahmad, W. Choi, N. Sharma, J. Zhang, Q. Zhong, D. Kim, Z. Chen, Y. Zhang, R. Han, D. Shim, S. Sankaran, E. Seok, C. Cao, C. Mao, R. Schueler, I. Medvedev, David John Lary, Hyun-Joo Nam, P. Raskin, F. Delucia, J. P. McMillan, C. Neese, I. Kim, I. Momson, P. Yellswarapu, S. Dong, B.-K. Kim","doi":"10.1109/IEDM.2016.7838509","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838509","url":null,"abstract":"Recent advances of CMOS technology and circuits have made it an alternative for realizing capable and affordable THz systems. With process and circuit optimization, it should be possible to generate useful power and coherently detect signals at frequencies beyond 1THz, and incoherently detect signals at 40THz in CMOS.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838510
A. Afzalian, M. Passlack, Y. Yeo
We report an in-depth atomistic study of the scaling potential of III-V GAA nanowire heterojunction TFET using an innovative tight-binding mode space (MS) technique with large speedup (up to 250×) while keeping good accuracy (error < 1%). It is shown that both n- and pTFET performances are best above 20 nm gate length for a cross-section of 5.5 nm in the [111] crystal orientation. At Vdd = 0.3 V and Ioff = 50 pA/μm, the on-current (Ion) and energy-delay product (ETP) gain over a Si NW GAA MOSFET are 58× and 56× respectively. In a beyond 5 nm node low power ITRS 2.0 horizontal GAA design rule however, where the gate length is restricted to 12 nm, a [100] orientation is best but features up to 3× Ion and 2.4× ETP degradation vs. the 20 nm TFET GAA design.
{"title":"Scaling perspective for III-V broken gap nanowire TFETs: An atomistic study using a fast tight-binding mode-space NEGF model","authors":"A. Afzalian, M. Passlack, Y. Yeo","doi":"10.1109/IEDM.2016.7838510","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838510","url":null,"abstract":"We report an in-depth atomistic study of the scaling potential of III-V GAA nanowire heterojunction TFET using an innovative tight-binding mode space (MS) technique with large speedup (up to 250×) while keeping good accuracy (error < 1%). It is shown that both n- and pTFET performances are best above 20 nm gate length for a cross-section of 5.5 nm in the [111] crystal orientation. At V<inf>dd</inf> = 0.3 V and I<inf>off</inf> = 50 pA/μm, the on-current (Ion) and energy-delay product (ETP) gain over a Si NW GAA MOSFET are 58× and 56× respectively. In a beyond 5 nm node low power ITRS 2.0 horizontal GAA design rule however, where the gate length is restricted to 12 nm, a [100] orientation is best but features up to 3× I<inf>on</inf> and 2.4× ETP degradation vs. the 20 nm TFET GAA design.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134544466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838536
I-Hsieh Wong, Fang-Liang Lu, Shih-Hsien Huang, Hung-Yu Ye, Chun-Ti Lu, Jhih-Yang Yan, Yu-Cheng Shen, Yu-Jiun Peng, H. Lan, C. W. Liu
The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.
{"title":"High performance Ge junctionless gate-all-around NFETs with simultaneous Ion =1235 μA/μm at Vov=Vds=1V, SS=95 mV/dec, high Ion/Ioff=2×106, and reduced noise power density using S/D dopant recovery by selective laser annealing","authors":"I-Hsieh Wong, Fang-Liang Lu, Shih-Hsien Huang, Hung-Yu Ye, Chun-Ti Lu, Jhih-Yang Yan, Yu-Cheng Shen, Yu-Jiun Peng, H. Lan, C. W. Liu","doi":"10.1109/IEDM.2016.7838536","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838536","url":null,"abstract":"The low channel doping concentrations of 1.2×10<sup>19</sup> cm<sup>−3</sup> to deplete the channel and the high S/D doping of 1.2×10<sup>20</sup> cm<sup>−3</sup> to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×10<sup>6</sup>, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134068691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838396
V. Kottler
This work describes a holistic approach to the application of the Robustness Validation methodology to the qualification of non-volatile memories (NVM) for automotive applications, as well as the resulting requirements to the NVM supplier and to the NVM design and technology.
{"title":"Automotive requirements to non-volatile memories — A holistic approach to qualification","authors":"V. Kottler","doi":"10.1109/IEDM.2016.7838396","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838396","url":null,"abstract":"This work describes a holistic approach to the application of the Robustness Validation methodology to the qualification of non-volatile memories (NVM) for automotive applications, as well as the resulting requirements to the NVM supplier and to the NVM design and technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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