Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838446
S. K. Ameri, R. Ho, H. Jang, Yu Wang, David M Schnyer, D. Akinwande, N. Lu
We report the first demonstration of a graphene-based epidermal sensor system (GESS) with total thickness below 500 nm. The GESS is manufactured by the cost-effective and rapid “cut-and-paste” method on tattoo paper and can be directly laminated on human skin like a temporary transfer tattoo. Without any tape or adhesive, the GESS completely conforms to the microscopic morphology of human skin via van der Waals interaction. The softness and transparency of the GESS, make it the world's first epidermal sensor system that is invisible both mechanically and optically. The GESS has been successfully applied to measure electrocardiogram (ECG), electroencephalogram (EEG) and electromyogram (EMG) with signal-to-noise ratio comparable with commercial electrodes, in addition to skin temperature and skin hydration. The thin and transparent graphene epidermal sensor can be used for the first time enable simultaneous electrical and optical epidermal sensing.
{"title":"Thinnest transparent epidermal sensor system based on graphene","authors":"S. K. Ameri, R. Ho, H. Jang, Yu Wang, David M Schnyer, D. Akinwande, N. Lu","doi":"10.1109/IEDM.2016.7838446","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838446","url":null,"abstract":"We report the first demonstration of a graphene-based epidermal sensor system (GESS) with total thickness below 500 nm. The GESS is manufactured by the cost-effective and rapid “cut-and-paste” method on tattoo paper and can be directly laminated on human skin like a temporary transfer tattoo. Without any tape or adhesive, the GESS completely conforms to the microscopic morphology of human skin via van der Waals interaction. The softness and transparency of the GESS, make it the world's first epidermal sensor system that is invisible both mechanically and optically. The GESS has been successfully applied to measure electrocardiogram (ECG), electroencephalogram (EEG) and electromyogram (EMG) with signal-to-noise ratio comparable with commercial electrodes, in addition to skin temperature and skin hydration. The thin and transparent graphene epidermal sensor can be used for the first time enable simultaneous electrical and optical epidermal sensing.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130950185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838532
S. Miyazaki, K. Makihara, A. Ohta, M. Ikeda
We have demonstrated high density formation of Si quantum dots with Ge core on thermally-grown SiO2 with control of highly-selective CVD. Through luminescence measurements, we have reported characteristic carrier confinement and recombination properties in the Ge core. Also, an impact of P delta-doping to the Ge core on the properties were shown.
{"title":"Processing and characterization of Si/Ge quantum dots","authors":"S. Miyazaki, K. Makihara, A. Ohta, M. Ikeda","doi":"10.1109/IEDM.2016.7838532","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838532","url":null,"abstract":"We have demonstrated high density formation of Si quantum dots with Ge core on thermally-grown SiO2 with control of highly-selective CVD. Through luminescence measurements, we have reported characteristic carrier confinement and recombination properties in the Ge core. Also, an impact of P delta-doping to the Ge core on the properties were shown.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131189258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838518
G. Jiao, M. Toledano-Luque, K. Nam, Nakanishi Toshiro, Seung-Hun Lee, Jin-Soak Kim, T. Kauerauf, Eun-ae Chung, D. Bae, Geumjong Bae, Dong-Won Kim, K. Hwang
In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (Ev) lowers the Eox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.
{"title":"Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB","authors":"G. Jiao, M. Toledano-Luque, K. Nam, Nakanishi Toshiro, Seung-Hun Lee, Jin-Soak Kim, T. Kauerauf, Eun-ae Chung, D. Bae, Geumjong Bae, Dong-Won Kim, K. Hwang","doi":"10.1109/IEDM.2016.7838518","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838518","url":null,"abstract":"In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (Ev) lowers the Eox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838448
J. M. Nassar, G. T. Sevilla, Seneca J. Velling, M. D. Cordero, M. Hussain
We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.
{"title":"A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications","authors":"J. M. Nassar, G. T. Sevilla, Seneca J. Velling, M. D. Cordero, M. Hussain","doi":"10.1109/IEDM.2016.7838448","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838448","url":null,"abstract":"We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133575591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838346
C. Nail, G. Molas, P. Blaise, G. Piccolboni, B. Sklénard, C. Cagli, M. Bernard, A. Roule, M. Azzaz, E. Vianello, C. Carabasse, R. Berthier, D. Cooper, C. Pelissier, T. Magis, G. Ghibaudo, C. Vallée, D. Bedeau, D. Bedau, O. Mosendz, B. De Salvo, L. Perniola
In this paper we clarify for the first time the correlation between endurance, window margin and retention of Resistive RAM. To this aim, various classes of RRAM (OXRAM and CBRAM) are investigated, showing high window margin up to 1010 cycles or high 300°C retention. From first principle calculations, we analyze the conducting filament composition for the various RRAM technologies, and extract the key filament features. We then propose an analytical model to calculate the dependence between endurance, window margin and retention, linking material parameters to memory characteristics.
{"title":"Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations","authors":"C. Nail, G. Molas, P. Blaise, G. Piccolboni, B. Sklénard, C. Cagli, M. Bernard, A. Roule, M. Azzaz, E. Vianello, C. Carabasse, R. Berthier, D. Cooper, C. Pelissier, T. Magis, G. Ghibaudo, C. Vallée, D. Bedeau, D. Bedau, O. Mosendz, B. De Salvo, L. Perniola","doi":"10.1109/IEDM.2016.7838346","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838346","url":null,"abstract":"In this paper we clarify for the first time the correlation between endurance, window margin and retention of Resistive RAM. To this aim, various classes of RRAM (OXRAM and CBRAM) are investigated, showing high window margin up to 1010 cycles or high 300°C retention. From first principle calculations, we analyze the conducting filament composition for the various RRAM technologies, and extract the key filament features. We then propose an analytical model to calculate the dependence between endurance, window margin and retention, linking material parameters to memory characteristics.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132004593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838491
Y. Song, J. Lee, H. Shin, K. H. Lee, K. Suh, J. R. Kang, S. Pyo, H. Jung, S. Hwang, G. Koh, Sechung Oh, Soojeoung Park, Jinhak Kim, Jae-Kyun Park, Ju-Sik Kim, K. Hwang, G. Jeong, K. Lee, E. Jung
We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.
{"title":"Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic","authors":"Y. Song, J. Lee, H. Shin, K. H. Lee, K. Suh, J. R. Kang, S. Pyo, H. Jung, S. Hwang, G. Koh, Sechung Oh, Soojeoung Park, Jinhak Kim, Jae-Kyun Park, Ju-Sik Kim, K. Hwang, G. Jeong, K. Lee, E. Jung","doi":"10.1109/IEDM.2016.7838491","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838491","url":null,"abstract":"We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115776792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838341
U. Radhakrishna, Pilsoon Choi, J. Grajal, L. Peh, T. Palacios, D. Antoniadis
This study is a first demonstration of the use of a physical compact model as a tool to identify technology bottlenecks to the linearity performance of emerging devices such as GaN HEMTs and to provide solutions to improve linearity both through device-design and circuit-design techniques. GaN-based HEMTs are emerging as key technology solutions in wireless communication systems that can address the increasing demand for highly efficient, linear amplification of digitally modulated information to cater to new applications such as personal communication, internet of things, 5G etc [1]. The primary advantage of GaN-HEMTs in terms of higher bandgap, carrier-mobility and charge-density can yield better output power (Pout), and power-added-efficiency (PAE) but the linearity behavior of GaN-based power amplifiers (PAs) that trades-off with the aforementioned figures of merit (FoMs) is still to be understood. Non-linearity results in adjacent channel interference, spectral regrowth, and degrading error vector magnitude (EVM) that impose bandwidth constraints and higher bit error rate (BER) for complex modulated signals.
{"title":"Study of RF-circuit linearity performance of GaN HEMT technology using the MVSG compact device model","authors":"U. Radhakrishna, Pilsoon Choi, J. Grajal, L. Peh, T. Palacios, D. Antoniadis","doi":"10.1109/IEDM.2016.7838341","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838341","url":null,"abstract":"This study is a first demonstration of the use of a physical compact model as a tool to identify technology bottlenecks to the linearity performance of emerging devices such as GaN HEMTs and to provide solutions to improve linearity both through device-design and circuit-design techniques. GaN-based HEMTs are emerging as key technology solutions in wireless communication systems that can address the increasing demand for highly efficient, linear amplification of digitally modulated information to cater to new applications such as personal communication, internet of things, 5G etc [1]. The primary advantage of GaN-HEMTs in terms of higher bandgap, carrier-mobility and charge-density can yield better output power (Pout), and power-added-efficiency (PAE) but the linearity behavior of GaN-based power amplifiers (PAs) that trades-off with the aforementioned figures of merit (FoMs) is still to be understood. Non-linearity results in adjacent channel interference, spectral regrowth, and degrading error vector magnitude (EVM) that impose bandwidth constraints and higher bit error rate (BER) for complex modulated signals.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115805600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838538
Tsung-Yeh Yang, A. Andreev, Y. Yamaoka, T. Ferrus, S. Oda, T. Kodera, D. Williams
For the first time, long coherence times (T2) up to tens of microseconds were observed in a silicon-based charge quantum bit (qubit) device at 4.2 K. The coherence times demonstrated in this paper are two orders of magnitude longer, and the operating temperature is two orders of magnitude higher than the reported semiconductor charge qubit systems (see Table 1). In contrast to other approaches, in this work the qubits are formed by trench isolation instead of surface gate-defined. The qubits were fabricated on P-doped silicon-on-insulator (SOI) wafers through current industrial semiconductor manufacturing technology. We have demonstrated the accurate readout of the qubits' electronic states by using a single electron transistor (SET) as an electrometer. The first observation of the interaction between two sets of capacitively coupled charge movements was achieved by using our charge detection technique.
{"title":"Quantum information processing in a silicon-based system","authors":"Tsung-Yeh Yang, A. Andreev, Y. Yamaoka, T. Ferrus, S. Oda, T. Kodera, D. Williams","doi":"10.1109/IEDM.2016.7838538","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838538","url":null,"abstract":"For the first time, long coherence times (T2) up to tens of microseconds were observed in a silicon-based charge quantum bit (qubit) device at 4.2 K. The coherence times demonstrated in this paper are two orders of magnitude longer, and the operating temperature is two orders of magnitude higher than the reported semiconductor charge qubit systems (see Table 1). In contrast to other approaches, in this work the qubits are formed by trench isolation instead of surface gate-defined. The qubits were fabricated on P-doped silicon-on-insulator (SOI) wafers through current industrial semiconductor manufacturing technology. We have demonstrated the accurate readout of the qubits' electronic states by using a single electron transistor (SET) as an electrometer. The first observation of the interaction between two sets of capacitively coupled charge movements was achieved by using our charge detection technique.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124206217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838550
Jhih-Yang Yan, Sun-Rong Jan, Yu-Jiun Peng, H. H. Lin, W. K. Wan, Y.-H. Huang, B. Hung, K.T. Chan, Michael Huang, M. Yang, C. Liu
A two-step pseudo isothermal plane model is used to calculate the thermal resistance of BEOL (Rth, beol). The intrinsic thermal resistances of 14nm FinFETs (Rth0, Device) are extracted with face-up (conventional measurement, heat flow from the channel to substrate) and face-down (flip-chip, heat flow from the channel to metal contact) configurations. Since the free convection of air has a large thermal resistance, the heat flow direction affects Rth0, Device. The face-up Rth0, Device is higher than face-down Rth0, Device. This is more significant for multi-finger FinFETs. The volume of hot spot affects the cooling time. In an inverter, the maximum temperature (Tmax) of pFET is higher than nFET due to the low thermal conductivity of SiGe S/D. Tmax and the high temperature duration can be controlled by the current and output capacitive loading of the inverter. The residual temperature in the channel and the temperatures of M1 layer are found too low to reflect the real device temperature, which may lead to an underestimation of device temperature with transient AC input.
{"title":"Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects","authors":"Jhih-Yang Yan, Sun-Rong Jan, Yu-Jiun Peng, H. H. Lin, W. K. Wan, Y.-H. Huang, B. Hung, K.T. Chan, Michael Huang, M. Yang, C. Liu","doi":"10.1109/IEDM.2016.7838550","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838550","url":null,"abstract":"A two-step pseudo isothermal plane model is used to calculate the thermal resistance of BEOL (Rth, beol). The intrinsic thermal resistances of 14nm FinFETs (Rth0, Device) are extracted with face-up (conventional measurement, heat flow from the channel to substrate) and face-down (flip-chip, heat flow from the channel to metal contact) configurations. Since the free convection of air has a large thermal resistance, the heat flow direction affects Rth0, Device. The face-up Rth0, Device is higher than face-down Rth0, Device. This is more significant for multi-finger FinFETs. The volume of hot spot affects the cooling time. In an inverter, the maximum temperature (Tmax) of pFET is higher than nFET due to the low thermal conductivity of SiGe S/D. Tmax and the high temperature duration can be controlled by the current and output capacitive loading of the inverter. The residual temperature in the channel and the temperatures of M1 layer are found too low to reflect the real device temperature, which may lead to an underestimation of device temperature with transient AC input.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114672872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838413
D. Marian, Elias Dib, T. Cusati, Alessandro Fortunelli, G. Iannaccone, G. Fiori
We propose two types of transistors based on lateral heterostructures of metallic and semiconducting phases of monolayer MoS2, whose top-down patterning has been recently demonstrated via electron beam irradiation [1]. The proposed transistors a MoS2 lateral heterostructure FET, and a “planar barristor”, a gate Schottky diode that is the full 2D counterpart of the graphene barristor device proposed in [2]. We evaluate their performance with ab-initio simulations using as a benchmark the CMOS technology roadmap.
{"title":"Two-dimensional transistors based on MoS2 lateral heterostructures","authors":"D. Marian, Elias Dib, T. Cusati, Alessandro Fortunelli, G. Iannaccone, G. Fiori","doi":"10.1109/IEDM.2016.7838413","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838413","url":null,"abstract":"We propose two types of transistors based on lateral heterostructures of metallic and semiconducting phases of monolayer MoS2, whose top-down patterning has been recently demonstrated via electron beam irradiation [1]. The proposed transistors a MoS2 lateral heterostructure FET, and a “planar barristor”, a gate Schottky diode that is the full 2D counterpart of the graphene barristor device proposed in [2]. We evaluate their performance with ab-initio simulations using as a benchmark the CMOS technology roadmap.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129312321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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