Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838410
E. Charbon, F. Sebastiano, Andrei Vladimirescu, H. Homulle, Stefan Visser, Lin Song, R. M. Incandela
Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.
{"title":"Cryo-CMOS for quantum computing","authors":"E. Charbon, F. Sebastiano, Andrei Vladimirescu, H. Homulle, Stefan Visser, Lin Song, R. M. Incandela","doi":"10.1109/IEDM.2016.7838410","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838410","url":null,"abstract":"Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123762944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838390
K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai
Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, — Vce(sat) reduction from 1.70 to 1.26 V — was experimentally confirmed for the 3D scaled IGBTs.
{"title":"Experimental verification of a 3D scaling principle for low Vce(sat) IGBT","authors":"K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, H. Iwai","doi":"10.1109/IEDM.2016.7838390","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838390","url":null,"abstract":"Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, — Vce(sat) reduction from 1.70 to 1.26 V — was experimentally confirmed for the 3D scaled IGBTs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116884689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.
{"title":"Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization","authors":"Qianqian Huang, Rundong Jia, Jiadi Zhu, Zhu Lv, Jiaxin Wang, Cheng Chen, Yang Zhao, Runsheng Wang, Weihai Bu, Wenbo Wang, Jin Kang, Kelu Hua, Hanming Wu, Shaofeng Yu, Yangyuan Wang, Ru Huang","doi":"10.1109/IEDM.2016.7838521","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838521","url":null,"abstract":"The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125265112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838400
M. H. Lee, Sheng-Ting Fan, C.-H. Tang, P. Chen, Y.-C. Chou, H. Chen, J. Kuo, M. Xie, S.-N. Liu, M. Liao, C. Jong, K.-S. Li, M.-C. Chen, C. Liu
Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.
{"title":"Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs","authors":"M. H. Lee, Sheng-Ting Fan, C.-H. Tang, P. Chen, Y.-C. Chou, H. Chen, J. Kuo, M. Xie, S.-N. Liu, M. Liao, C. Jong, K.-S. Li, M.-C. Chen, C. Liu","doi":"10.1109/IEDM.2016.7838400","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838400","url":null,"abstract":"Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115856672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838503
M. Urteaga, J. Hacker, Z. Griffith, A. Young, R. Pierson, P. Rowell, M. Seo, M. Rodwell
A 130 nm InP HBT IC technology has been developed capable of circuit demonstrations at > 600 GHz. Transistors demonstrate RF figures-of-merit ft > 500 GHz and fmax > 1 THz. The HBTs support high current densities > 25 mA/μm2 with a common-emitter breakdown voltage BVceo = 3.5 V. The technology includes a multi-level thin-film wiring environment capable of low-loss THz signal routing and high integration density. A large-signal HBT model has been developed capable of accurately predicting circuit performance at THz frequencies. Circuit demonstrations include fundamental oscillators and amplifiers operating at > 600 GHz as well as integrated transmitter and receiver circuits.
{"title":"A 130 nm InP HBT integrated circuit technology for THz electronics","authors":"M. Urteaga, J. Hacker, Z. Griffith, A. Young, R. Pierson, P. Rowell, M. Seo, M. Rodwell","doi":"10.1109/IEDM.2016.7838503","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838503","url":null,"abstract":"A 130 nm InP HBT IC technology has been developed capable of circuit demonstrations at > 600 GHz. Transistors demonstrate RF figures-of-merit f<inf>t</inf> > 500 GHz and f<inf>max</inf> > 1 THz. The HBTs support high current densities > 25 mA/μm<sup>2</sup> with a common-emitter breakdown voltage BV<inf>ceo</inf> = 3.5 V. The technology includes a multi-level thin-film wiring environment capable of low-loss THz signal routing and high integration density. A large-signal HBT model has been developed capable of accurately predicting circuit performance at THz frequencies. Circuit demonstrations include fundamental oscillators and amplifiers operating at > 600 GHz as well as integrated transmitter and receiver circuits.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124258822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838508
H.-T. Chen
Metamaterials and metasurfaces have demonstrated many unusual properties that are useful for creating high-performance terahertz devices and components. Integration of functional materials allows metasurfaces to expand their scope of applications. Here we show that hybrid metasurfaces can provide ultrafast modulation of terahertz waves that are critical for future applications in terahertz imaging and communications.
{"title":"Active terahertz metasurface devices","authors":"H.-T. Chen","doi":"10.1109/IEDM.2016.7838508","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838508","url":null,"abstract":"Metamaterials and metasurfaces have demonstrated many unusual properties that are useful for creating high-performance terahertz devices and components. Integration of functional materials allows metasurfaces to expand their scope of applications. Here we show that hybrid metasurfaces can provide ultrafast modulation of terahertz waves that are critical for future applications in terahertz imaging and communications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121726993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838478
Jeonghwan Song, Jaehyuk Park, Kibong Moon, J. Woo, Seokjae Lim, Jongmyung Yoo, Dongwook Lee, H. Hwang
AgTe/TiN/TiO2/TiN threshold switching (TS) device was monolithically integrated with silicon MOSFET to demonstrate steep subthreshold slope field-effect transistors. The TS device with AgTe top electrode showed the high on-current, since the Te allows an extraction of the Ag out of the filament. The TiN liner was also inserted at the AgTe/TiO2 interface to prevent in-diffusion of Ag into the TiO2 layer during back-end-of-line process. Finally, the transistor with TS device has a sub-5-mV/dec subthreshold slope (SS) and a high on/off current ratio (Ion/Ioff) of >108 with a low drain voltage (0.5 V) even after the 400°C annealing process.
{"title":"Monolithic integration of AgTe/TiO2 based threshold switching device with TiN liner for steep slope field-effect transistors","authors":"Jeonghwan Song, Jaehyuk Park, Kibong Moon, J. Woo, Seokjae Lim, Jongmyung Yoo, Dongwook Lee, H. Hwang","doi":"10.1109/IEDM.2016.7838478","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838478","url":null,"abstract":"AgTe/TiN/TiO2/TiN threshold switching (TS) device was monolithically integrated with silicon MOSFET to demonstrate steep subthreshold slope field-effect transistors. The TS device with AgTe top electrode showed the high on-current, since the Te allows an extraction of the Ag out of the filament. The TiN liner was also inserted at the AgTe/TiO2 interface to prevent in-diffusion of Ag into the TiO2 layer during back-end-of-line process. Finally, the transistor with TS device has a sub-5-mV/dec subthreshold slope (SS) and a high on/off current ratio (Ion/Ioff) of >108 with a low drain voltage (0.5 V) even after the 400°C annealing process.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838026
Seok-Hee Lee
Challenges in scaling of semiconductor memory technologies are reviewed with the focus on DRAM and NAND Flash while demands for memory improvement in the ICT industry are increasing. This paper introduces evolutionary and revolutionary paths to overcome scaling challenges of current and emerging memory technologies along with some promising solutions.
{"title":"Technology scaling challenges and opportunities of memory devices","authors":"Seok-Hee Lee","doi":"10.1109/IEDM.2016.7838026","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838026","url":null,"abstract":"Challenges in scaling of semiconductor memory technologies are reviewed with the focus on DRAM and NAND Flash while demands for memory improvement in the ICT industry are increasing. This paper introduces evolutionary and revolutionary paths to overcome scaling challenges of current and emerging memory technologies along with some promising solutions.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117260095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838404
C. Chang, K. Endo, K. Kato, C. Yokoyama, M. Takenaka, S. Takagi
The impact of La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs and the physical origins are systematically investigated. It is found that La2O3/ InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/ InGaAs MOSFETs because of higher fixed oxide charge density. Also, it is experimentally found for the first time that ALD La2O3 films with thermal budget lower than 300°C have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance (NC) effect have been demonstrated for the first time in W/La2O3(15nm)/InGaAs MOSFETs.
{"title":"Impact of La2O3/InGaAs MOS interface on InGaAs MOSFET performance and its application to InGaAs negative capacitance FET","authors":"C. Chang, K. Endo, K. Kato, C. Yokoyama, M. Takenaka, S. Takagi","doi":"10.1109/IEDM.2016.7838404","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838404","url":null,"abstract":"The impact of La<inf>2</inf>O<inf>3</inf>/InGaAs MOS interfaces on the performance of InGaAs MOSFETs and the physical origins are systematically investigated. It is found that La<inf>2</inf>O<inf>3</inf>/ InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al<inf>2</inf>O<inf>3</inf>/ InGaAs MOSFETs because of higher fixed oxide charge density. Also, it is experimentally found for the first time that ALD La<inf>2</inf>O<inf>3</inf> films with thermal budget lower than 300°C have ferroelectricity in W/La<inf>2</inf>O<inf>3</inf>/InGaAs MOS and W/La<inf>2</inf>O<inf>3</inf>/W MIM structures. The steep slope characteristics due to the negative capacitance (NC) effect have been demonstrated for the first time in W/La<inf>2</inf>O<inf>3</inf>(15nm)/InGaAs MOSFETs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838343
W. Kim, M. BrightSky, T. Masuda, N. Sosa, S. Kim, R. Bruce, F. Carta, G. Fraczak, H. Cheng, A. Ray, Y. Zhu, H. Lung, K. Suu, C. Lam
We present for the first time in-depth analysis of the outstanding endurance characteristics of an ALD-based confined phase change memory (PCM) [1] with a thin metallic liner. Experimental results confirm that both the proper metallic liner and the confined pore cell structure are required for a reliability advantage. This confined PCM with a metallic liner is found to be immune to classic endurance failure mechanisms. The void-free confined PCM yields a new record endurance (2×1012 cycles) with stabilized elemental segregation that does not result in stuck-SET failure.
{"title":"ALD-based confined PCM with a metallic liner toward unlimited endurance","authors":"W. Kim, M. BrightSky, T. Masuda, N. Sosa, S. Kim, R. Bruce, F. Carta, G. Fraczak, H. Cheng, A. Ray, Y. Zhu, H. Lung, K. Suu, C. Lam","doi":"10.1109/IEDM.2016.7838343","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838343","url":null,"abstract":"We present for the first time in-depth analysis of the outstanding endurance characteristics of an ALD-based confined phase change memory (PCM) [1] with a thin metallic liner. Experimental results confirm that both the proper metallic liner and the confined pore cell structure are required for a reliability advantage. This confined PCM with a metallic liner is found to be immune to classic endurance failure mechanisms. The void-free confined PCM yields a new record endurance (2×1012 cycles) with stabilized elemental segregation that does not result in stuck-SET failure.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123277313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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