Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838393
S. Tsuda, Y. Kawashima, K. Sonoda, A. Yoshitomi, T. Mihara, S. Narumi, M. Inoue, S. Muranaka, T. Maruyama, T. Yamashita, Y. Yamaguchi, D. Hisamoto
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the first time. Excellent subthreshold characteristics and small threshold-voltage variability owing to a Fin-structure are clarified. It is demonstrated that Fin top-corner effects are well suppressed by incremental step pulse programming for source side injection. Highly reliable data retention at 150 °C after 250K program/erase cycles is confirmed for advanced automotive system applications.
{"title":"First demonstration of FinFET split-gate MONOS for high-speed and highly-reliable embedded flash in 16/14nm-node and beyond","authors":"S. Tsuda, Y. Kawashima, K. Sonoda, A. Yoshitomi, T. Mihara, S. Narumi, M. Inoue, S. Muranaka, T. Maruyama, T. Yamashita, Y. Yamaguchi, D. Hisamoto","doi":"10.1109/IEDM.2016.7838393","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838393","url":null,"abstract":"FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the first time. Excellent subthreshold characteristics and small threshold-voltage variability owing to a Fin-structure are clarified. It is demonstrated that Fin top-corner effects are well suppressed by incremental step pulse programming for source side injection. Highly reliable data retention at 150 °C after 250K program/erase cycles is confirmed for advanced automotive system applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114898260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838469
M. Stelzer, F. Kreupl
Contact resistance and thermal degradation of metal-silicon contacts are challenges in nanoscale CMOS as well as in power device applications. Titanium silicide (TiSi) contacts are commonly used metal-silicon contacts, but are known to diffuse into the active region under high current stress. In this paper we show that a graphenic carbon (C) contact deposited on n-type silicon (C-Si) by CVD, has the same low Schottky barrier height of 0.45 eV as TiSi, but a much improved reliability against high current stress. The C-Si contact is over 108 times more stable against high current stress pulses than the conventionally used TiSi junction. The C-Si contact properties even show promise to establish an ultra-low, high temperature stable contact resistance. The finding has important consequences for the enhancement of reliability in power devices as well as in Schottky-diodes and electrical contacts to silicon in general.
{"title":"Graphenic carbon-silicon contacts for reliability improvement of metal-silicon junctions","authors":"M. Stelzer, F. Kreupl","doi":"10.1109/IEDM.2016.7838469","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838469","url":null,"abstract":"Contact resistance and thermal degradation of metal-silicon contacts are challenges in nanoscale CMOS as well as in power device applications. Titanium silicide (TiSi) contacts are commonly used metal-silicon contacts, but are known to diffuse into the active region under high current stress. In this paper we show that a graphenic carbon (C) contact deposited on n-type silicon (C-Si) by CVD, has the same low Schottky barrier height of 0.45 eV as TiSi, but a much improved reliability against high current stress. The C-Si contact is over 108 times more stable against high current stress pulses than the conventionally used TiSi junction. The C-Si contact properties even show promise to establish an ultra-low, high temperature stable contact resistance. The finding has important consequences for the enhancement of reliability in power devices as well as in Schottky-diodes and electrical contacts to silicon in general.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127155735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838513
N. Prasad, X. Mou, L. Register, S. Banerjee
The resonant tunneling characteristics of the inter-layer tunnel field-effect transistor (ITFET) within 2D van der Waals' materials can be made sharper by the use of multiple (m) intermediate well and tunnel barrier layers within a “mlTFET” variation. Ballistic quantum transport simulations are used to obtain the resonance characteristics in an MoS2 based-system, for specificity. Circuit simulations illustrate how the sharper resonance can lead to lower operating voltages and, thus, power, thereby improving the circuit performance.
{"title":"Multi-barrier inter-layer tunnel field-effect transistor","authors":"N. Prasad, X. Mou, L. Register, S. Banerjee","doi":"10.1109/IEDM.2016.7838513","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838513","url":null,"abstract":"The resonant tunneling characteristics of the inter-layer tunnel field-effect transistor (ITFET) within 2D van der Waals' materials can be made sharper by the use of multiple (m) intermediate well and tunnel barrier layers within a “mlTFET” variation. Ballistic quantum transport simulations are used to obtain the resonance characteristics in an MoS2 based-system, for specificity. Circuit simulations illustrate how the sharper resonance can lead to lower operating voltages and, thus, power, thereby improving the circuit performance.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127180371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838514
J. Duarte, S. Khandelwal, A. Khan, A. Sachid, Yen-Kai Lin, Huan-Lin Chang, S. Salahuddin, C. Hu
This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.
{"title":"Compact models of negative-capacitance FinFETs: Lumped and distributed charge models","authors":"J. Duarte, S. Khandelwal, A. Khan, A. Sachid, Yen-Kai Lin, Huan-Lin Chang, S. Salahuddin, C. Hu","doi":"10.1109/IEDM.2016.7838514","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838514","url":null,"abstract":"This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838369
O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, J. Barbe
In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confinement, this model is able to handle arbitrary NW/NS cross-section shape of stacked-planar and vertical GAA MOSFETs (circular, square, rectangular). This Nanowire Surface Potential (NSP) based model, validated both by numerical simulations and experimental data, is demonstrated to be very accurate in all operation regimes of GAA MOSFETs.
{"title":"NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs","authors":"O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, J. Barbe","doi":"10.1109/IEDM.2016.7838369","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838369","url":null,"abstract":"In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confinement, this model is able to handle arbitrary NW/NS cross-section shape of stacked-planar and vertical GAA MOSFETs (circular, square, rectangular). This Nanowire Surface Potential (NSP) based model, validated both by numerical simulations and experimental data, is demonstrated to be very accurate in all operation regimes of GAA MOSFETs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125119603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838374
M. Mori, Y. Sakata, M. Usuda, S. Kasuga, S. Yamahira, Y. Hirose, Y. Kato, A. Odagawa, T. Tanaka
We present a sensitivity-boosting technique by incorporating an avalanche photodiode into a normal photo-conversion region. Under a dark scene, an avalanche photodiode operation is selected, where the photo-electrons are multiplied up to 105 electrons. Under a bright scene, a photodiode operation is selected, where photo-electrons in proportional to light intensity are generated in a similar way to conventional CMOS image sensors. Alternating the two operations enables wide operational range extending to dark conditions.
{"title":"An APD-CMOS image sensor toward high sensitivity and wide dynamic range","authors":"M. Mori, Y. Sakata, M. Usuda, S. Kasuga, S. Yamahira, Y. Hirose, Y. Kato, A. Odagawa, T. Tanaka","doi":"10.1109/IEDM.2016.7838374","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838374","url":null,"abstract":"We present a sensitivity-boosting technique by incorporating an avalanche photodiode into a normal photo-conversion region. Under a dark scene, an avalanche photodiode operation is selected, where the photo-electrons are multiplied up to 105 electrons. Under a bright scene, a photodiode operation is selected, where photo-electrons in proportional to light intensity are generated in a similar way to conventional CMOS image sensors. Alternating the two operations enables wide operational range extending to dark conditions.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838428
Haitong Li, Tony F. Wu, Abbas Rahimi, Kai-Shin Li, M. Rusch, Chang-Hsien Lin, Juo-Luen Hsu, M. Sabry, S. Eryilmaz, Joon Sohn, W. Chiu, Min-Cheng Chen, Tsung-Ta Wu, J. Shieh, W. Yeh, J. Rabaey, S. Mitra, H. Wong
The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.
{"title":"Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition","authors":"Haitong Li, Tony F. Wu, Abbas Rahimi, Kai-Shin Li, M. Rusch, Chang-Hsien Lin, Juo-Luen Hsu, M. Sabry, S. Eryilmaz, Joon Sohn, W. Chiu, Min-Cheng Chen, Tsung-Ta Wu, J. Shieh, W. Yeh, J. Rabaey, S. Mitra, H. Wong","doi":"10.1109/IEDM.2016.7838428","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838428","url":null,"abstract":"The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123190358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838458
G. Deboy, M. Treu, O. Haeberlen, D. Neumayr
This paper discusses key parameters such as capacitances & switching losses for silicon, SiC and GaN power devices with respect to applications in switch mode power supplies. Whereas wide bandgap devices deliver roughly one order of magnitude lower charges stored in the output capacitance, the energy equivalent is nearly on par with latest generation super junction devices. Silicon devices will hence prevail in classic hard switching applications at moderate switching frequencies whereas SiC and GaN based power devices will play to their full benefits in resonant topologies at moderate to high switching frequencies.
{"title":"Si, SiC and GaN power devices: An unbiased view on key performance indicators","authors":"G. Deboy, M. Treu, O. Haeberlen, D. Neumayr","doi":"10.1109/IEDM.2016.7838458","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838458","url":null,"abstract":"This paper discusses key parameters such as capacitances & switching losses for silicon, SiC and GaN power devices with respect to applications in switch mode power supplies. Whereas wide bandgap devices deliver roughly one order of magnitude lower charges stored in the output capacitance, the energy equivalent is nearly on par with latest generation super junction devices. Silicon devices will hence prevail in classic hard switching applications at moderate switching frequencies whereas SiC and GaN based power devices will play to their full benefits in resonant topologies at moderate to high switching frequencies.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126290564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838542
N. Shukla, B. Grisafe, R. Ghosh, N. Jao, Ahmedullah Aziz, J. Frougier, M. Jerry, S. Sonde, S. Rouvimov, T. Orlova, S. Gupta, S. Datta
We demonstrate a novel Ag/HfO2 based threshold switch (TS) with a selectivity∼107, a high ON-state current (Ion) of 100 μA, and ∼10pA leakage current. The thresholding characteristics of the TS result from electrically triggered spontaneous formation and rupture of an Ag filament which acts an interstitial dopant in the HfO2 insulating matrix. Further, we harness the extreme non-linearity of the TS in (1) Selectors for Phase Change Memory (PCM) based cross-point memory. We show through array level simulations of a 1024kb memory, a read margin of 28% and write margin of 32% for a leakage power of <25μW (V/3 scheme); (2) A steep-slope sub-kT/q Phase-FET, experimentally demonstrating a switching-slope (SS) of 3mV/decade (over 5 orders of Ids), and >10x Ion improvement over the conventional FET (at iso-Ioff) at T=90C (50x at T=25C); making this a promising TS for both emerging memory, and steep-slope transistor applications.
{"title":"Ag/HfO2 based threshold switch with extreme non-linearity for unipolar cross-point memory and steep-slope phase-FETs","authors":"N. Shukla, B. Grisafe, R. Ghosh, N. Jao, Ahmedullah Aziz, J. Frougier, M. Jerry, S. Sonde, S. Rouvimov, T. Orlova, S. Gupta, S. Datta","doi":"10.1109/IEDM.2016.7838542","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838542","url":null,"abstract":"We demonstrate a novel Ag/HfO2 based threshold switch (TS) with a selectivity∼107, a high ON-state current (Ion) of 100 μA, and ∼10pA leakage current. The thresholding characteristics of the TS result from electrically triggered spontaneous formation and rupture of an Ag filament which acts an interstitial dopant in the HfO2 insulating matrix. Further, we harness the extreme non-linearity of the TS in (1) Selectors for Phase Change Memory (PCM) based cross-point memory. We show through array level simulations of a 1024kb memory, a read margin of 28% and write margin of 32% for a leakage power of <25μW (V/3 scheme); (2) A steep-slope sub-kT/q Phase-FET, experimentally demonstrating a switching-slope (SS) of 3mV/decade (over 5 orders of Ids), and >10x Ion improvement over the conventional FET (at iso-Ioff) at T=90C (50x at T=25C); making this a promising TS for both emerging memory, and steep-slope transistor applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123148601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/IEDM.2016.7838450
E. Memišević, J. Svensson, M. Hellenbrand, E. Lind, L. Wernersson
We present a vertical nanowire InAs/GaAsSb/GaSb TFET with a highly scaled InAs diameter (20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for Vds = 0.1–0.5 V and achieves an Ion = 10.6 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V. The lowest subthreshold swing achieved is 44 mV/dec. at Vds= 0.05 V. Furthermore, a benchmarking is performed against state-of-the-art TFETs and MOSFETs demonstrating a record high I60 and performance benefits for Vds between 0.1 and 0.3 V.
{"title":"Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V","authors":"E. Memišević, J. Svensson, M. Hellenbrand, E. Lind, L. Wernersson","doi":"10.1109/IEDM.2016.7838450","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838450","url":null,"abstract":"We present a vertical nanowire InAs/GaAsSb/GaSb TFET with a highly scaled InAs diameter (20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for V<inf>ds</inf> = 0.1–0.5 V and achieves an I<inf>on</inf> = 10.6 μA/μm for I<inf>off</inf> = 1 nA/μm at V<inf>ds</inf> = 0.3 V. The lowest subthreshold swing achieved is 44 mV/dec. at V<inf>ds</inf>= 0.05 V. Furthermore, a benchmarking is performed against state-of-the-art TFETs and MOSFETs demonstrating a record high I60 and performance benefits for V<inf>ds</inf> between 0.1 and 0.3 V.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129670563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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