Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558913
Chunfeng Hu, Mingxiang Wang, Meng Zhang, Bo Zhang, M. Wong
Device degradation of solution based metal-induced laterally crystallized (MILC) p-type poly-Si thin film transistors (TFTs) is studied under DC bias stresses, which is found to be dominated by negative bias temperature instability (NBTI) mechanism. While standard NBTI or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, a mixed NBTI and EI degradation is observed under combined low -Vg and -Vd stresses. Under high -Vd and moderate -Vg stress, pure hot carrier (HC) degradation cannot be observed, but a combined degradation of NBTI and HC occurs. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTspsila degradation.
{"title":"Degradation of solution based metal induced laterally crystallized p-type poly-Si TFTS under DC bias stresses","authors":"Chunfeng Hu, Mingxiang Wang, Meng Zhang, Bo Zhang, M. Wong","doi":"10.1109/RELPHY.2008.4558913","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558913","url":null,"abstract":"Device degradation of solution based metal-induced laterally crystallized (MILC) p-type poly-Si thin film transistors (TFTs) is studied under DC bias stresses, which is found to be dominated by negative bias temperature instability (NBTI) mechanism. While standard NBTI or electron injection (EI) is observed under -Vg or -Vd only stress, respectively, a mixed NBTI and EI degradation is observed under combined low -Vg and -Vd stresses. Under high -Vd and moderate -Vg stress, pure hot carrier (HC) degradation cannot be observed, but a combined degradation of NBTI and HC occurs. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTspsila degradation.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121224114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558941
K. Stawiasz, K. Jenkins, P. Lu
This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models.
{"title":"On-Chip circuit for monitoring frequency degradation due to NBTI","authors":"K. Stawiasz, K. Jenkins, P. Lu","doi":"10.1109/RELPHY.2008.4558941","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558941","url":null,"abstract":"This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558945
G. Haase
Low-k dielectrics used in interconnect systems of advanced microelectronics devices tend to degrade faster than gate oxide under electric field. As spacing between metal lines shrink, degradation models like the E-model, which are used to extrapolate time-dependent dielectric breakdown under constant voltage stress conditions back to operating voltages, give too conservative lifetimes. This paper suggests a simple model to explain the nature of the field-and current-induced degradation. It is based on observations of trapped charge and leakage behavior as a function of time under a constant voltage stress. This model predicts that as the stress voltage is lowered to a typical operating regime, the lifetime increases dramatically, and that using a more lenient radic(E )-model for lifetime prediction is still safe.
{"title":"An alternativemodel for interconnect low-k dielectric lifetime dependence on voltage","authors":"G. Haase","doi":"10.1109/RELPHY.2008.4558945","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558945","url":null,"abstract":"Low-k dielectrics used in interconnect systems of advanced microelectronics devices tend to degrade faster than gate oxide under electric field. As spacing between metal lines shrink, degradation models like the E-model, which are used to extrapolate time-dependent dielectric breakdown under constant voltage stress conditions back to operating voltages, give too conservative lifetimes. This paper suggests a simple model to explain the nature of the field-and current-induced degradation. It is based on observations of trapped charge and leakage behavior as a function of time under a constant voltage stress. This model predicts that as the stress voltage is lowered to a typical operating regime, the lifetime increases dramatically, and that using a more lenient radic(E )-model for lifetime prediction is still safe.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121353277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558875
N. Suzumura, S. Yamamoto, D. Kodama, Hidetoshi Miyazaki, M. Ogasawara, J. Komori, E. Murakami
The electric field and temperature dependencies of time-dependent dielectric breakdown (TDDB) degradation in Cu/low-k damascene structures are investigated using Cu/SiOC and Cu/SiCN damascene structures. A field-dependent activation energy analysis of TDDB lifetimes demonstrates that there are multiple TDDB degradation mechanisms for a Cu/SiOC structure and that the dominant TDDB degradation mechanism is dependent on the electric field. Under higher electric fields, the SiCN film used as a Cu barrier dielectric (BD) is the main cause of the TDDB failure. As the electric field decreases, the degradation of the inter-level dielectric (ILD) or ILD/BD interface has an impact on TDDB failure. Furthermore, it was found that the field-dependency of Ea reflects the dominant TDDB degradation mechanism and is an important factor in determining a TDDB degradation model that can predict an accurate TDDB lifetime.
{"title":"Electric-field and temperature dependencies of TDDB degradation in Cu/Low-K damascene structures","authors":"N. Suzumura, S. Yamamoto, D. Kodama, Hidetoshi Miyazaki, M. Ogasawara, J. Komori, E. Murakami","doi":"10.1109/RELPHY.2008.4558875","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558875","url":null,"abstract":"The electric field and temperature dependencies of time-dependent dielectric breakdown (TDDB) degradation in Cu/low-k damascene structures are investigated using Cu/SiOC and Cu/SiCN damascene structures. A field-dependent activation energy analysis of TDDB lifetimes demonstrates that there are multiple TDDB degradation mechanisms for a Cu/SiOC structure and that the dominant TDDB degradation mechanism is dependent on the electric field. Under higher electric fields, the SiCN film used as a Cu barrier dielectric (BD) is the main cause of the TDDB failure. As the electric field decreases, the degradation of the inter-level dielectric (ILD) or ILD/BD interface has an impact on TDDB failure. Furthermore, it was found that the field-dependency of Ea reflects the dominant TDDB degradation mechanism and is an important factor in determining a TDDB degradation model that can predict an accurate TDDB lifetime.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558972
N. Rahim, D. Misra
In this paper negative bias temperature instability (NBTI) characteristics of Al/HfO2/Ge MOS gate stack with nitrided Ge surface was compared with the non-nitrided Ge surface at high temperatures (125degC). Results show that nitridation creates additional bulk traps even though it shows initial improvements. The authors, therefore, noticed that nitrided Ge has higher DeltaVFB shift and stress induced leakage current than non-nitrided samples. NBTI degradation of nitrided germanium surface is also consistent with literature regarding NBTI on nitrided Si devices. Optimization on nitrogen content and nitridation procedure may improve sensitivity to NBTI.
{"title":"NBTI behavior of Ge/HFO2/Al gate stacks","authors":"N. Rahim, D. Misra","doi":"10.1109/RELPHY.2008.4558972","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558972","url":null,"abstract":"In this paper negative bias temperature instability (NBTI) characteristics of Al/HfO2/Ge MOS gate stack with nitrided Ge surface was compared with the non-nitrided Ge surface at high temperatures (125degC). Results show that nitridation creates additional bulk traps even though it shows initial improvements. The authors, therefore, noticed that nitrided Ge has higher DeltaVFB shift and stress induced leakage current than non-nitrided samples. NBTI degradation of nitrided germanium surface is also consistent with literature regarding NBTI on nitrided Si devices. Optimization on nitrogen content and nitridation procedure may improve sensitivity to NBTI.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116361791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558961
M. Verchiani, E. Bouyssou, F. Cantin, C. Anceau, P. Ranson
This work focuses on ESD HBM robustness of metal insulator metal TaON capacitors. An electrothermal model including a complete leakage current description and a thermal RC network is proposed to explain the ESD experimental results. The leakage current description is based on a Poole-Frenkel mechanism combined with a TDDB theory.
{"title":"Electrothermal model for MIM TaON capacitors during ESD HBM pulses","authors":"M. Verchiani, E. Bouyssou, F. Cantin, C. Anceau, P. Ranson","doi":"10.1109/RELPHY.2008.4558961","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558961","url":null,"abstract":"This work focuses on ESD HBM robustness of metal insulator metal TaON capacitors. An electrothermal model including a complete leakage current description and a thermal RC network is proposed to explain the ESD experimental results. The leakage current description is based on a Poole-Frenkel mechanism combined with a TDDB theory.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123413251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558995
Y. Tsuji, M. Terai, S. Fujieda, K. Ando
We found a new-mode degradation of program-disturb immunity in split-gate SONOS memory with 90-nm technology node. The degradation proved to be caused by hot holes created during erase operation: they can reach word gate (WG) oxide over memory gate (MG). The captured holes within the WG oxide reduce effective inhibit-field that is applied to the WG of non-selected cells during program operation, thereby degrading program-disturb immunity. Hole-trapping defects in the WG oxide seem to be induced in cell fabrication processes, especially in processes using plasma excitation, not by program/erase (P/E) cycling. The degradation was suppressed by implementing a proper gate protection diode.
{"title":"New degradation mode of program disturb immunity of sub 90-nm node split-gate SONOS memory","authors":"Y. Tsuji, M. Terai, S. Fujieda, K. Ando","doi":"10.1109/RELPHY.2008.4558995","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558995","url":null,"abstract":"We found a new-mode degradation of program-disturb immunity in split-gate SONOS memory with 90-nm technology node. The degradation proved to be caused by hot holes created during erase operation: they can reach word gate (WG) oxide over memory gate (MG). The captured holes within the WG oxide reduce effective inhibit-field that is applied to the WG of non-selected cells during program operation, thereby degrading program-disturb immunity. Hole-trapping defects in the WG oxide seem to be induced in cell fabrication processes, especially in processes using plasma excitation, not by program/erase (P/E) cycling. The degradation was suppressed by implementing a proper gate protection diode.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122866410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558996
Seokhan Park, Bonggu Sung, H. Jung, Junhee Lim, Sang-Woo Lee, Jooyoung Lee, Won-suk Yang, Kyungseok Oh, Taeyoung Chung, Kinam Kim
One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.
{"title":"A novel method to analyze and design a NWL scheme DRAM","authors":"Seokhan Park, Bonggu Sung, H. Jung, Junhee Lim, Sang-Woo Lee, Jooyoung Lee, Won-suk Yang, Kyungseok Oh, Taeyoung Chung, Kinam Kim","doi":"10.1109/RELPHY.2008.4558996","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558996","url":null,"abstract":"One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor \"on\" current and to maintain \"off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121067911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558985
V. Verriere, C. Guedj, V. Arnal, A. Sylvestre
The low field conduction mechanism in advanced Cu/ULK interconnects is consistent with 3D phonon-assisted hopping conduction in exponential band-tails. From these measurements, a defectivity parameter proportional to the density of defects near Fermi level is deduced. In addition, the relative fraction of interface versus bulk defect states may be obtained using measurements for several dielectric thicknesses. This parameter may be obtained at nominal operating conditions, it is therefore a good parameter for realistic reliability studies of advanced interconnects.
{"title":"Dielectric conduction mechanisms of ULK/CU interconnects: Low field conduction mechanism and determination of defect density","authors":"V. Verriere, C. Guedj, V. Arnal, A. Sylvestre","doi":"10.1109/RELPHY.2008.4558985","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558985","url":null,"abstract":"The low field conduction mechanism in advanced Cu/ULK interconnects is consistent with 3D phonon-assisted hopping conduction in exponential band-tails. From these measurements, a defectivity parameter proportional to the density of defects near Fermi level is deduced. In addition, the relative fraction of interface versus bulk defect states may be obtained using measurements for several dielectric thicknesses. This parameter may be obtained at nominal operating conditions, it is therefore a good parameter for realistic reliability studies of advanced interconnects.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121513709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558884
G. Gasiot, Philippe Roche, P. Stmicroelectronics
This paper presents alpha and neutron experimental results on 130 nm SRAMs processed in SOI and bulk technologies. Experiments were analyzed for multiple cells upset (MCU) occurrence. MCU percentages and rates were recorded as a function of different experimental parameters (supply voltage, test pattern, etc.). This work sheds light on the different mechanisms involved in MCU occurrence between SOI and bulk technologies.
{"title":"Comparison of multiple cell upset response of BULK and SOI 130NM technologies in the terrestrial environment","authors":"G. Gasiot, Philippe Roche, P. Stmicroelectronics","doi":"10.1109/RELPHY.2008.4558884","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558884","url":null,"abstract":"This paper presents alpha and neutron experimental results on 130 nm SRAMs processed in SOI and bulk technologies. Experiments were analyzed for multiple cells upset (MCU) occurrence. MCU percentages and rates were recorded as a function of different experimental parameters (supply voltage, test pattern, etc.). This work sheds light on the different mechanisms involved in MCU occurrence between SOI and bulk technologies.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122929949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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