Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558903
W. Abadeer, R. Rassel, J.B. Johnson
Junction varactors form key passive components for RF and analog application where capacitance could be tuned by a control voltage. This paper details and models a reliability degradation mechanism due to electron trapping at the side of shallow trench isolation (STI) of the varactor, leading to systematic capacitance degradation as function of time and stress conditions. A key dimension which controls this mechanism is the anode width or spacing between STI, where a minimum value should be defined to meet reliability targets.
{"title":"A capacitance reliability degradation mechanism in Hyper-abrupt junction varactors","authors":"W. Abadeer, R. Rassel, J.B. Johnson","doi":"10.1109/RELPHY.2008.4558903","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558903","url":null,"abstract":"Junction varactors form key passive components for RF and analog application where capacitance could be tuned by a control voltage. This paper details and models a reliability degradation mechanism due to electron trapping at the side of shallow trench isolation (STI) of the varactor, leading to systematic capacitance degradation as function of time and stress conditions. A key dimension which controls this mechanism is the anode width or spacing between STI, where a minimum value should be defined to meet reliability targets.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130760998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558978
J. Ryan, P. Lenahan
Recent studies have demonstrated that deep level defects very near the Si/dielectric boundary are important reliability problems in HfO2 based devices. In this study, we provide a partial identification of the chemical and structural nature of an electrically active center which is present in the interfacial layer (IL) of HfO2 based devices. The defect almost certainly involves an oxygen deficient silicon probably weakly coupled to a nearby hafnium atom.
{"title":"Interfacial layer defects and instabilities in HfO2 MOS structures","authors":"J. Ryan, P. Lenahan","doi":"10.1109/RELPHY.2008.4558978","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558978","url":null,"abstract":"Recent studies have demonstrated that deep level defects very near the Si/dielectric boundary are important reliability problems in HfO2 based devices. In this study, we provide a partial identification of the chemical and structural nature of an electrically active center which is present in the interfacial layer (IL) of HfO2 based devices. The defect almost certainly involves an oxygen deficient silicon probably weakly coupled to a nearby hafnium atom.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128137071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559007
K. Min, C. Kang, Ooksang Yoo, B. Park, Sung Woo Kim, C. Young, D. Heh, G. Bersuker, B. Lee, G. Yeom
Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transconductance and gate leakage were used to evaluate PID. BTI and dielectric breakdown were measured to study the PID effect. For both nMOSFETs and pMOSFETs, the transconductance was degraded for the different antenna structures. It was found that, even below 0.9 nm of EOT range, the plasma charging damage was observed for various device parameters. This plasma damage can deteriorate the reliability of sub 32 nm metal gate/high-k dielectric CMOSFETs.
{"title":"Plasma induced damage of aggressively scaled gate dielectric (EOT ≪ 1.0nm) in metal gate/high-k dielectric CMOSFETs","authors":"K. Min, C. Kang, Ooksang Yoo, B. Park, Sung Woo Kim, C. Young, D. Heh, G. Bersuker, B. Lee, G. Yeom","doi":"10.1109/RELPHY.2008.4559007","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559007","url":null,"abstract":"Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transconductance and gate leakage were used to evaluate PID. BTI and dielectric breakdown were measured to study the PID effect. For both nMOSFETs and pMOSFETs, the transconductance was degraded for the different antenna structures. It was found that, even below 0.9 nm of EOT range, the plasma charging damage was observed for various device parameters. This plasma damage can deteriorate the reliability of sub 32 nm metal gate/high-k dielectric CMOSFETs.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133401353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558922
M. Meneghini, G. Meneghesso, N. Trivellin, L. Trevisanello, K. Orita, M. Yuri, E. Zanoni
This paper describes an analysis of the reliability of GaN-based laser diodes, submitted to constant current, constant optical power and high temperature stress. We demonstrate that constant current and constant optical power stress induce the increase of the threshold current of the devices, that varies according to the square-root of time. The threshold current increase is found to be strongly correlated to the decrease of the sub-threshold emission of the devices, thus suggesting that stress determines the increase of the non-radiative recombination paths in the active layer. Degradation rate is found to depend on stress temperature and on current level, while it does not significantly depend on the optical field in the cavity. The evidences presented within this work support previous literature results, that attribute devices degradation to the diffusion of impurity species towards the active layer, with subsequent increase of the non-radiative recombination rate. The identified degradation process is shown to be electro-thermally activated.
{"title":"Electro-thermally activated degradation of blu-ray gan-based laser diodes","authors":"M. Meneghini, G. Meneghesso, N. Trivellin, L. Trevisanello, K. Orita, M. Yuri, E. Zanoni","doi":"10.1109/RELPHY.2008.4558922","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558922","url":null,"abstract":"This paper describes an analysis of the reliability of GaN-based laser diodes, submitted to constant current, constant optical power and high temperature stress. We demonstrate that constant current and constant optical power stress induce the increase of the threshold current of the devices, that varies according to the square-root of time. The threshold current increase is found to be strongly correlated to the decrease of the sub-threshold emission of the devices, thus suggesting that stress determines the increase of the non-radiative recombination paths in the active layer. Degradation rate is found to depend on stress temperature and on current level, while it does not significantly depend on the optical field in the cavity. The evidences presented within this work support previous literature results, that attribute devices degradation to the diffusion of impurity species towards the active layer, with subsequent increase of the non-radiative recombination rate. The identified degradation process is shown to be electro-thermally activated.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559008
N. Liu, A. Haggag, J. Peschke, M. Moosa, C. Weintraub, H. Lazar, G. Campbell, A. Srivastava, J. Liu, J. Porter, K. Picone, J. Parrish, J. Jiang
In this work, voltage ramp dielectric breakdown (VRDB), time dependent dielectric breakdown, (TDDB) and bias temperature instability (BTI) were conducted to evaluate the impacts of process induced interfacial defects on GOI. It is found that process induced defects near the gate oxide edges by poor adhesion of photo resist resulted in severe effective thinning; and defects near oxide interfaces by various process steps led to the degradation of voltage acceleration factor (VAF), which is likely related to nitrogen enhanced anode hydrogen release (AHR).
{"title":"Impacts of process induced interfacial defects on gate oxide integrity","authors":"N. Liu, A. Haggag, J. Peschke, M. Moosa, C. Weintraub, H. Lazar, G. Campbell, A. Srivastava, J. Liu, J. Porter, K. Picone, J. Parrish, J. Jiang","doi":"10.1109/RELPHY.2008.4559008","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559008","url":null,"abstract":"In this work, voltage ramp dielectric breakdown (VRDB), time dependent dielectric breakdown, (TDDB) and bias temperature instability (BTI) were conducted to evaluate the impacts of process induced interfacial defects on GOI. It is found that process induced defects near the gate oxide edges by poor adhesion of photo resist resulted in severe effective thinning; and defects near oxide interfaces by various process steps led to the degradation of voltage acceleration factor (VAF), which is likely related to nitrogen enhanced anode hydrogen release (AHR).","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116122440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558964
D. Marreiro, S. Shastri, M. Liu, T. Keena, S. Khan, A. Salih, S. Etter, G. Grivna, J. Parsey, R. Ashton, S. Loo, R. Jones, L. Robinson, B. Buhrman, R. Hurley
A novel protection device providing ultra-low line capacitance and improved ESD (J. E. Vinson et al., 2003) and surge capability is presented. Applications include stand-alone protection arrays and integrated protection in baseband- or RF-filters. A proprietary epitaxial layer and isolation capability enable high levels of surge power handling capability, while keeping line capacitance low and reducing device footprint. The response of the device to ESD and surge stresses is investigated at wafer- and package-level. Process condition variations and derived structures are studied, along with a consideration of issues related to the measurement of capacitance, ESD and surge capability.
提出了一种新颖的保护装置，提供超低的线路电容和改进的ESD (J. E. Vinson等，2003)和浪涌能力。应用包括基带或射频滤波器中的独立保护阵列和集成保护。专有的外延层和隔离功能可实现高水平的浪涌功率处理能力，同时保持低线路电容并减少器件占地面积。在晶圆级和封装级研究了器件对ESD和浪涌应力的响应。研究了工艺条件变化及其衍生结构，并考虑了与电容、ESD和浪涌能力测量相关的问题。
{"title":"Multi-channel, high-density, ultra-low capacitance arrays for ESD and surge protection","authors":"D. Marreiro, S. Shastri, M. Liu, T. Keena, S. Khan, A. Salih, S. Etter, G. Grivna, J. Parsey, R. Ashton, S. Loo, R. Jones, L. Robinson, B. Buhrman, R. Hurley","doi":"10.1109/RELPHY.2008.4558964","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558964","url":null,"abstract":"A novel protection device providing ultra-low line capacitance and improved ESD (J. E. Vinson et al., 2003) and surge capability is presented. Applications include stand-alone protection arrays and integrated protection in baseband- or RF-filters. A proprietary epitaxial layer and isolation capability enable high levels of surge power handling capability, while keeping line capacitance low and reducing device footprint. The response of the device to ESD and surge stresses is investigated at wafer- and package-level. Process condition variations and derived structures are studied, along with a consideration of issues related to the measurement of capacitance, ESD and surge capability.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558943
N. Tega, H. Miki, Masanao Yamaoka, Hitoshi Kume, T. Mine, Takeshi Ishida, Y. Mori, Renichi Yamada, K. Torii
The impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time. To estimate the impact on SRAM, we statistically analyzed a threshold voltage fluctuation (DeltaVth) of n-and p-MOSFETs. It is revealed that DeltaVth of the p-MOSFET is larger than that of the n-MOSFET. This difference can be explained by considering the followings: (i) number- and mobility-fluctuation models of RTN (ii) the difference in the capture cross section between electron and hole. In addition, based on these results, SRAM margin enclosed by read / write Vth curves with or without RTN was simulated. We consequently found that Vth margin comes close to Vth window of the SRAM by considering the effect of RTN on DeltaVth, even at hp 65. Moreover, DeltaVth due to RTN of the p-MOSFET is comparable with DeltaVth due to the random dopant fluctuation (RDF) at hp 45 because DeltaVth due to the RDF is inversely proportional to square root of the gate area (S), while DeltaVth due to RTN is inversely proportional to S.
{"title":"Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM","authors":"N. Tega, H. Miki, Masanao Yamaoka, Hitoshi Kume, T. Mine, Takeshi Ishida, Y. Mori, Renichi Yamada, K. Torii","doi":"10.1109/RELPHY.2008.4558943","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558943","url":null,"abstract":"The impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time. To estimate the impact on SRAM, we statistically analyzed a threshold voltage fluctuation (DeltaVth) of n-and p-MOSFETs. It is revealed that DeltaVth of the p-MOSFET is larger than that of the n-MOSFET. This difference can be explained by considering the followings: (i) number- and mobility-fluctuation models of RTN (ii) the difference in the capture cross section between electron and hole. In addition, based on these results, SRAM margin enclosed by read / write Vth curves with or without RTN was simulated. We consequently found that Vth margin comes close to Vth window of the SRAM by considering the effect of RTN on DeltaVth, even at hp 65. Moreover, DeltaVth due to RTN of the p-MOSFET is comparable with DeltaVth due to the random dopant fluctuation (RDF) at hp 45 because DeltaVth due to the RDF is inversely proportional to square root of the gate area (S), while DeltaVth due to RTN is inversely proportional to S.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115335967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558998
Ziyuan Liu, T. Saito, T. Matsuda, K. Ando, Shu Ito, M. Wilde, K. Fukutani
We demonstrate that hydrogen (H) atom penetration into the bottom oxide (BTO) of ONO stacks degrades the retention reliability of MONOS memory. We observe that post-nitride (SiN) N2-annealing improves the retention through a suppression of the H atom diffusion in ONO stacks. Nuclear reaction analysis revealed the presence of an ultra thin H-storage layer in the top oxide/SiN interface, which can effectively shield the BTO from H diffusion, and in turn provides H species resistant against energetic electron damage.
{"title":"Hydrogen distribution in oxide-nitride-oxide stacks and correlation with data retention of MONOS memories","authors":"Ziyuan Liu, T. Saito, T. Matsuda, K. Ando, Shu Ito, M. Wilde, K. Fukutani","doi":"10.1109/RELPHY.2008.4558998","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558998","url":null,"abstract":"We demonstrate that hydrogen (H) atom penetration into the bottom oxide (BTO) of ONO stacks degrades the retention reliability of MONOS memory. We observe that post-nitride (SiN) N2-annealing improves the retention through a suppression of the H atom diffusion in ONO stacks. Nuclear reaction analysis revealed the presence of an ultra thin H-storage layer in the top oxide/SiN interface, which can effectively shield the BTO from H diffusion, and in turn provides H species resistant against energetic electron damage.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114877724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558993
Y. Hsiao, H. Lue, M.Y. Lee, Shih-Chieh Huang, T.Y. Chou, Szu-Yu Wang, K. Hsieh, Rich Liu, Chih-Yuan Lu
The high-Vt state data retention of 2bit/cell SONOS using hot-hole erasing method is studied extensively using a 0.13 mum virtual-ground array NOR-type test chip. We design various trap-layer engineering using multi-layer stacks of SiN and SiON in order to change the intra-nitride conduction. However, our results show that the post-cycled retention is insensitive to the trap-layer engineering. Next, we apply the electrical refill method to test the retention, and find that retention can be improved. Hence our results supports the trap assisted charge loss mechanism. Finally, using a novel bit-by-bit tracking technique, we find that the retention behavior of an individual bit has a random but wide distribution, and some tail bits even show abnormal charge gain. This suggests that both electron and hole de-trapping happen during retention.
{"title":"A study of SONOS charge loss mechanism after hot-hole stressing using trap-layer engineering and electrical re-fill methods","authors":"Y. Hsiao, H. Lue, M.Y. Lee, Shih-Chieh Huang, T.Y. Chou, Szu-Yu Wang, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/RELPHY.2008.4558993","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558993","url":null,"abstract":"The high-Vt state data retention of 2bit/cell SONOS using hot-hole erasing method is studied extensively using a 0.13 mum virtual-ground array NOR-type test chip. We design various trap-layer engineering using multi-layer stacks of SiN and SiON in order to change the intra-nitride conduction. However, our results show that the post-cycled retention is insensitive to the trap-layer engineering. Next, we apply the electrical refill method to test the retention, and find that retention can be improved. Hence our results supports the trap assisted charge loss mechanism. Finally, using a novel bit-by-bit tracking technique, we find that the retention behavior of an individual bit has a random but wide distribution, and some tail bits even show abnormal charge gain. This suggests that both electron and hole de-trapping happen during retention.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127071305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558871
X.J. Chen, H. Barnaby, R. Pease, P. Adell
The results of this study showed that when excess hydrogen is introduced to gated bipolar devices in the radiation environment, the buildup of radiation-induced defects in device oxides and their annealing behaviors are dramatically changed due to hydrogen. The different annealing behaviors of oxide charge between hydrogen-rich and -depleted devices suggest that the defects contributing to the enhanced oxide charge may be microscopically different from the conventional trapped charge described in literature.
{"title":"Behavior of radiation-induced defects in bipolar oxides during irradiation and annealing in hydrogen-rich and -depleted ambients","authors":"X.J. Chen, H. Barnaby, R. Pease, P. Adell","doi":"10.1109/RELPHY.2008.4558871","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558871","url":null,"abstract":"The results of this study showed that when excess hydrogen is introduced to gated bipolar devices in the radiation environment, the buildup of radiation-induced defects in device oxides and their annealing behaviors are dramatically changed due to hydrogen. The different annealing behaviors of oxide charge between hydrogen-rich and -depleted devices suggest that the defects contributing to the enhanced oxide charge may be microscopically different from the conventional trapped charge described in literature.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126108367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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