Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559006
M. Gurfinkel, P. Livshits, A. Rozen, Y. Fefer, J. Bernstein, Y. Shapira
On-die measurements of VDD and VSS signals inside a 90 nm technology chip are presented. The results show fluctuations in the VDD and VSS signals, which might constitute an important new reliability concern. These fluctuations also indirectly affect other reliability mechanisms, such as NBTI, HCI and TDDB. Simulations predict aggravation of this phenomenon for future technologies, which may prove to be a show stopper for further scaling.
{"title":"Supply signal fluctuations due to chip power grid resonance — a new reliability concern","authors":"M. Gurfinkel, P. Livshits, A. Rozen, Y. Fefer, J. Bernstein, Y. Shapira","doi":"10.1109/RELPHY.2008.4559006","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559006","url":null,"abstract":"On-die measurements of VDD and VSS signals inside a 90 nm technology chip are presented. The results show fluctuations in the VDD and VSS signals, which might constitute an important new reliability concern. These fluctuations also indirectly affect other reliability mechanisms, such as NBTI, HCI and TDDB. Simulations predict aggravation of this phenomenon for future technologies, which may prove to be a show stopper for further scaling.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125922127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558858
B. Kaczer, T. Grasser, P. Roussel, J. Martin-Martinez, R. O'Connor, B. O’Sullivan, G. Groeseneken
The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are discussed in detail for pFET with SiON dielectric subjected to NBTI stress. Based on similarities with dielectric relaxation, a physical picture and an equivalent circuit are proposed.
{"title":"Ubiquitous relaxation in BTI stressing—New evaluation and insights","authors":"B. Kaczer, T. Grasser, P. Roussel, J. Martin-Martinez, R. O'Connor, B. O’Sullivan, G. Groeseneken","doi":"10.1109/RELPHY.2008.4558858","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558858","url":null,"abstract":"The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are discussed in detail for pFET with SiON dielectric subjected to NBTI stress. Based on similarities with dielectric relaxation, a physical picture and an equivalent circuit are proposed.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121688154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558883
Takuya Nakauchi, Nobukazu Mikami, Akira Oyama, H. Kobayashi, Hiroki Usui, Jun Kase
We investigated the effect of back bias (VBB) on neutron-induced multi-cell upset (MCU) in 65 nm low stand-by power SRAM. MCUs containing characteristic even number upsets were observed, and they were strongly related to the memory cell array layout. We concluded that most MCUs were induced by activation of parasitic lateral npn-bipolar transistors. We also found that MCU could be drastically reduced by supplying VBB in the p-wells. The SER of MCU was reduced to 1/10 by supplying VBB = -2.0 V in the p-wells without any modification of error checking and correction (ECC) circuits.
{"title":"A novel technique for mitigating neutron-induced multi -cell upset by means of back bias","authors":"Takuya Nakauchi, Nobukazu Mikami, Akira Oyama, H. Kobayashi, Hiroki Usui, Jun Kase","doi":"10.1109/RELPHY.2008.4558883","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558883","url":null,"abstract":"We investigated the effect of back bias (VBB) on neutron-induced multi-cell upset (MCU) in 65 nm low stand-by power SRAM. MCUs containing characteristic even number upsets were observed, and they were strongly related to the memory cell array layout. We concluded that most MCUs were induced by activation of parasitic lateral npn-bipolar transistors. We also found that MCU could be drastically reduced by supplying VBB in the p-wells. The SER of MCU was reduced to 1/10 by supplying VBB = -2.0 V in the p-wells without any modification of error checking and correction (ECC) circuits.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124680457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558911
S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, J. Wiedemer
In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.
{"title":"BTI reliability of 45 nm high-K + metal-gate process technology","authors":"S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, J. Wiedemer","doi":"10.1109/RELPHY.2008.4558911","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558911","url":null,"abstract":"In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"138 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128782803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558915
C. Hau-Riege, R. Klein
We have conducted electromigration studies of Cu interconnects with wide-to-narrow transitions and observed bimodal failure distributions. The early failure mode corresponds to a fatal void at the width transition site while the late failure mode corresponds to a fatal void at the cathode. Also, we observed that as the distance between the cathode and transition decreases, the frequency of the early mode increases while the median time to failure of this mode decreases. Interestingly, we do not assert that the width transition site is as a site of flux divergence. Since a common test current is applied to the entire structure, the number of atoms entering and leaving the transition site should be constant, which was confirmed by simulation. Instead, we explain the experimental observations by different rates of void growth and motion, which are determined by current density. Because there is a much faster growth rate and motion in the narrow region than the wide region, voids that form in the narrow region coalesce at the transition thereby leading to early fails, and voids that form in the wide region lead to late (standard) cathode fails. Width transitions of various types and geometries are relatively common in product designs, therefore this mechanism should be included as part of the chip-level electromigration risk assessment.
{"title":"The effect of a width transition on the electromigration reliability of Cu interconnects","authors":"C. Hau-Riege, R. Klein","doi":"10.1109/RELPHY.2008.4558915","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558915","url":null,"abstract":"We have conducted electromigration studies of Cu interconnects with wide-to-narrow transitions and observed bimodal failure distributions. The early failure mode corresponds to a fatal void at the width transition site while the late failure mode corresponds to a fatal void at the cathode. Also, we observed that as the distance between the cathode and transition decreases, the frequency of the early mode increases while the median time to failure of this mode decreases. Interestingly, we do not assert that the width transition site is as a site of flux divergence. Since a common test current is applied to the entire structure, the number of atoms entering and leaving the transition site should be constant, which was confirmed by simulation. Instead, we explain the experimental observations by different rates of void growth and motion, which are determined by current density. Because there is a much faster growth rate and motion in the narrow region than the wide region, voids that form in the narrow region coalesce at the transition thereby leading to early fails, and voids that form in the wide region lead to late (standard) cathode fails. Width transitions of various types and geometries are relatively common in product designs, therefore this mechanism should be included as part of the chip-level electromigration risk assessment.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"6 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129719699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558987
H. Matsuyama, T. Suzuki, H. Ehara, K. Yanai, T. Kouno, S. Otsuka, N. Misawa, T. Nakamura, Y. Mizushima, M. Shiozu, M. Miyajima, K. Shono
Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.
{"title":"Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern","authors":"H. Matsuyama, T. Suzuki, H. Ehara, K. Yanai, T. Kouno, S. Otsuka, N. Misawa, T. Nakamura, Y. Mizushima, M. Shiozu, M. Miyajima, K. Shono","doi":"10.1109/RELPHY.2008.4558987","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558987","url":null,"abstract":"Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126430619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558949
J. Chen, T. Sekiguchi, N. Fukata, M. Takase, T. Chikyow, K. Yamabe, R. Hasumuma, M. Sato, Y. Nara, K. Yamada
Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. Carrier separated EBIC measurement has found that in non-stressed samples, hole conduction in pMOS is significantly enhanced by trap-assisted tunneling, while electron conduction in nMOS is independent of traps. The transport mechanisms of electron and holes in non-stressed high-k MOS capacitors were clarified. After stressing, positive charged traps are induced in nMOS and enhance electron conduction.
{"title":"Characterization of leakage behaviors of high-k gate stacks by electron-beam-induced current","authors":"J. Chen, T. Sekiguchi, N. Fukata, M. Takase, T. Chikyow, K. Yamabe, R. Hasumuma, M. Sato, Y. Nara, K. Yamada","doi":"10.1109/RELPHY.2008.4558949","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558949","url":null,"abstract":"Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. Carrier separated EBIC measurement has found that in non-stressed samples, hole conduction in pMOS is significantly enhanced by trap-assisted tunneling, while electron conduction in nMOS is independent of traps. The transport mechanisms of electron and holes in non-stressed high-k MOS capacitors were clarified. After stressing, positive charged traps are induced in nMOS and enhance electron conduction.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"422 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127601138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558956
Hsiang Chen, J. Lai, P. Preech, Guann-Pyng Li
Hot hole trapping was mechanism was reported for GaN HEMTs from observations of electroluminescence changes and threshold voltage shifts. Passivation effect was studied through EL on the surface traps or surface states and proved to be effective in real-time monitoring of HEMT operation.Hole trapping leading to an increase in the drain to source current, and a decrease in the threshold voltage have also been shown.
{"title":"Effects of hot hole trapping in GaN HEMTs","authors":"Hsiang Chen, J. Lai, P. Preech, Guann-Pyng Li","doi":"10.1109/RELPHY.2008.4558956","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558956","url":null,"abstract":"Hot hole trapping was mechanism was reported for GaN HEMTs from observations of electroluminescence changes and threshold voltage shifts. Passivation effect was studied through EL on the surface traps or surface states and proved to be effective in real-time monitoring of HEMT operation.Hole trapping leading to an increase in the drain to source current, and a decrease in the threshold voltage have also been shown.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122948061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558930
O. Amusan, L. Massengill, M. Baze, Bharat L. Bhuva, A. Witulski, J. D. Black, A. Balasubramanian, M. C. casey, Deborah Black, J. Ahlbin, Robert A. Reed, M. W. McCurdy
Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.
{"title":"Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process","authors":"O. Amusan, L. Massengill, M. Baze, Bharat L. Bhuva, A. Witulski, J. D. Black, A. Balasubramanian, M. C. casey, Deborah Black, J. Ahlbin, Robert A. Reed, M. W. McCurdy","doi":"10.1109/RELPHY.2008.4558930","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558930","url":null,"abstract":"Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121504665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558983
O. Aubel, S. Thierbach, R. Seidel, B. Freudenberg, M. Meyer, F. Feustel, J. Poppe, M. Nopper, A. Preusse, C. Zistl, K. Weide-Zaage
Reliability of copper interconnect systems is very sensitive to the maximum current used in the product. In this paper we present the results of advanced process improvements leading to very reliable full-build interconnect systems ready for high volume production. Besides the electromigration investigation, we studied stress migration performance as well as BTS and leakage measurements. We found behavior changes in almost all reliability tests suggesting differences in physical behavior, while exhibiting very strong lifetime performance.
{"title":"Comprehensive reliability analysis of CoWP Metal Cap unit processes for high volume production in sub-μm dimensions","authors":"O. Aubel, S. Thierbach, R. Seidel, B. Freudenberg, M. Meyer, F. Feustel, J. Poppe, M. Nopper, A. Preusse, C. Zistl, K. Weide-Zaage","doi":"10.1109/RELPHY.2008.4558983","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558983","url":null,"abstract":"Reliability of copper interconnect systems is very sensitive to the maximum current used in the product. In this paper we present the results of advanced process improvements leading to very reliable full-build interconnect systems ready for high volume production. Besides the electromigration investigation, we studied stress migration performance as well as BTS and leakage measurements. We found behavior changes in almost all reliability tests suggesting differences in physical behavior, while exhibiting very strong lifetime performance.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115560140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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