Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558879
A. Breeze
Thin-film photovoltaic modules made of materials such as copper indium gallium diselenide (CIGS), cadmium telluride (CdTe) and amorphous silicon (a-Si) offer the opportunity to reduce solar energy manufacturing costs through the minimization of material usage, as compared to more longstanding PV systems such as crystalline silicon. The market share for thin-film PV is still low but recently has begun to grow rapidly in the United States [1]. This paper gives an introduction to solar cell characterization and solar cells in the first two categories, namely CIGS and CdTe.
{"title":"Next generation thin-film solar cells","authors":"A. Breeze","doi":"10.1109/RELPHY.2008.4558879","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558879","url":null,"abstract":"Thin-film photovoltaic modules made of materials such as copper indium gallium diselenide (CIGS), cadmium telluride (CdTe) and amorphous silicon (a-Si) offer the opportunity to reduce solar energy manufacturing costs through the minimization of material usage, as compared to more longstanding PV systems such as crystalline silicon. The market share for thin-film PV is still low but recently has begun to grow rapidly in the United States [1]. This paper gives an introduction to solar cell characterization and solar cells in the first two categories, namely CIGS and CdTe.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121882011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558861
Chia-Han Yang, Y. Kuo, Rui Wan, Chen-Han Lin, W. Kuo
Semiconducting and metallic nanocrystals have been embedded in high-k dielectrics for nonvolatile memories for advantages of low leakage currents, large charge storage capacities, and long retention times. However, there are few studies on the reliability issues, such as the breakdown mechanism and relaxation current decay rate. In this paper, authors investigated the reliability of four different kinds of nanocrystals, i.e., ruthenium, indium tin oxide, silicon, and zinc oxide, embedded in the Zr-doped HfO2 high-k thin film. Although all nanocrystals embedded samples have charge storage capacity about one order of magnitude higher than that without nanocrystals embedded samples, the formerpsilas relaxation currents are higher and decay times are longer than those of the latter. When the relaxation currents were fitted to the Curie-von Schweidler law, the formerpsilas n values were between 0.4 and 0.65, which are different from the latterpsilas n values of near 1. When the naocrystals embedded sample was broken under a high bias gate voltage stress, the high-k part failed while the nanocrystals remained unattacked. This is demonstrated by the lack of polarity change of the relaxation current. The time to breakdown of the high-k film was also extended due to the inclusion of nanocrystals in the film. Therefore, the embedded nanocrystals play an important role for the reliability of this kind of nonvolatile memory device.
{"title":"Failure analysis of nanocrystals embedded high-k dielectrics for nonvolatile memories","authors":"Chia-Han Yang, Y. Kuo, Rui Wan, Chen-Han Lin, W. Kuo","doi":"10.1109/RELPHY.2008.4558861","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558861","url":null,"abstract":"Semiconducting and metallic nanocrystals have been embedded in high-k dielectrics for nonvolatile memories for advantages of low leakage currents, large charge storage capacities, and long retention times. However, there are few studies on the reliability issues, such as the breakdown mechanism and relaxation current decay rate. In this paper, authors investigated the reliability of four different kinds of nanocrystals, i.e., ruthenium, indium tin oxide, silicon, and zinc oxide, embedded in the Zr-doped HfO2 high-k thin film. Although all nanocrystals embedded samples have charge storage capacity about one order of magnitude higher than that without nanocrystals embedded samples, the formerpsilas relaxation currents are higher and decay times are longer than those of the latter. When the relaxation currents were fitted to the Curie-von Schweidler law, the formerpsilas n values were between 0.4 and 0.65, which are different from the latterpsilas n values of near 1. When the naocrystals embedded sample was broken under a high bias gate voltage stress, the high-k part failed while the nanocrystals remained unattacked. This is demonstrated by the lack of polarity change of the relaxation current. The time to breakdown of the high-k film was also extended due to the inclusion of nanocrystals in the film. Therefore, the embedded nanocrystals play an important role for the reliability of this kind of nonvolatile memory device.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558917
A. Oates, M. H. Lin
We investigate electromigration void morphologies, associated resistance increases and failure distributions for down-stream electron flow of Cu dual damascene via structures. We show that void formation occurs below the traditionally defined critical current density, and we develop a model to accurately predict via failure distributions as a function of current density.
{"title":"Analysis and modeling of critical current density effects on electromigration failure distributions of Cu dual-damascene vias","authors":"A. Oates, M. H. Lin","doi":"10.1109/RELPHY.2008.4558917","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558917","url":null,"abstract":"We investigate electromigration void morphologies, associated resistance increases and failure distributions for down-stream electron flow of Cu dual damascene via structures. We show that void formation occurs below the traditionally defined critical current density, and we develop a model to accurately predict via failure distributions as a function of current density.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131481447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558920
H. Hamamura, T. Ishida, T. Mine, Y. Okuyama, D. Hisamoto, Y. Shimamoto, S. Kimura, K. Torii
To determine the potential of hafnium oxide (HfO2) film as a charge-trapping layer for flash memories, distributions of electron traps, equivalent oxide thickness (EOT) scalability, and data-retention characteristics are investigated. Electrons are trapped at both top and bottom interfaces of oxide/HfO2 and in the HfO2 bulk. This distinguishes HfO2 from silicon nitride (SiN), where electrons are mainly trapped at the two interfaces. The interface trap densities of electrons are of the order of 1013 cm-2, and that of the HfO2 bulk is of the order of 1018 cm-3, which is one order larger than that of the SiN bulk. The oxygen vacancy is a possible origin of HfO2 bulk traps. From the viewpoint of EOT scaling, HfO2 is superior to SiN as a trapping layer. Moreover, retention characteristics of HfO2 were better than those of SiN.
{"title":"Electron trapping characteristics and scalability of HfO2 as a trapping layer in SONOS-type flash memories","authors":"H. Hamamura, T. Ishida, T. Mine, Y. Okuyama, D. Hisamoto, Y. Shimamoto, S. Kimura, K. Torii","doi":"10.1109/RELPHY.2008.4558920","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558920","url":null,"abstract":"To determine the potential of hafnium oxide (HfO<sub>2</sub>) film as a charge-trapping layer for flash memories, distributions of electron traps, equivalent oxide thickness (EOT) scalability, and data-retention characteristics are investigated. Electrons are trapped at both top and bottom interfaces of oxide/HfO<sub>2</sub> and in the HfO<sub>2</sub> bulk. This distinguishes HfO<sub>2</sub> from silicon nitride (SiN), where electrons are mainly trapped at the two interfaces. The interface trap densities of electrons are of the order of 10<sup>13</sup> cm<sup>-2</sup>, and that of the HfO<sub>2</sub> bulk is of the order of 10<sup>18</sup> cm<sup>-3</sup>, which is one order larger than that of the SiN bulk. The oxygen vacancy is a possible origin of HfO<sub>2</sub> bulk traps. From the viewpoint of EOT scaling, HfO<sub>2</sub> is superior to SiN as a trapping layer. Moreover, retention characteristics of HfO<sub>2</sub> were better than those of SiN.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558971
C. Kendrick, R. Stout, M. Cook
The failure mechanisms for NLDMOS transistors subjected to rectangular power pulses are investigated. The study confirms by measurement and simulation that the transistors survive single power pulses up to an energy that causes snapback at a critical temperature. However, devices can fail due to large thermal-mechanical stress and metal migration when subjected to repetitive power pulses of significantly smaller energy. The failure mechanism is confirmed by physical analysis then a Coffin-Manson metal fatigue model is applied to predict transistor reliability.
{"title":"Reliability of NLDMOS transistors subjected to repetitive power pulses","authors":"C. Kendrick, R. Stout, M. Cook","doi":"10.1109/RELPHY.2008.4558971","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558971","url":null,"abstract":"The failure mechanisms for NLDMOS transistors subjected to rectangular power pulses are investigated. The study confirms by measurement and simulation that the transistors survive single power pulses up to an energy that causes snapback at a critical temperature. However, devices can fail due to large thermal-mechanical stress and metal migration when subjected to repetitive power pulses of significantly smaller energy. The failure mechanism is confirmed by physical analysis then a Coffin-Manson metal fatigue model is applied to predict transistor reliability.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131983840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558874
F. Chen, J. Lloyd, K. Chanda, R. Achanta, O. Bravo, A. Strong, P. McLaughlin, M. Shinosky, S. Sankaran, E. Gebreselasie, A. Stamper, Z. He
The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.
低k TDDB线空间标度的研究对于保证新技术的鲁棒可靠性具有重要意义。虽然之前有报道过线边缘粗糙度(LER)对低k TDDB寿命的间距影响(Chen et al.， 2007;Lloyd等人，2007;Kim et al.， 2007)，一直缺乏一种分析模型，用简单的定量格式将线边缘粗糙度与实验TDDB数据联系起来。本文对低钾SiCOH线LER对低钾TDDB的影响进行了深入的研究，包括实验结果和有限元模拟。发现由侧壁LER凹凸引起的最大电场强度与凹凸曲率有关。然后仔细分析了在相同外加电场下，低k线间距的减小导致TDDB寿命缩短的原因。提出了线边粗糙度对TDDB失效时间缩短影响的简单解析模型。实验结果验证了该模型的正确性。此外，还介绍了一种电量化整体线边缘粗糙度的方法。
{"title":"Line edge roughness and spacing effect on low-k TDDB characteristics","authors":"F. Chen, J. Lloyd, K. Chanda, R. Achanta, O. Bravo, A. Strong, P. McLaughlin, M. Shinosky, S. Sankaran, E. Gebreselasie, A. Stamper, Z. He","doi":"10.1109/RELPHY.2008.4558874","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558874","url":null,"abstract":"The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115084676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559001
Po-Ying Chen, S.L. Chen, M. Tsai, M.H. Jing, T. Lin, W. Yeh
The effects of crystal-originated particles (COPs) on ultra-thin gate oxide for recent ultra large-scale integration (ULSI) devices were studied. Various Czochralski (CZ) silicon wafers were prepared by controlling the pulling speed of silicon ingots to determine the relationships between COPs and the breakdown characteristics of the ultra thin-gate oxide.
{"title":"Effect of crystal-originated particles (COPs) on ULSI process integrity","authors":"Po-Ying Chen, S.L. Chen, M. Tsai, M.H. Jing, T. Lin, W. Yeh","doi":"10.1109/RELPHY.2008.4559001","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559001","url":null,"abstract":"The effects of crystal-originated particles (COPs) on ultra-thin gate oxide for recent ultra large-scale integration (ULSI) devices were studied. Various Czochralski (CZ) silicon wafers were prepared by controlling the pulling speed of silicon ingots to determine the relationships between COPs and the breakdown characteristics of the ultra thin-gate oxide.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128403028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558962
H. Sarbishaei, S.S. Lubana, O. Semenov, M. Sachdev
Silicon controlled rectifiers (SCRs) are used extensively in high frequency applications. To reduce their first breakdown voltage, they are used with different triggering mechanisms. In this paper, a novel ESD protection device is proposed that can reduce the first breakdown voltage of SCR to 3V without any extra triggering devices.
{"title":"Adarlington-based SCR ESD protection device for high-speed applications","authors":"H. Sarbishaei, S.S. Lubana, O. Semenov, M. Sachdev","doi":"10.1109/RELPHY.2008.4558962","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558962","url":null,"abstract":"Silicon controlled rectifiers (SCRs) are used extensively in high frequency applications. To reduce their first breakdown voltage, they are used with different triggering mechanisms. In this paper, a novel ESD protection device is proposed that can reduce the first breakdown voltage of SCR to 3V without any extra triggering devices.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128413648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558902
Kyong-Taek Lee, C. Kang, Ooksang Yoo, D. Chadwin, G. Bersuker, Ho Kyung Park, Jun Myung Lee, H. Hwang, B. Lee, H. Lee, Y. Jeong
Effects of a stressor nitride layer on device performance and reliability are investigated. To decouple intrinsic mechanical stress and process-related effects, device characteristics under mechanical bending stress and stressor layers were compared. The compressive stressor device exhibits improved initial interface quality, although slightly degraded reliability characteristics, due to increased hydrogen passivation of the dielectric/substrate interface. Thereby, the hydrogen passivation in the interface is found to be a primary cause of the difference in reliability characteristics.
{"title":"A comparative study of reliability and performance of strain engineering using CESL stressor and mechanical strain","authors":"Kyong-Taek Lee, C. Kang, Ooksang Yoo, D. Chadwin, G. Bersuker, Ho Kyung Park, Jun Myung Lee, H. Hwang, B. Lee, H. Lee, Y. Jeong","doi":"10.1109/RELPHY.2008.4558902","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558902","url":null,"abstract":"Effects of a stressor nitride layer on device performance and reliability are investigated. To decouple intrinsic mechanical stress and process-related effects, device characteristics under mechanical bending stress and stressor layers were compared. The compressive stressor device exhibits improved initial interface quality, although slightly degraded reliability characteristics, due to increased hydrogen passivation of the dielectric/substrate interface. Thereby, the hydrogen passivation in the interface is found to be a primary cause of the difference in reliability characteristics.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133157134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559018
Jang-Sik Lee, W. Wu, A. Islam, M. Alam, A. Oates
In this study, we propose a systematic method to separate the hole trapping from measured V1 shift, thus giving the ideal interface trap generation behavior without measurement disturbance. Three stages of interface trap generation have been illustrated with the analytical H-H2 NBTI reaction-diffusion model, and the hole trapping has also been verified with its voltage-enhanced and temperature-insensitive properties. Finally, the PMOS device lifetime extrapolation without considering the hole trapping might lead to significant lifetime overestimation.
{"title":"Separation method of hole trapping and interface trap generation and their roles in NBTI reaction-diffusion model","authors":"Jang-Sik Lee, W. Wu, A. Islam, M. Alam, A. Oates","doi":"10.1109/RELPHY.2008.4559018","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559018","url":null,"abstract":"In this study, we propose a systematic method to separate the hole trapping from measured V1 shift, thus giving the ideal interface trap generation behavior without measurement disturbance. Three stages of interface trap generation have been illustrated with the analytical H-H2 NBTI reaction-diffusion model, and the hole trapping has also been verified with its voltage-enhanced and temperature-insensitive properties. Finally, the PMOS device lifetime extrapolation without considering the hole trapping might lead to significant lifetime overestimation.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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