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2008 IEEE International Reliability Physics Symposium最新文献

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Next generation thin-film solar cells 下一代薄膜太阳能电池
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558879
A. Breeze
Thin-film photovoltaic modules made of materials such as copper indium gallium diselenide (CIGS), cadmium telluride (CdTe) and amorphous silicon (a-Si) offer the opportunity to reduce solar energy manufacturing costs through the minimization of material usage, as compared to more longstanding PV systems such as crystalline silicon. The market share for thin-film PV is still low but recently has begun to grow rapidly in the United States [1]. This paper gives an introduction to solar cell characterization and solar cells in the first two categories, namely CIGS and CdTe.
薄膜光伏组件由铜铟镓二硒化(CIGS)、碲化镉(CdTe)和非晶硅(a-Si)等材料制成,与晶体硅等更长期的光伏系统相比,通过最大限度地减少材料使用,提供了降低太阳能制造成本的机会。薄膜光伏的市场份额仍然很低,但最近在美国已经开始快速增长[1]。本文介绍了太阳能电池的特性和太阳能电池的前两类,即CIGS和CdTe。
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引用次数: 20
Failure analysis of nanocrystals embedded high-k dielectrics for nonvolatile memories 非易失性存储器中嵌入高k介电体的纳米晶体失效分析
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558861
Chia-Han Yang, Y. Kuo, Rui Wan, Chen-Han Lin, W. Kuo
Semiconducting and metallic nanocrystals have been embedded in high-k dielectrics for nonvolatile memories for advantages of low leakage currents, large charge storage capacities, and long retention times. However, there are few studies on the reliability issues, such as the breakdown mechanism and relaxation current decay rate. In this paper, authors investigated the reliability of four different kinds of nanocrystals, i.e., ruthenium, indium tin oxide, silicon, and zinc oxide, embedded in the Zr-doped HfO2 high-k thin film. Although all nanocrystals embedded samples have charge storage capacity about one order of magnitude higher than that without nanocrystals embedded samples, the formerpsilas relaxation currents are higher and decay times are longer than those of the latter. When the relaxation currents were fitted to the Curie-von Schweidler law, the formerpsilas n values were between 0.4 and 0.65, which are different from the latterpsilas n values of near 1. When the naocrystals embedded sample was broken under a high bias gate voltage stress, the high-k part failed while the nanocrystals remained unattacked. This is demonstrated by the lack of polarity change of the relaxation current. The time to breakdown of the high-k film was also extended due to the inclusion of nanocrystals in the film. Therefore, the embedded nanocrystals play an important role for the reliability of this kind of nonvolatile memory device.
半导体和金属纳米晶体已被嵌入到高k介电介质中,用于非易失性存储器,具有低泄漏电流、大电荷存储容量和长保持时间的优点。然而,对击穿机理和弛豫电流衰减率等可靠性问题的研究却很少。在本文中,作者研究了四种不同的纳米晶体,即钌,氧化铟锡,硅和氧化锌,嵌入在zr掺杂的HfO2高k薄膜中的可靠性。虽然所有纳米晶包埋样品的电荷存储容量都比没有纳米晶包埋样品高一个数量级,但前者的弛豫电流更大,衰变时间更长。当弛豫电流符合Curie-von Schweidler定律时,前者的n值在0.4 ~ 0.65之间,与后者接近1的n值不同。当纳米晶在高偏置栅极电压应力下被破坏时,高k部分失效,而纳米晶未受攻击。这可以通过松弛电流没有极性变化来证明。由于薄膜中含有纳米晶体,高k薄膜的击穿时间也延长了。因此,内嵌的纳米晶体对这种非易失性存储器件的可靠性起着重要的作用。
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引用次数: 4
Analysis and modeling of critical current density effects on electromigration failure distributions of Cu dual-damascene vias 临界电流密度对铜双damascene过孔电迁移失效分布影响的分析与建模
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558917
A. Oates, M. H. Lin
We investigate electromigration void morphologies, associated resistance increases and failure distributions for down-stream electron flow of Cu dual damascene via structures. We show that void formation occurs below the traditionally defined critical current density, and we develop a model to accurately predict via failure distributions as a function of current density.
我们研究了铜双砷通过结构的电迁移空穴形态、相关的电阻增加和下游电子流的失效分布。我们发现,孔隙形成发生在传统定义的临界电流密度以下,我们开发了一个模型,通过失效分布作为电流密度的函数来准确预测。
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引用次数: 12
Electron trapping characteristics and scalability of HfO2 as a trapping layer in SONOS-type flash memories HfO2在sonos型闪存中作为捕获层的电子捕获特性和可扩展性
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558920
H. Hamamura, T. Ishida, T. Mine, Y. Okuyama, D. Hisamoto, Y. Shimamoto, S. Kimura, K. Torii
To determine the potential of hafnium oxide (HfO2) film as a charge-trapping layer for flash memories, distributions of electron traps, equivalent oxide thickness (EOT) scalability, and data-retention characteristics are investigated. Electrons are trapped at both top and bottom interfaces of oxide/HfO2 and in the HfO2 bulk. This distinguishes HfO2 from silicon nitride (SiN), where electrons are mainly trapped at the two interfaces. The interface trap densities of electrons are of the order of 1013 cm-2, and that of the HfO2 bulk is of the order of 1018 cm-3, which is one order larger than that of the SiN bulk. The oxygen vacancy is a possible origin of HfO2 bulk traps. From the viewpoint of EOT scaling, HfO2 is superior to SiN as a trapping layer. Moreover, retention characteristics of HfO2 were better than those of SiN.
为了确定氧化铪(HfO2)薄膜作为闪存电荷捕获层的潜力,研究了电子陷阱的分布、等效氧化物厚度(EOT)的可扩展性和数据保留特性。电子被捕获在氧化物/HfO2的顶部和底部界面以及HfO2体中。这将HfO2与氮化硅(SiN)区别开来,氮化硅的电子主要被捕获在两个界面上。电子的界面阱密度为1013 cm-2数量级,HfO2体的界面阱密度为1018 cm-3数量级,比SiN体大一个数量级。氧空位可能是HfO2体积圈闭的来源。从EOT标度的角度来看,HfO2作为捕获层优于SiN。HfO2的保留特性优于SiN。
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引用次数: 11
Reliability of NLDMOS transistors subjected to repetitive power pulses 重复功率脉冲作用下NLDMOS晶体管的可靠性
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558971
C. Kendrick, R. Stout, M. Cook
The failure mechanisms for NLDMOS transistors subjected to rectangular power pulses are investigated. The study confirms by measurement and simulation that the transistors survive single power pulses up to an energy that causes snapback at a critical temperature. However, devices can fail due to large thermal-mechanical stress and metal migration when subjected to repetitive power pulses of significantly smaller energy. The failure mechanism is confirmed by physical analysis then a Coffin-Manson metal fatigue model is applied to predict transistor reliability.
研究了矩形功率脉冲作用下NLDMOS晶体管的失效机理。该研究通过测量和模拟证实,晶体管在单个功率脉冲达到临界温度时能够存活下来。然而,当受到明显较小能量的重复功率脉冲时,设备可能由于大的热机械应力和金属迁移而失效。通过物理分析确定了失效机理,并采用Coffin-Manson金属疲劳模型对晶体管的可靠性进行了预测。
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引用次数: 2
Line edge roughness and spacing effect on low-k TDDB characteristics 线边缘粗糙度和间距对低k TDDB特性的影响
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558874
F. Chen, J. Lloyd, K. Chanda, R. Achanta, O. Bravo, A. Strong, P. McLaughlin, M. Shinosky, S. Sankaran, E. Gebreselasie, A. Stamper, Z. He
The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.
低k TDDB线空间标度的研究对于保证新技术的鲁棒可靠性具有重要意义。虽然之前有报道过线边缘粗糙度(LER)对低k TDDB寿命的间距影响(Chen et al., 2007;Lloyd等人,2007;Kim et al., 2007),一直缺乏一种分析模型,用简单的定量格式将线边缘粗糙度与实验TDDB数据联系起来。本文对低钾SiCOH线LER对低钾TDDB的影响进行了深入的研究,包括实验结果和有限元模拟。发现由侧壁LER凹凸引起的最大电场强度与凹凸曲率有关。然后仔细分析了在相同外加电场下,低k线间距的减小导致TDDB寿命缩短的原因。提出了线边粗糙度对TDDB失效时间缩短影响的简单解析模型。实验结果验证了该模型的正确性。此外,还介绍了一种电量化整体线边缘粗糙度的方法。
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引用次数: 51
Effect of crystal-originated particles (COPs) on ULSI process integrity 晶源颗粒(cop)对ULSI工艺完整性的影响
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4559001
Po-Ying Chen, S.L. Chen, M. Tsai, M.H. Jing, T. Lin, W. Yeh
The effects of crystal-originated particles (COPs) on ultra-thin gate oxide for recent ultra large-scale integration (ULSI) devices were studied. Various Czochralski (CZ) silicon wafers were prepared by controlling the pulling speed of silicon ingots to determine the relationships between COPs and the breakdown characteristics of the ultra thin-gate oxide.
研究了晶体源粒子(COPs)对超薄栅极氧化物(ULSI)器件的影响。通过控制硅锭的拉拔速度,制备了多种CZ型硅晶片,确定了COPs与超薄栅氧化物击穿特性的关系。
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引用次数: 0
Adarlington-based SCR ESD protection device for high-speed applications 基于adarlington的SCR ESD保护装置,用于高速应用
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558962
H. Sarbishaei, S.S. Lubana, O. Semenov, M. Sachdev
Silicon controlled rectifiers (SCRs) are used extensively in high frequency applications. To reduce their first breakdown voltage, they are used with different triggering mechanisms. In this paper, a novel ESD protection device is proposed that can reduce the first breakdown voltage of SCR to 3V without any extra triggering devices.
可控硅整流器(SCRs)广泛应用于高频应用。为了降低它们的第一次击穿电压,它们与不同的触发机制一起使用。本文提出了一种新型的ESD保护装置,可以在不增加触发装置的情况下,将可控硅的一次击穿电压降低到3V。
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引用次数: 3
A comparative study of reliability and performance of strain engineering using CESL stressor and mechanical strain 使用CESL应力源和机械应变的应变工程可靠性和性能的比较研究
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4558902
Kyong-Taek Lee, C. Kang, Ooksang Yoo, D. Chadwin, G. Bersuker, Ho Kyung Park, Jun Myung Lee, H. Hwang, B. Lee, H. Lee, Y. Jeong
Effects of a stressor nitride layer on device performance and reliability are investigated. To decouple intrinsic mechanical stress and process-related effects, device characteristics under mechanical bending stress and stressor layers were compared. The compressive stressor device exhibits improved initial interface quality, although slightly degraded reliability characteristics, due to increased hydrogen passivation of the dielectric/substrate interface. Thereby, the hydrogen passivation in the interface is found to be a primary cause of the difference in reliability characteristics.
研究了应力源氮化层对器件性能和可靠性的影响。为了解耦固有机械应力和工艺相关影响,比较了机械弯曲应力和应力源层下的器件特性。由于介质/衬底界面的氢钝化程度增加,压缩应力源器件的初始界面质量得到改善,但可靠性特性略有下降。因此,发现界面中的氢钝化是可靠性特性差异的主要原因。
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引用次数: 10
Separation method of hole trapping and interface trap generation and their roles in NBTI reaction-diffusion model NBTI反应扩散模型中空穴捕获和界面捕获的分离方法及其作用
Pub Date : 2008-07-09 DOI: 10.1109/RELPHY.2008.4559018
Jang-Sik Lee, W. Wu, A. Islam, M. Alam, A. Oates
In this study, we propose a systematic method to separate the hole trapping from measured V1 shift, thus giving the ideal interface trap generation behavior without measurement disturbance. Three stages of interface trap generation have been illustrated with the analytical H-H2 NBTI reaction-diffusion model, and the hole trapping has also been verified with its voltage-enhanced and temperature-insensitive properties. Finally, the PMOS device lifetime extrapolation without considering the hole trapping might lead to significant lifetime overestimation.
在这项研究中,我们提出了一种系统的方法来分离空穴捕获和测量到的V1位移,从而在没有测量干扰的情况下给出理想的界面捕获行为。用解析的H-H2 NBTI反应-扩散模型说明了界面陷阱产生的三个阶段,并证实了空穴陷阱具有电压增强和温度不敏感的特性。最后,不考虑空穴捕获的PMOS器件寿命外推可能导致显著的寿命高估。
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引用次数: 46
期刊
2008 IEEE International Reliability Physics Symposium
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