Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558984
K. Wang, C. Wilson, A. Cuthbertson, R. Herberholz, H. Coulson, A. O'Neill, A. Horsfall
In this paper we investigate the reliability of Cu contacts with both Ta and W based barriers using thermal and electrical stressing. The Ta based barrier showed superior resistance to electrical stressing, with a time-to-failure approaching that of the W-plug reference and a via like failure mode. However early fails reduce the t50 due to high process induced stress imposed by the pre-metal dielectric. These initial results suggest, with further process optimization to reduce thermal stress and improve barrier uniformity, Cu contacts with Ta based barriers can be as reliable as vias in higher metals layers and the traditional W contacts.
{"title":"Influence of barriers on the reliability of dual damascene copper contacts","authors":"K. Wang, C. Wilson, A. Cuthbertson, R. Herberholz, H. Coulson, A. O'Neill, A. Horsfall","doi":"10.1109/RELPHY.2008.4558984","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558984","url":null,"abstract":"In this paper we investigate the reliability of Cu contacts with both Ta and W based barriers using thermal and electrical stressing. The Ta based barrier showed superior resistance to electrical stressing, with a time-to-failure approaching that of the W-plug reference and a via like failure mode. However early fails reduce the t50 due to high process induced stress imposed by the pre-metal dielectric. These initial results suggest, with further process optimization to reduce thermal stress and improve barrier uniformity, Cu contacts with Ta based barriers can be as reliable as vias in higher metals layers and the traditional W contacts.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115775275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558862
A. Diebold
Advances in process technology enable high volume manufacture of integrated circuits with nano-scale transistor and interconnect technology. This fabrication capability results in the availability of a great range of nano-scale materials and structures such as nano-tubes, thin films, nano-dots, and nanowires. Many of these materials are under consideration as the material for beyond CMOS switches. There are two themes emphasized in this paper. First, materials exhibit new phenomena such as quantum confinement at nano-scale dimensions. Measurements not only observe these phenomena, determination of the dimensions of nanoscale materials requires understanding of these phenomena. Second, simulation and modeling at nano-scale dimensions is critical to both device operation and metrology. This extended abstract reviews the materials characterization and metrology methods necessary for measuring materials properties. This abstract covers several of the many measurement methods necessary for nanoscale characterization and metrology.
{"title":"Survey of characterization and metrology for nanoelectronics","authors":"A. Diebold","doi":"10.1109/RELPHY.2008.4558862","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558862","url":null,"abstract":"Advances in process technology enable high volume manufacture of integrated circuits with nano-scale transistor and interconnect technology. This fabrication capability results in the availability of a great range of nano-scale materials and structures such as nano-tubes, thin films, nano-dots, and nanowires. Many of these materials are under consideration as the material for beyond CMOS switches. There are two themes emphasized in this paper. First, materials exhibit new phenomena such as quantum confinement at nano-scale dimensions. Measurements not only observe these phenomena, determination of the dimensions of nanoscale materials requires understanding of these phenomena. Second, simulation and modeling at nano-scale dimensions is critical to both device operation and metrology. This extended abstract reviews the materials characterization and metrology methods necessary for measuring materials properties. This abstract covers several of the many measurement methods necessary for nanoscale characterization and metrology.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115437896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558951
E. Ng, E. Poh, D. Lam, Z. Xinhua
Resistive contacts and, in particular, resistive gate contacts in multilayer interconnects have been an ongoing challenge for semiconductor industries. The failing mechanisms behind them were difficult to uncover, which made it necessary to initiate deeper research into each issue that we managed to isolate. The traditional approach of using passive voltage contrast (PVC), scanning electron microscope (SEM), or focused ion beam (FIB) to identify resistance gate contacts is getting more difficult, especially for those contacts with resistance that is only marginally higher than normal contacts. In this paper, we discuss a resistive gate contact issue arising from reliability tests. Finding the root cause for the resistive gate contacts is vital to solving reliability and yield losses. Specifically, we focused on the physical failure analysis to characterize and to uncover the abnormal material behind the resistive gate contacts so we could explain the underdetermined failure mechanism. We established a novel approach to electrical characterization using conductive atomic force microscopy (CAFM). Using transmission electron microscope (TEM), we were able to directly observe the details and to identify the chemical composition of the abnormal, subtle resistive material between the contact and the gate. With these findings, we were able to fully understand the root cause of the failure mechanism and to resolve this issue.
{"title":"Failure mechanism study for high resistance gate contact in dram devices for 2008 IRPS","authors":"E. Ng, E. Poh, D. Lam, Z. Xinhua","doi":"10.1109/RELPHY.2008.4558951","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558951","url":null,"abstract":"Resistive contacts and, in particular, resistive gate contacts in multilayer interconnects have been an ongoing challenge for semiconductor industries. The failing mechanisms behind them were difficult to uncover, which made it necessary to initiate deeper research into each issue that we managed to isolate. The traditional approach of using passive voltage contrast (PVC), scanning electron microscope (SEM), or focused ion beam (FIB) to identify resistance gate contacts is getting more difficult, especially for those contacts with resistance that is only marginally higher than normal contacts. In this paper, we discuss a resistive gate contact issue arising from reliability tests. Finding the root cause for the resistive gate contacts is vital to solving reliability and yield losses. Specifically, we focused on the physical failure analysis to characterize and to uncover the abnormal material behind the resistive gate contacts so we could explain the underdetermined failure mechanism. We established a novel approach to electrical characterization using conductive atomic force microscopy (CAFM). Using transmission electron microscope (TEM), we were able to directly observe the details and to identify the chemical composition of the abnormal, subtle resistive material between the contact and the gate. With these findings, we were able to fully understand the root cause of the failure mechanism and to resolve this issue.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130815537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558906
R. O'Connor, L. Pantisano, R. Degraeve, T. Kauerauf, B. Kaczer, P. Roussel, G. Groeseneken
In this work we present a novel trap spectroscopy based on stress induced leakage current measurements for constant voltage stress and substrate hot carrier injection stresses in nMOSFET devices. Peaks in the stress induced leakage current at several gate voltages are attributed specifically to defects in the bulk and at the interface by using the substrate hot electron injection technique to specifically create defects in different spatial locations. Our results show that low energy carriers preferentially creates defects which are deep in the bandgap but close to the interface, while injection into the HfSiON conduction band creates bulk defects approximately aligned with the Si conduction band.
{"title":"SILC defect generation spectroscopy in HfSiON using constant voltage stress and substrate hot electron injection","authors":"R. O'Connor, L. Pantisano, R. Degraeve, T. Kauerauf, B. Kaczer, P. Roussel, G. Groeseneken","doi":"10.1109/RELPHY.2008.4558906","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558906","url":null,"abstract":"In this work we present a novel trap spectroscopy based on stress induced leakage current measurements for constant voltage stress and substrate hot carrier injection stresses in nMOSFET devices. Peaks in the stress induced leakage current at several gate voltages are attributed specifically to defects in the bulk and at the interface by using the substrate hot electron injection technique to specifically create defects in different spatial locations. Our results show that low energy carriers preferentially creates defects which are deep in the bandgap but close to the interface, while injection into the HfSiON conduction band creates bulk defects approximately aligned with the Si conduction band.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128126487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558927
D. Frear, L. Ramanathan, J. Jang, N. Owens
The trend for microelectronic devices has historically been, and will continue to be, towards smaller feature size, faster speeds, more complexity, higher power and lower cost. The motivating force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunication, RF applications are beginning to drive many areas of microelectronics traditionally led by the development of the microprocessor. An increasingly dominant factor in RF microelectronics is electronic packaging and the reliability of the package and the materials that comprise the package and, in particular, the solder interconnects. The need for Pb-free assembly and the application to hand-held electronics has challenged the reliability of electronic packages. This paper discusses packaging reliability of solder interconnects for hand-held wireless and RF applications and describe the tests used to evaluate reliability. The specific reliability issues discussed will be thermomechanical stress (fatigue), solder joint electromigration (DC and RF) and high speed impact stresses (drop test performance).
{"title":"Emerging reliability challenges in electronic packaging","authors":"D. Frear, L. Ramanathan, J. Jang, N. Owens","doi":"10.1109/RELPHY.2008.4558927","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558927","url":null,"abstract":"The trend for microelectronic devices has historically been, and will continue to be, towards smaller feature size, faster speeds, more complexity, higher power and lower cost. The motivating force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunication, RF applications are beginning to drive many areas of microelectronics traditionally led by the development of the microprocessor. An increasingly dominant factor in RF microelectronics is electronic packaging and the reliability of the package and the materials that comprise the package and, in particular, the solder interconnects. The need for Pb-free assembly and the application to hand-held electronics has challenged the reliability of electronic packages. This paper discusses packaging reliability of solder interconnects for hand-held wireless and RF applications and describe the tests used to evaluate reliability. The specific reliability issues discussed will be thermomechanical stress (fatigue), solder joint electromigration (DC and RF) and high speed impact stresses (drop test performance).","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"18 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116859746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558950
K. Lin, C. H. Chao, Tsui-hua Huang, Hsiu-Mei Fan, Shey-Shi Lu
Electron energy loss spectrum (EELS) is widely used for material science analysis (F. R. Chen at al., 1998)(D. B. Williams et al., 1996), such as analyzing material elemental analysis and chemistry compound (Y. Mitsui et al., 1998)(M. Shimada et al., 2005). In semiconductor failure analysis, EELS provides clear evidence for investigating and identifying failure mechanisms and root cause discussions. There are three failure analysis cases in this article. The first one is the nearest atomic number failure analysis. The Z contrast of TEM image is not easy distinguished from Al (13), Si (14), which is obviously identified by EELS Al-K(1560ev) and Si-K(1839ev). [5] The second case is realized from the EELS result, the failure mechanism is silicon dioxide residue that resulted in a transistor out of specification. The third case is a barrier bridge identified by EELS mapping. From the EELS evidence, the root cause is identified as a insufficient tungsten back chemical mechanical polishing (W-back-CMP). Based on clear identification, the EELS application for failure mechanism investigation is very useful and helpful in Semiconductor Failure Analysis.
电子能量损失谱(EELS)广泛应用于材料科学分析(F. R. Chen at al.， 1998)。B. Williams et al.， 1996)，例如分析材料元素分析和化学化合物(Y. Mitsui et al.， 1998)。Shimada et al.， 2005)。在半导体故障分析中，EELS为调查和识别故障机制和根本原因讨论提供了明确的证据。本文中有三个失效分析案例。第一个是最接近原子序数的失效分析。TEM图像的Z对比不容易与Al(13)、Si(14)区分，用EELS Al- k (1560ev)和Si- k (1839ev)可以明显区分。第二种情况是由EELS结果实现的，失效机制是二氧化硅残留导致晶体管不符合规格。第三种情况是EELS映射确定的屏障桥。从EELS证据来看，根本原因被确定为钨背化学机械抛光(W-back-CMP)不足。基于对失效机理的明确认识，利用电子能谱进行失效机理研究对半导体失效分析具有重要意义。
{"title":"Electron energy loss spectrum application for failure mechanism investigation in semiconductor failure analysis","authors":"K. Lin, C. H. Chao, Tsui-hua Huang, Hsiu-Mei Fan, Shey-Shi Lu","doi":"10.1109/RELPHY.2008.4558950","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558950","url":null,"abstract":"Electron energy loss spectrum (EELS) is widely used for material science analysis (F. R. Chen at al., 1998)(D. B. Williams et al., 1996), such as analyzing material elemental analysis and chemistry compound (Y. Mitsui et al., 1998)(M. Shimada et al., 2005). In semiconductor failure analysis, EELS provides clear evidence for investigating and identifying failure mechanisms and root cause discussions. There are three failure analysis cases in this article. The first one is the nearest atomic number failure analysis. The Z contrast of TEM image is not easy distinguished from Al (13), Si (14), which is obviously identified by EELS Al-K(1560ev) and Si-K(1839ev). [5] The second case is realized from the EELS result, the failure mechanism is silicon dioxide residue that resulted in a transistor out of specification. The third case is a barrier bridge identified by EELS mapping. From the EELS evidence, the root cause is identified as a insufficient tungsten back chemical mechanical polishing (W-back-CMP). Based on clear identification, the EELS application for failure mechanism investigation is very useful and helpful in Semiconductor Failure Analysis.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114471505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558867
C. Schlunder, M. Hoffmann, R. Vollertsen, G. Schindler, W. Heinrigs, W. Gustin, H. Reisinger
In recent literature several measurement methods were introduced to characterize the Vth-degradation due to NBTI considering the recovery phenomenon. To our knowledge each method has a severe problem or at least a significant disadvantage. Either there are long delay times, the accuracy is not satisfactory or it is not possible to implement the method with customary equipment. A compromise is to perform a one point measurement in the subthreshold region and calculate Vth based on the assumption that the subthreshold slope is not affected by NBTI. In this paper we disprove the universality of this assumption. Vth determination using a one point measurement can lead to imprecise values. This extraction method disregards changes of the subthreshold slope due to NBTI, however a change of the slope impacts the extracted Vth. We clearly demonstrate this effect with our measurements. We introduce a new smart Vth extraction methodology offering both shortest possible delay times with customary equipment and consideration of NBTI-impact on subthreshold slope.
{"title":"A novel multi-point NBTI characterization methodology using Smart Intermediate Stress (SIS)","authors":"C. Schlunder, M. Hoffmann, R. Vollertsen, G. Schindler, W. Heinrigs, W. Gustin, H. Reisinger","doi":"10.1109/RELPHY.2008.4558867","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558867","url":null,"abstract":"In recent literature several measurement methods were introduced to characterize the Vth-degradation due to NBTI considering the recovery phenomenon. To our knowledge each method has a severe problem or at least a significant disadvantage. Either there are long delay times, the accuracy is not satisfactory or it is not possible to implement the method with customary equipment. A compromise is to perform a one point measurement in the subthreshold region and calculate Vth based on the assumption that the subthreshold slope is not affected by NBTI. In this paper we disprove the universality of this assumption. Vth determination using a one point measurement can lead to imprecise values. This extraction method disregards changes of the subthreshold slope due to NBTI, however a change of the slope impacts the extracted Vth. We clearly demonstrate this effect with our measurements. We introduce a new smart Vth extraction methodology offering both shortest possible delay times with customary equipment and consideration of NBTI-impact on subthreshold slope.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558921
M. Janai, A. Shappir, I. Bloom, B. Eitan
Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster than electron relaxation. The degradation of data retention in cycled NROM cells is interpreted in terms of dispersive transport arising from random-walk of excess holes in the disordered nitride glass.
{"title":"Relaxation of localized charge in trapping-based nonvolatile memory devices","authors":"M. Janai, A. Shappir, I. Bloom, B. Eitan","doi":"10.1109/RELPHY.2008.4558921","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558921","url":null,"abstract":"Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster than electron relaxation. The degradation of data retention in cycled NROM cells is interpreted in terms of dispersive transport arising from random-walk of excess holes in the disordered nitride glass.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558914
Carl V. Thompson
The use of carbon nanotubes (CNTs) to replace or complement Cu-based IC interconnects is under wide-spread investigation. CNTs have low resistivities and can be configured to have low capacitive coupling, and are also chemically stable so that diffusion barriers are not needed. They can also carry very high current densities without damage. Properties and processing of CNTs for IC interconnects are reviewed and emerging technologies and possible reliability issues are discussed.
{"title":"Carbon nanotubes as interconnects: Emerging technology and potential reliability issues","authors":"Carl V. Thompson","doi":"10.1109/RELPHY.2008.4558914","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558914","url":null,"abstract":"The use of carbon nanotubes (CNTs) to replace or complement Cu-based IC interconnects is under wide-spread investigation. CNTs have low resistivities and can be configured to have low capacitive coupling, and are also chemically stable so that diffusion barriers are not needed. They can also carry very high current densities without damage. Properties and processing of CNTs for IC interconnects are reviewed and emerging technologies and possible reliability issues are discussed.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"85 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558876
S. Yokogawa, D. Oshida, H. Tsuchiya, T. Taiji, T. Morita, Y. Tsuchiya, T. Takewaki
A novel method for the prediction of early failure (EF) due to a non-visual defect is proposed for the time-dependent dielectric breakdown (TDDB) of low-k dielectrics. The yield-reliability relation model is modified to evaluate the EFs. The effectiveness of the novel method is experimentally confirmed by using a 65 nm technology node. A bimodal lifetime distribution is used to evaluate the lifetime distribution. The probability of EF can be estimated based on the basis of the results and the defect density of each wafer.
{"title":"Prediction of early failure due to non-visual defect on time-dependent dielectric breakdown of low-k dielectrics: Experimental verification of a yield-reliability model","authors":"S. Yokogawa, D. Oshida, H. Tsuchiya, T. Taiji, T. Morita, Y. Tsuchiya, T. Takewaki","doi":"10.1109/RELPHY.2008.4558876","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558876","url":null,"abstract":"A novel method for the prediction of early failure (EF) due to a non-visual defect is proposed for the time-dependent dielectric breakdown (TDDB) of low-k dielectrics. The yield-reliability relation model is modified to evaluate the EFs. The effectiveness of the novel method is experimentally confirmed by using a 65 nm technology node. A bimodal lifetime distribution is used to evaluate the lifetime distribution. The probability of EF can be estimated based on the basis of the results and the defect density of each wafer.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"133 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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