Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558946
D. Varghese, V. Reddy, H. Shichijo, D. Mosher, S. Krishnan, M. A. Alam
In this paper, we provide the first systematic and comprehensive analysis of off-state degradation in Drain-Extended PMOS transistors - an enabling input/output (I/O) component in many systems and a prototypical example of devices with correlated degradation (i.e., hot carrier damage leading to gate dielectric failure). We use a wide range of characterization tools (e.g., Charge-pumping and multi-frequency charge pumping to probe damage generation, IDLIN measurement for parametric degradation, current-ratio technique to locate breakdown spot, etc.) along with broad range of computational models (e.g., process, device, Monte Carlo models for hot-carrier profiling, asymmetric percolation for failure statistics, etc.) to carefully and systematically map the spatial and temporal dynamics of correlated trap generation in DePMOS transistors. Our key finding is that, despite the apparent complexity and randomness of the trap-generation process, appropriate scaling shows that the mechanics of trap generation is inherently universal. We use the universality to understand the parametric degradation and TDDB of DePMOS transistors and to perform lifetime projections from stress to operating conditions.
{"title":"A comprehensive analysis of off-state stress in drain extended PMOS transistors: Theory and characterization of parametric degradation and dielectric failure","authors":"D. Varghese, V. Reddy, H. Shichijo, D. Mosher, S. Krishnan, M. A. Alam","doi":"10.1109/RELPHY.2008.4558946","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558946","url":null,"abstract":"In this paper, we provide the first systematic and comprehensive analysis of off-state degradation in Drain-Extended PMOS transistors - an enabling input/output (I/O) component in many systems and a prototypical example of devices with correlated degradation (i.e., hot carrier damage leading to gate dielectric failure). We use a wide range of characterization tools (e.g., Charge-pumping and multi-frequency charge pumping to probe damage generation, IDLIN measurement for parametric degradation, current-ratio technique to locate breakdown spot, etc.) along with broad range of computational models (e.g., process, device, Monte Carlo models for hot-carrier profiling, asymmetric percolation for failure statistics, etc.) to carefully and systematically map the spatial and temporal dynamics of correlated trap generation in DePMOS transistors. Our key finding is that, despite the apparent complexity and randomness of the trap-generation process, appropriate scaling shows that the mechanics of trap generation is inherently universal. We use the universality to understand the parametric degradation and TDDB of DePMOS transistors and to perform lifetime projections from stress to operating conditions.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123427328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558896
M. Khazhinsky, M. Chowdhury, D. Tekleab, L. Mathew, J. Miller
In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.
{"title":"Study of undoped channel FinFETs in active rail clamp ESD networks","authors":"M. Khazhinsky, M. Chowdhury, D. Tekleab, L. Mathew, J. Miller","doi":"10.1109/RELPHY.2008.4558896","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558896","url":null,"abstract":"In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123624358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558855
C. Duvvury
For more than 20 years, IC component level ESD requirements have essentially stayed constant, while the silicon technologies rapidly advanced and effective production control methods have vastly improved. The silicon area impact coming from the technology scaling, combined with the high speed circuit performance impact and the influence from the IC package technology advances, are making the ESD design to the current levels a constraint leading to permanent delays in the product innovative cycles. Todaypsilas enhanced control methods do not justify this ESD over-design. This paper will propose a paradigm shift to more realistic but safe ESD target levels based on field data collected from IC suppliers and contract manufacturers.
{"title":"Paradigm shift in ESD qualification","authors":"C. Duvvury","doi":"10.1109/RELPHY.2008.4558855","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558855","url":null,"abstract":"For more than 20 years, IC component level ESD requirements have essentially stayed constant, while the silicon technologies rapidly advanced and effective production control methods have vastly improved. The silicon area impact coming from the technology scaling, combined with the high speed circuit performance impact and the influence from the IC package technology advances, are making the ESD design to the current levels a constraint leading to permanent delays in the product innovative cycles. Todaypsilas enhanced control methods do not justify this ESD over-design. This paper will propose a paradigm shift to more realistic but safe ESD target levels based on field data collected from IC suppliers and contract manufacturers.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558929
M. van Soestbergen, R. Rongen, J. Knol, A. Mavinkurve, J. Egbers, S. Nath, G.Q. Zhang, L. Ernst
The supply current of plastic encapsulated microelectronic devices in the presence of a high potential source can increase abnormally due to parasitic gate leakage. According to reliability qualification standards, stress during a parasitic gate leakage test is applied by a corona discharge at a thin tungsten needle placed a few centimeters above the devices under test. The gate leakage sensitivity factor obtained from this test lacks any physical basis and is therefore not believed to be useful. Here we show that this sensitivity factor can be replaced by a physical model for charge transport through the encapsulation material. The model is used to explain why devices encapsulated by a molding compound with a low volume resistivity of 6 times 1011 Ohm-cm, at high temperature, 150degC, are more prone to fail the test on an increased current, compared to devices encapsulated by a compound having a high resistivity of 4 times 1013 Ohmtimescm at the same temperature. Furthermore, we discuss an alternative test setup where the potential difference between two parallel electrodes sandwiching the devices is used as the source of stress. It is suggested in literature that this setup yields identical results as the current setup. However, using both setups on the same product did not result in an equal outcome, which indicates that both tests do not trigger the same failure mechanism to the same extent.
{"title":"Electrical characterization of plastic encapsulations using an alternative gate leakage test method","authors":"M. van Soestbergen, R. Rongen, J. Knol, A. Mavinkurve, J. Egbers, S. Nath, G.Q. Zhang, L. Ernst","doi":"10.1109/RELPHY.2008.4558929","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558929","url":null,"abstract":"The supply current of plastic encapsulated microelectronic devices in the presence of a high potential source can increase abnormally due to parasitic gate leakage. According to reliability qualification standards, stress during a parasitic gate leakage test is applied by a corona discharge at a thin tungsten needle placed a few centimeters above the devices under test. The gate leakage sensitivity factor obtained from this test lacks any physical basis and is therefore not believed to be useful. Here we show that this sensitivity factor can be replaced by a physical model for charge transport through the encapsulation material. The model is used to explain why devices encapsulated by a molding compound with a low volume resistivity of 6 times 1011 Ohm-cm, at high temperature, 150degC, are more prone to fail the test on an increased current, compared to devices encapsulated by a compound having a high resistivity of 4 times 1013 Ohmtimescm at the same temperature. Furthermore, we discuss an alternative test setup where the potential difference between two parallel electrodes sandwiching the devices is used as the source of stress. It is suggested in literature that this setup yields identical results as the current setup. However, using both setups on the same product did not result in an equal outcome, which indicates that both tests do not trigger the same failure mechanism to the same extent.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122714296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558859
T. Grasser, B. Kaczer, W. Goes
Many recent publications discussing the stress and recovery behavior of bias temperature instability (BTI) have suggested the existence of two components contributing to the phenomenon. One of these components was found to be quickly relaxing while the other was only slowly relaxing or even permanent. Curiously, although the most likely suggested mechanisms are the generation of interface states and the capture of holes into pre-existing traps, there is no agreement on which mechanism corresponds to which component and both possibilities have been suggested. Alternatively, other groups have suggested evidence that BTI is dominated by a single mechanism, and used the reaction-diffusion (RD) model to describe the degradation. However, RD theory cannot explain the recovery and related intricacies of the phenomenon. We present a new modeling framework based on the various possible energetic configurations of the system and tentatively assign these levels to the hydrogen binding/transport levels in an amorphous oxide. We investigate the possibility that the often observed recoverable and permanent components are in fact two facets of a single degradation mechanism proceeding as a series of steps. We finally subject the model to various experimental data (DC, AC, duty-factor, negative and positive stress, mixed stresses) which are all well reproduced by the model.
{"title":"An energy-level perspective of bias temperature instability","authors":"T. Grasser, B. Kaczer, W. Goes","doi":"10.1109/RELPHY.2008.4558859","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558859","url":null,"abstract":"Many recent publications discussing the stress and recovery behavior of bias temperature instability (BTI) have suggested the existence of two components contributing to the phenomenon. One of these components was found to be quickly relaxing while the other was only slowly relaxing or even permanent. Curiously, although the most likely suggested mechanisms are the generation of interface states and the capture of holes into pre-existing traps, there is no agreement on which mechanism corresponds to which component and both possibilities have been suggested. Alternatively, other groups have suggested evidence that BTI is dominated by a single mechanism, and used the reaction-diffusion (RD) model to describe the degradation. However, RD theory cannot explain the recovery and related intricacies of the phenomenon. We present a new modeling framework based on the various possible energetic configurations of the system and tentatively assign these levels to the hydrogen binding/transport levels in an amorphous oxide. We investigate the possibility that the often observed recoverable and permanent components are in fact two facets of a single degradation mechanism proceeding as a series of steps. We finally subject the model to various experimental data (DC, AC, duty-factor, negative and positive stress, mixed stresses) which are all well reproduced by the model.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122930910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558997
K. Hosotani, M. Nagamine, H. Aikawa, N. Shimomura, M. Nakayama, T. Kai, S. Ikegawa, Y. Asao, H. Yoda, A. Nitayama
Magnetoresistive Random Access Memory (MRAM) is a promising device for high-density (over Gbits scale), high-speed (equal to DRAM or better) non-volatile RAM, and much research has been done over several years with a view to overcoming the problems regarding practical use. Spin Torque Transfer switching MRAM (STT-MRAM) is considered to be the most promising candidate and there already are some papers on this new device. MgO is expected to be the best material for magnetic tunnel junction (MTJ) of STT-MRAM, because MgO-MTJ is known to show large Magnetoresistance (MR) and enhance spin polarization by the coherent tunneling effect, resulting in decrease of writing current of MTJ. MgO-MTJ has been shown to be an excellent barrier with little resistance drift compared with MTJ using alumina. Notwithstanding its excellent potential, the degradation mechanism of MgO-MTJ has not been well understood. In this paper, we will demonstrate for the first time the degradation of coherent tunneling and trapping phenomena of MgO-MTJ and discuss its mechanism.
{"title":"Resistance drift of MgO magnetic tunnel junctions by trapping and degradation of coherent tunneling","authors":"K. Hosotani, M. Nagamine, H. Aikawa, N. Shimomura, M. Nakayama, T. Kai, S. Ikegawa, Y. Asao, H. Yoda, A. Nitayama","doi":"10.1109/RELPHY.2008.4558997","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558997","url":null,"abstract":"Magnetoresistive Random Access Memory (MRAM) is a promising device for high-density (over Gbits scale), high-speed (equal to DRAM or better) non-volatile RAM, and much research has been done over several years with a view to overcoming the problems regarding practical use. Spin Torque Transfer switching MRAM (STT-MRAM) is considered to be the most promising candidate and there already are some papers on this new device. MgO is expected to be the best material for magnetic tunnel junction (MTJ) of STT-MRAM, because MgO-MTJ is known to show large Magnetoresistance (MR) and enhance spin polarization by the coherent tunneling effect, resulting in decrease of writing current of MTJ. MgO-MTJ has been shown to be an excellent barrier with little resistance drift compared with MTJ using alumina. Notwithstanding its excellent potential, the degradation mechanism of MgO-MTJ has not been well understood. In this paper, we will demonstrate for the first time the degradation of coherent tunneling and trapping phenomena of MgO-MTJ and discuss its mechanism.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130948645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558880
T. Mcmahon
Solar cell/module degradation and failure diagnostics are reviewed. Cell and packaging failure are distinguished. Failure relevant to photovoltaics(PV) is caused by and can be accelerated with each or combination of each of the following stresses: temperature, voltage, moisture, current, and thermal cycling. Failure mechanisms for the different module technologies are summarized. Diagnostic tools for locating the affected area within a large-area module are pointed out along with the importance of interpretation of the visual appearance of the different damage mechanisms.
{"title":"Solar cell/module degradation and failure diagnostics","authors":"T. Mcmahon","doi":"10.1109/RELPHY.2008.4558880","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558880","url":null,"abstract":"Solar cell/module degradation and failure diagnostics are reviewed. Cell and packaging failure are distinguished. Failure relevant to photovoltaics(PV) is caused by and can be accelerated with each or combination of each of the following stresses: temperature, voltage, moisture, current, and thermal cycling. Failure mechanisms for the different module technologies are summarized. Diagnostic tools for locating the affected area within a large-area module are pointed out along with the importance of interpretation of the visual appearance of the different damage mechanisms.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"542 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558869
peixiong zhao, K. Warren, R. Weller, R. Reed, L. Massengill, M. Alles, D. Fleetwood, X.J. Zhou, L. Tsetseris, S. Pantelides
The reliability of advanced integrated circuit (IC) technologies may be dominated by the interaction of environmental radiation with the devices in the ICs. In particular, single event upsets (SEUs) and soft errors produced by single energetic particles may have a significant impact on the error rate of digital ICs. Additionally, some of the mechanisms responsible for long-term degradation of ICs under normal operating conditions are related to degradation mechanisms produced by ionizing radiation. This paper reviews issues related to prediction of error rates in ICs and discusses the roles of hydrogen in bias-temperature instability and total-ionizingdose radiation sensitivity.
{"title":"Reliability and radiation effects in IC technologies","authors":"peixiong zhao, K. Warren, R. Weller, R. Reed, L. Massengill, M. Alles, D. Fleetwood, X.J. Zhou, L. Tsetseris, S. Pantelides","doi":"10.1109/RELPHY.2008.4558869","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558869","url":null,"abstract":"The reliability of advanced integrated circuit (IC) technologies may be dominated by the interaction of environmental radiation with the devices in the ICs. In particular, single event upsets (SEUs) and soft errors produced by single energetic particles may have a significant impact on the error rate of digital ICs. Additionally, some of the mechanisms responsible for long-term degradation of ICs under normal operating conditions are related to degradation mechanisms produced by ionizing radiation. This paper reviews issues related to prediction of error rates in ICs and discusses the roles of hydrogen in bias-temperature instability and total-ionizingdose radiation sensitivity.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"5 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127257711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558973
M. Sato, C. Tamura, K. Yamabe, K. Shiraishi, K. Yamada, R. Hasunuma, T. Aoyama, Y. Nara, Y. Ohji
This study aims to investigate the application of a technique to separate bulk hole trap effects from interface state degradation in NBTI to understand hole traps behavior including MOSFET fabrication process dependence. A gate last process is used to fabricate the pMOSFETs with HfSiON/TiN gate stacks. Results show that RTA is an effective method for reducing pre-existing hole traps, while nitridation is effective in the thermally de-activation of hole traps. The hole traps, which are thought to be due to the negatively charged interstitial oxygen, increase logarithmically with hole injection.
{"title":"Fabrication process controlled pre-existing and charge - discharge effect of hole traps in NBTI of high-k / metal gate pMOSFET","authors":"M. Sato, C. Tamura, K. Yamabe, K. Shiraishi, K. Yamada, R. Hasunuma, T. Aoyama, Y. Nara, Y. Ohji","doi":"10.1109/RELPHY.2008.4558973","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558973","url":null,"abstract":"This study aims to investigate the application of a technique to separate bulk hole trap effects from interface state degradation in NBTI to understand hole traps behavior including MOSFET fabrication process dependence. A gate last process is used to fabricate the pMOSFETs with HfSiON/TiN gate stacks. Results show that RTA is an effective method for reducing pre-existing hole traps, while nitridation is effective in the thermally de-activation of hole traps. The hole traps, which are thought to be due to the negatively charged interstitial oxygen, increase logarithmically with hole injection.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125711763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558868
A. Islam, V. Maheta, H. Das, S. Mahapatra, M. A. Alam
Mobility degradation due to generation of interface traps (Deltamueff(NIT)) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Deltamueff(NIT) is relatively insignificant (compared to Deltamueff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis. Here, we investigate the importance of considering Deltamueff(NIT) for reliability analysis by analyzing a wide variety of plasma oxynitride PMOS devices using both parametric and physical mobility models. We find that contrary to popular belief this correction is fundamentally important for robust and uncorrupted estimates of the key reliability parameters like threshold-voltage shift, lifetime projection, voltage acceleration factor, etc. Therefore, in this paper, we develop a generalized algorithm for estimating Deltamueff(NIT) for plasma oxynitride PMOS devices and systematically explore its implications for NBTI-specific reliability analysis.
{"title":"Mobility degradation due to interface traps in plasma oxynitride PMOS devices","authors":"A. Islam, V. Maheta, H. Das, S. Mahapatra, M. A. Alam","doi":"10.1109/RELPHY.2008.4558868","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558868","url":null,"abstract":"Mobility degradation due to generation of interface traps (Deltamueff(NIT)) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Deltamueff(NIT) is relatively insignificant (compared to Deltamueff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis. Here, we investigate the importance of considering Deltamueff(NIT) for reliability analysis by analyzing a wide variety of plasma oxynitride PMOS devices using both parametric and physical mobility models. We find that contrary to popular belief this correction is fundamentally important for robust and uncorrupted estimates of the key reliability parameters like threshold-voltage shift, lifetime projection, voltage acceleration factor, etc. Therefore, in this paper, we develop a generalized algorithm for estimating Deltamueff(NIT) for plasma oxynitride PMOS devices and systematically explore its implications for NBTI-specific reliability analysis.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126115445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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