Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559003
Tao Cheng, M.Z. Lee, M. Yang
A new device reliability evaluation method is reported for the circuit application under voltage overdrive. Through an appropriate methodology shown in this paper, the 3.3V CMOS oxide reliability can be passed the specification and well characterized, even under 8V at drain side overdrive in some circuit application.
{"title":"A new device reliability evaluation method for overdrive voltage circuit application","authors":"Tao Cheng, M.Z. Lee, M. Yang","doi":"10.1109/RELPHY.2008.4559003","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559003","url":null,"abstract":"A new device reliability evaluation method is reported for the circuit application under voltage overdrive. Through an appropriate methodology shown in this paper, the 3.3V CMOS oxide reliability can be passed the specification and well characterized, even under 8V at drain side overdrive in some circuit application.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124579347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558877
Hiroshi Miyazaki, D. Kodama, N. Suzumura
Time-dependent dielectric breakdown (TDDB) was investigated, noting the time variation of stress-induce leakage current (SILC) between copper (Cu) lines. To clarify the TDDB mechanism, triangular voltage sweep (TVS) and bias temperature aging were alternatively performed for Cu damascene structures. The SILC was largely increased with stress time; however no Cu ion peak was detected in TVS measurements. The point-symmetric TVS hysteresis clearly indicates that the distribution of stress-induced defects is independent of electric polarity, namely it is a random or symmetric distribution. In addition, the SILC of Cu interconnect increased as slow as that of tungsten (W) in the usual bias temperature aging. Since the optimize barrier process sufficiently suppresses Cu ion drift in TDDB testing, the dielectric breakdown is only controlled by intrinsic factors. When the protection against moisture is structurally insufficient, the water-related degradation is seriously pronounced instead of Cu ion drift. The water-absorbed interconnect abruptly breaks down while the current is decreasing. Just before the breakdown, the asymmetric TVS hysteresis appears. Therefore, TVS observation enables us to distinguish whether stress-induced leakage current comes from intrinsic or extrinsic causes.
{"title":"The observation of stress-induced leakage current of damascene interconnects after bias temperature aging","authors":"Hiroshi Miyazaki, D. Kodama, N. Suzumura","doi":"10.1109/RELPHY.2008.4558877","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558877","url":null,"abstract":"Time-dependent dielectric breakdown (TDDB) was investigated, noting the time variation of stress-induce leakage current (SILC) between copper (Cu) lines. To clarify the TDDB mechanism, triangular voltage sweep (TVS) and bias temperature aging were alternatively performed for Cu damascene structures. The SILC was largely increased with stress time; however no Cu ion peak was detected in TVS measurements. The point-symmetric TVS hysteresis clearly indicates that the distribution of stress-induced defects is independent of electric polarity, namely it is a random or symmetric distribution. In addition, the SILC of Cu interconnect increased as slow as that of tungsten (W) in the usual bias temperature aging. Since the optimize barrier process sufficiently suppresses Cu ion drift in TDDB testing, the dielectric breakdown is only controlled by intrinsic factors. When the protection against moisture is structurally insufficient, the water-related degradation is seriously pronounced instead of Cu ion drift. The water-absorbed interconnect abruptly breaks down while the current is decreasing. Just before the breakdown, the asymmetric TVS hysteresis appears. Therefore, TVS observation enables us to distinguish whether stress-induced leakage current comes from intrinsic or extrinsic causes.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558955
A. Padovani, L. Larcher, S. Verma, P. Pavan, P. Majhi, P. Kapur, K. Parat, G. Bersuker, K. Saraswat
We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.
{"title":"Statistical Modeling of Leakage Currents Through SiO2/High-κ Dielectrics Stacks for Non-Volatile Memory Applications","authors":"A. Padovani, L. Larcher, S. Verma, P. Pavan, P. Majhi, P. Kapur, K. Parat, G. Bersuker, K. Saraswat","doi":"10.1109/RELPHY.2008.4558955","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558955","url":null,"abstract":"We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130552052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559004
A. Vassighi, R. Kacprowicz, C. Carranza, W. Riordan
Due to the large sample sizes required, certain reliability modeling parameters for infant mortality cannot be measured during technology development with desired confidence levels by engineering experiments. Among these reliability modeling parameters is thermal energy activation (Ea). Ea is used in the Arrhenius equation to calculate the burn-in time for integrated circuits. A small change in this parameter can have a great impact in burn-in time. In this work we have measured this parameter in high volume manufacturing (HVM) in 65 nm technology using naturally occurring data by applying novel new techniques at virtually no cost.
{"title":"Characterizing infant mortality in high volume manufacturing","authors":"A. Vassighi, R. Kacprowicz, C. Carranza, W. Riordan","doi":"10.1109/RELPHY.2008.4559004","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559004","url":null,"abstract":"Due to the large sample sizes required, certain reliability modeling parameters for infant mortality cannot be measured during technology development with desired confidence levels by engineering experiments. Among these reliability modeling parameters is thermal energy activation (Ea). Ea is used in the Arrhenius equation to calculate the burn-in time for integrated circuits. A small change in this parameter can have a great impact in burn-in time. In this work we have measured this parameter in high volume manufacturing (HVM) in 65 nm technology using naturally occurring data by applying novel new techniques at virtually no cost.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124352486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558982
A. Goyal, J. Whitfield, Changsoo Hong, C. Gill, C. Rouying Zhan, V. Kushner, A. Gendron, S. Contractor
We have identified and explained a unique ESD breakdown mechanism of high voltage 80V LDMOS structures for very fast CDM transients. The device was protected against observed damage by placing a zener across the gate and source which prevents the observed voltage build up at the gate of the LDMOS.
{"title":"Unique ESD failure mechanism of high voltage LDMOS transistors for very fast transients","authors":"A. Goyal, J. Whitfield, Changsoo Hong, C. Gill, C. Rouying Zhan, V. Kushner, A. Gendron, S. Contractor","doi":"10.1109/RELPHY.2008.4558982","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558982","url":null,"abstract":"We have identified and explained a unique ESD breakdown mechanism of high voltage 80V LDMOS structures for very fast CDM transients. The device was protected against observed damage by placing a zener across the gate and source which prevents the observed voltage build up at the gate of the LDMOS.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128002468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558897
F. Farbiz, E. Rosenbaum
Circuit models are presented that allow one to identify the worst-case testing condition for external latchup and to simulate the value of the latchup trigger current. The models are valid under both moderate and high-level injection. A good fit between the model and the measurements is observed. The roles of substrate majority and minority carriers are elucidated.
{"title":"Modeling of majority and minority carrier triggered external latchup","authors":"F. Farbiz, E. Rosenbaum","doi":"10.1109/RELPHY.2008.4558897","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558897","url":null,"abstract":"Circuit models are presented that allow one to identify the worst-case testing condition for external latchup and to simulate the value of the latchup trigger current. The models are valid under both moderate and high-level injection. A good fit between the model and the measurements is observed. The roles of substrate majority and minority carriers are elucidated.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127933491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558907
X. Garros, P. Besson, G. Reimbold, V. Loup, T. Salvetat, N. Rochat, S. Lhostis, F. Boulanger
This paper investigates the impact of crystallinity of HfO2 oxides on VT instabilities. Wet etch rate measurements enhances a critical thickness tHK C for HfO2 which marks the transition between a monoclinic crystalline phase to a near amorphous state, both clearly identified by ATR FTIR. Using electrical measurements and modeling, it is demonstrated that this transition from the crystalline phase to an amorphous state is accompanied by a strong reduction of the density of bulk HfO2 defects responsible for electron trapping, Prevents the crystallization of an high-k layer is therefore fundamental to improve its BTI reliability.
{"title":"Impact of crystallinity of High-k oxides on Vt instabilities of NMOS devices assessed by physical and electrical measurements","authors":"X. Garros, P. Besson, G. Reimbold, V. Loup, T. Salvetat, N. Rochat, S. Lhostis, F. Boulanger","doi":"10.1109/RELPHY.2008.4558907","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558907","url":null,"abstract":"This paper investigates the impact of crystallinity of HfO2 oxides on VT instabilities. Wet etch rate measurements enhances a critical thickness tHK C for HfO2 which marks the transition between a monoclinic crystalline phase to a near amorphous state, both clearly identified by ATR FTIR. Using electrical measurements and modeling, it is demonstrated that this transition from the crystalline phase to an amorphous state is accompanied by a strong reduction of the density of bulk HfO2 defects responsible for electron trapping, Prevents the crystallization of an high-k layer is therefore fundamental to improve its BTI reliability.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131295944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559014
D. Ang, G. Du, Y.Z. Hu, S. Wang, C. Ng
Evidence from negative-bias temperature stressing of both p- and n-MOSFET employing the ultra-thin (15 Aring) plasma-nitrided gate dielectric shows that stress induced Si/SiON interface states have (1) a bipolar, i.e. both acceptor- and donor-like, characteristic in the upper-half of the Si bandgap and (2) a donor-like characteristic in the lower-half of the Si bandgap. During Id-Vg measurement of the p-MOSFET, interface states above mid-gap behave like ldquopositive oxide trapped chargerdquo, resulting in a negative shift of the subthreshold I-V curve of the p-MOSFET. On the other hand, a change in charge state from positive-to-negative, during positive gate bias sweep, results in a significant ldquostretch-outrdquo of the n-MOSFET subthreshold I-V curve. As a consequence of this bipolar charge-state transition, stress induced interface state density extracted from subthreshold swing degradation of the n-MOSFET is consistently ~2times that obtained from the increase in the charge pumping current.
{"title":"Energy distribution and electrical characteristics of NBTI induced Si/SiON interface states","authors":"D. Ang, G. Du, Y.Z. Hu, S. Wang, C. Ng","doi":"10.1109/RELPHY.2008.4559014","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559014","url":null,"abstract":"Evidence from negative-bias temperature stressing of both p- and n-MOSFET employing the ultra-thin (15 Aring) plasma-nitrided gate dielectric shows that stress induced Si/SiON interface states have (1) a bipolar, i.e. both acceptor- and donor-like, characteristic in the upper-half of the Si bandgap and (2) a donor-like characteristic in the lower-half of the Si bandgap. During Id-Vg measurement of the p-MOSFET, interface states above mid-gap behave like ldquopositive oxide trapped chargerdquo, resulting in a negative shift of the subthreshold I-V curve of the p-MOSFET. On the other hand, a change in charge state from positive-to-negative, during positive gate bias sweep, results in a significant ldquostretch-outrdquo of the n-MOSFET subthreshold I-V curve. As a consequence of this bipolar charge-state transition, stress induced interface state density extracted from subthreshold swing degradation of the n-MOSFET is consistently ~2times that obtained from the increase in the charge pumping current.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116287816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558940
S. Mitra
The idea behind circuit failure prediction is to predict the occurrence of a circuit failure before errors actually appear in system data and states. This concept enables a sea change in robust system design by overcoming major reliability challenges such as circuit aging and early-life failures (infant mortality).
{"title":"Circuit failure prediction for robust system design in scaled CMOS","authors":"S. Mitra","doi":"10.1109/RELPHY.2008.4558940","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558940","url":null,"abstract":"The idea behind circuit failure prediction is to predict the occurrence of a circuit failure before errors actually appear in system data and states. This concept enables a sea change in robust system design by overcoming major reliability challenges such as circuit aging and early-life failures (infant mortality).","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126450487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4559005
S. Kitazaki, Y. Kumura, S. Shuto, T. Ozaki, T. Hamamoto, A. Nitayama
The most appropriate method to evaluate the process damage is proposed. FeRAM process is used as a damage source. The degradation of the drain current of long-channel MOSFET is larger than that of short-channel MOSFET, although long-channel MOSFET has been believed to be more robust. In the case of short-channel MOSFET, the drain current is limited by saturation velocity, and thus the mobility degradation caused by the process damage has a smaller influence. On the contrary, in the case of long-channel MOSFET, the drain current is not limited by saturation velocity, which leads to the degradation of the drain current owing to the mobility reduction caused by the process damage of the FeRAM capacitor process. These results suggest that the most accurate method for evaluating the process damage is to monitor the degradation of the drain current of long-channel MOSFET.
{"title":"A novel characterization method to monitor process damage for transistors","authors":"S. Kitazaki, Y. Kumura, S. Shuto, T. Ozaki, T. Hamamoto, A. Nitayama","doi":"10.1109/RELPHY.2008.4559005","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4559005","url":null,"abstract":"The most appropriate method to evaluate the process damage is proposed. FeRAM process is used as a damage source. The degradation of the drain current of long-channel MOSFET is larger than that of short-channel MOSFET, although long-channel MOSFET has been believed to be more robust. In the case of short-channel MOSFET, the drain current is limited by saturation velocity, and thus the mobility degradation caused by the process damage has a smaller influence. On the contrary, in the case of long-channel MOSFET, the drain current is not limited by saturation velocity, which leads to the degradation of the drain current owing to the mobility reduction caused by the process damage of the FeRAM capacitor process. These results suggest that the most accurate method for evaluating the process damage is to monitor the degradation of the drain current of long-channel MOSFET.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116077583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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