Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558939
M. Porter, P. Gerrish, L. Tyler, S. Murray, R. Mauriello, F. Soto, G. Phetteplace, S. Hareland
Implantable medical devices continue to grow in complexity, mirroring the ascent of the semiconductor industry along the Moorepsilas Law curve. Traditionally, implantable applications have taken a fast-follower approach to silicon adoption, using more mature technologies to reduce risk. While commercial manufacturers, in some circumstances, may be able to trade off lifetime requirements for performance, this is decidedly not the case for implantable use, where 10 to 12 year requirements are typical. On the other hand, hardware and software redundancy solutions employed by high reliability avionics, telecommunications, and servers are difficult to implement in a battery-powered device, where current drain restrictions are severe. This paper discusses some of the reliability challenges faced by implantable device manufacturers as the need to provide more sophisticated therapy and diagnostics requires increasingly advanced technologies.
{"title":"Reliability considerations for implantable medical ICs","authors":"M. Porter, P. Gerrish, L. Tyler, S. Murray, R. Mauriello, F. Soto, G. Phetteplace, S. Hareland","doi":"10.1109/RELPHY.2008.4558939","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558939","url":null,"abstract":"Implantable medical devices continue to grow in complexity, mirroring the ascent of the semiconductor industry along the Moorepsilas Law curve. Traditionally, implantable applications have taken a fast-follower approach to silicon adoption, using more mature technologies to reduce risk. While commercial manufacturers, in some circumstances, may be able to trade off lifetime requirements for performance, this is decidedly not the case for implantable use, where 10 to 12 year requirements are typical. On the other hand, hardware and software redundancy solutions employed by high reliability avionics, telecommunications, and servers are difficult to implement in a battery-powered device, where current drain restrictions are severe. This paper discusses some of the reliability challenges faced by implantable device manufacturers as the need to provide more sophisticated therapy and diagnostics requires increasingly advanced technologies.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115269584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558992
H. Lue, T. Hsu, Szu-Yu Wang, E. Lai, K. Hsieh, R. Liu, Chih-Yuan Lu
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal property for any charge-trapping devices, assuming charges are fully captured. However, when the device is integrated in various STI geometries, the ISPP slope is often degraded. This is due to the STI edge effect. Non-uniform injection happens along the channel width and degrades the programming efficiency at higher VT levels. The degradation of trans-conductance (gm) and subthreshold slope (S.S) during programming validates the STI edge effect. We find that through process modifications for the STI edge, the ISPP slope can be improved.
{"title":"study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash","authors":"H. Lue, T. Hsu, Szu-Yu Wang, E. Lai, K. Hsieh, R. Liu, Chih-Yuan Lu","doi":"10.1109/RELPHY.2008.4558992","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558992","url":null,"abstract":"Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal property for any charge-trapping devices, assuming charges are fully captured. However, when the device is integrated in various STI geometries, the ISPP slope is often degraded. This is due to the STI edge effect. Non-uniform injection happens along the channel width and degrades the programming efficiency at higher VT levels. The degradation of trans-conductance (gm) and subthreshold slope (S.S) during programming validates the STI edge effect. We find that through process modifications for the STI edge, the ISPP slope can be improved.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115950921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558881
D. Xi, Chenjun Shi, Yan Yao, Yang Yang, Q. Pei
Polymer solar cells generally contain a low bandgap p-type conjugated polymer as photosensitizer and an inorganic or organic n-type semiconductor as electron acceptor. We investigated two nanostructured composites of the complementary semiconductors: nanometer-scale blends and interpenetrating nanorod arrays. In the blend approach, new low bandgap polymers were synthesized to match with electron-acceptors such as C60-PCBM and C70-PCBM for increased absorption efficiency. The nanorod arrays were fabricated by solution-based electrochemical growth. Photovoltaic performance of the composites is also discussed.
{"title":"Nanostructured polymer solar cells","authors":"D. Xi, Chenjun Shi, Yan Yao, Yang Yang, Q. Pei","doi":"10.1109/RELPHY.2008.4558881","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558881","url":null,"abstract":"Polymer solar cells generally contain a low bandgap p-type conjugated polymer as photosensitizer and an inorganic or organic n-type semiconductor as electron acceptor. We investigated two nanostructured composites of the complementary semiconductors: nanometer-scale blends and interpenetrating nanorod arrays. In the blend approach, new low bandgap polymers were synthesized to match with electron-acceptors such as C60-PCBM and C70-PCBM for increased absorption efficiency. The nanorod arrays were fabricated by solution-based electrochemical growth. Photovoltaic performance of the composites is also discussed.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121400420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558916
C. Hau-Riege, A. Marathe, Z.-S. Choi
We have conducted electromigration tests on Cu/low-k standard short-line structures as well as those with varying numbers of reservoirs. We found that the presence and number of reservoirs as well as current direction relative to the reservoir led to markedly different electromigration performance in terms of lifetime and distribution shape. That is, in the case of a reservoir by the anode (or electron sink) line-end, lifetimes were similar or slightly better than the In the case of a reservoir by the cathode (or electron source) line-end, lifetimes were extremely longer than the long-line case or even immortal. Further, the distribution of the cathode reservoir structure exhibited a roll-over shape, in which the first fails corresponded to small void sizes and the later fails corresponded to larger void sizes. We believe these observations are related to the differences in stress development during electromigration, which will be constrained at the line-end at which the reservoir is present, and has been verified through simulation. Finally, we propose a method for assigning an equivalent length to these complex short-line configurations which indicates a ldquostrengthrdquo of the short-line benefit which would be equivalent to that of a standard short-line.
{"title":"The effect of current direction on the electromigration in short-lines with reservoirs","authors":"C. Hau-Riege, A. Marathe, Z.-S. Choi","doi":"10.1109/RELPHY.2008.4558916","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558916","url":null,"abstract":"We have conducted electromigration tests on Cu/low-k standard short-line structures as well as those with varying numbers of reservoirs. We found that the presence and number of reservoirs as well as current direction relative to the reservoir led to markedly different electromigration performance in terms of lifetime and distribution shape. That is, in the case of a reservoir by the anode (or electron sink) line-end, lifetimes were similar or slightly better than the In the case of a reservoir by the cathode (or electron source) line-end, lifetimes were extremely longer than the long-line case or even immortal. Further, the distribution of the cathode reservoir structure exhibited a roll-over shape, in which the first fails corresponded to small void sizes and the later fails corresponded to larger void sizes. We believe these observations are related to the differences in stress development during electromigration, which will be constrained at the line-end at which the reservoir is present, and has been verified through simulation. Finally, we propose a method for assigning an equivalent length to these complex short-line configurations which indicates a ldquostrengthrdquo of the short-line benefit which would be equivalent to that of a standard short-line.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125296023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558928
Y. Li, M. van Gils, W. V. van Driel, R. van Silfhout, J. Bisschop, J. Janssen, G.Q. Zhang
In this work the impact of the layout of the top metal of the integrated circuit (IC) and the most relevant process and material parameters of IC wafer fab and assembly fab on package stress induced damages to the ICs during temperature cycling is studied by means of thermo-mechanical simulations with experimental verifications. Besides die size, the materials for passivation, silicon thickness, molding compound properties, the cohesion between the molding compound and the die surface, and lead frame yield stress, all are found to significantly influence the risk of damages or failures on the IC surface. The results suggest a more complete package stress relief design rule, pointing to a systematic approach to eliminate or suppress the package stress induced damages to the IC and consequently a possibly more efficient use of the silicon area in IC design.
{"title":"Impact of IC wafer fab and assembly fab processes on package stress induced product reliability issues - an insight into the package stress relief design rules by simulation","authors":"Y. Li, M. van Gils, W. V. van Driel, R. van Silfhout, J. Bisschop, J. Janssen, G.Q. Zhang","doi":"10.1109/RELPHY.2008.4558928","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558928","url":null,"abstract":"In this work the impact of the layout of the top metal of the integrated circuit (IC) and the most relevant process and material parameters of IC wafer fab and assembly fab on package stress induced damages to the ICs during temperature cycling is studied by means of thermo-mechanical simulations with experimental verifications. Besides die size, the materials for passivation, silicon thickness, molding compound properties, the cohesion between the molding compound and the die surface, and lead frame yield stress, all are found to significantly influence the risk of damages or failures on the IC surface. The results suggest a more complete package stress relief design rule, pointing to a systematic approach to eliminate or suppress the package stress induced damages to the IC and consequently a possibly more efficient use of the silicon area in IC design.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558975
I. Hirano, T. Yamaguchi, Y. Nakasaki, K. Sekine, Y. Mitani
In this paper, we investigate the correlation between traps and the degradation of reliability in HfSiON/SiO2 stacks with F incorporation. It was found that the nature of generated traps corresponds to that of pre-existing traps. Namely new traps cannot be generated if there is no seeds traps which can be eliminate by F incorporation. The controlling pre-existing electron traps which work as seeds traps is effective for suppression of degradation. As TDDB and BTI lifetime strongly depends on trap characteristics, such as positions and their levels, the dominant traps concerning the degradations differ for each reliability characteristic, and also depending on stress polarities in FETs.
{"title":"Influence of pre-existing and generated traps on reliability in HfSiON/SiO2 stacks with fluorine incorporation","authors":"I. Hirano, T. Yamaguchi, Y. Nakasaki, K. Sekine, Y. Mitani","doi":"10.1109/RELPHY.2008.4558975","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558975","url":null,"abstract":"In this paper, we investigate the correlation between traps and the degradation of reliability in HfSiON/SiO2 stacks with F incorporation. It was found that the nature of generated traps corresponds to that of pre-existing traps. Namely new traps cannot be generated if there is no seeds traps which can be eliminate by F incorporation. The controlling pre-existing electron traps which work as seeds traps is effective for suppression of degradation. As TDDB and BTI lifetime strongly depends on trap characteristics, such as positions and their levels, the dominant traps concerning the degradations differ for each reliability characteristic, and also depending on stress polarities in FETs.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558882
N. Seifert, B. Gill, K. Foley, P. Relangi
Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.
{"title":"Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments","authors":"N. Seifert, B. Gill, K. Foley, P. Relangi","doi":"10.1109/RELPHY.2008.4558882","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558882","url":null,"abstract":"Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133207771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558872
Yuan Chen, M. Mojarradi, L. Westergard, N. Aranki, E. Kolawa, B. Blalock
A case study is presented applying a design-for-reliability methodology to design, fabricate and qualify a quad rail-to-rail operational amplifier for the wide temperature range operation of -140degC to +125degC to for space applications. The design-for-reliability approach was developed and implemented from transistor level up to board/system level, along with a comprehensive qualification procedure for the wide temperature range. The quad op-amp is used for a flight mission and available from a commercial production line.
{"title":"A case study: Design for reliability for a rail-to-rail operational amplifier for wide temperature range operation for Mars missions","authors":"Yuan Chen, M. Mojarradi, L. Westergard, N. Aranki, E. Kolawa, B. Blalock","doi":"10.1109/RELPHY.2008.4558872","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558872","url":null,"abstract":"A case study is presented applying a design-for-reliability methodology to design, fabricate and qualify a quad rail-to-rail operational amplifier for the wide temperature range operation of -140degC to +125degC to for space applications. The design-for-reliability approach was developed and implemented from transistor level up to board/system level, along with a comprehensive qualification procedure for the wide temperature range. The quad op-amp is used for a flight mission and available from a commercial production line.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131928100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558991
P. van der Wel, J. Stulemeijer, J. Bielen, F. Theunis, A. den Dekker, M. van Gils, R. Havens
RF MEMS capacitive switches can be used for band switching and adaptive antenna matching in cell phone Front End Modules. They are extremely linear and, if made in standard silicon technology, can be integrated into other applications in the phone. Many efforts have been put in the intrinsic reliability of the RF MEMS capacitive switches. The main failure mechanism is stiction due to dielectric charging. The progress made in RF MEMS processing has shifted the focus towards the package. It is generally accepted that a hermetic package is needed to keep the effect of charging within specification. Since packages are very small (typically 300nl), new hermeticity tests are needed because the leak rate tests are not sensitive enough for these small packages. In this paper we demonstrate the reliability of a capacitive RF MEMS switch package. The product is assembled using a AuSn bonding process in which a Silicon cap wafer is assembled on top of the MEMS die. The package is filled with pure N2 to the desired pressure. Hermeticity is determined by measuring the pressure dependence of the mechanical resonance of the MEMS top electrode. First we will describe the method we have used to determine the pressure inside the cavity and how to apply that to hermeticity testing. Second, we describe how the requirements for the leak rate of the package can be determined. Finally we show with the use of temperature, humidity and high pressure N2 testing that our package fulfills these requirements. Although the method may not be new, the combination of extensive reliability testing and understanding the RF MEMS device using FEM simulations has not been reported before.
{"title":"Hermeticity testing of capacitive RF MEMS switches","authors":"P. van der Wel, J. Stulemeijer, J. Bielen, F. Theunis, A. den Dekker, M. van Gils, R. Havens","doi":"10.1109/RELPHY.2008.4558991","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558991","url":null,"abstract":"RF MEMS capacitive switches can be used for band switching and adaptive antenna matching in cell phone Front End Modules. They are extremely linear and, if made in standard silicon technology, can be integrated into other applications in the phone. Many efforts have been put in the intrinsic reliability of the RF MEMS capacitive switches. The main failure mechanism is stiction due to dielectric charging. The progress made in RF MEMS processing has shifted the focus towards the package. It is generally accepted that a hermetic package is needed to keep the effect of charging within specification. Since packages are very small (typically 300nl), new hermeticity tests are needed because the leak rate tests are not sensitive enough for these small packages. In this paper we demonstrate the reliability of a capacitive RF MEMS switch package. The product is assembled using a AuSn bonding process in which a Silicon cap wafer is assembled on top of the MEMS die. The package is filled with pure N2 to the desired pressure. Hermeticity is determined by measuring the pressure dependence of the mechanical resonance of the MEMS top electrode. First we will describe the method we have used to determine the pressure inside the cavity and how to apply that to hermeticity testing. Second, we describe how the requirements for the leak rate of the package can be determined. Finally we show with the use of temperature, humidity and high pressure N2 testing that our package fulfills these requirements. Although the method may not be new, the combination of extensive reliability testing and understanding the RF MEMS device using FEM simulations has not been reported before.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133375511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-09DOI: 10.1109/RELPHY.2008.4558891
V. Martinez, C. Besset, F. Monsieur, D. Ney, L. Montès, G. Ghibaudo
In this study, conduction asymmetry is analyzed using asymmetric stacks in order to appreciate the cathode role. Then original test structures are used to highlight fringe leakage and to model asymmetry in a pure Ta2O5 capacitor for both surface and peripheral currents. Finally, the impact of peripheral on self-heating and consequently on reliability parameters is deeply investigated. Important information are then provided regarding intrinsic MIM characteristics, process optimization, reliability methodology and design rules.
{"title":"New insight into tantalum pentoxide Metal-Insulator-Metal (MIM) capacitors: Leakage current modeling, self-heating, reliability assessment and industrial applications","authors":"V. Martinez, C. Besset, F. Monsieur, D. Ney, L. Montès, G. Ghibaudo","doi":"10.1109/RELPHY.2008.4558891","DOIUrl":"https://doi.org/10.1109/RELPHY.2008.4558891","url":null,"abstract":"In this study, conduction asymmetry is analyzed using asymmetric stacks in order to appreciate the cathode role. Then original test structures are used to highlight fringe leakage and to model asymmetry in a pure Ta2O5 capacitor for both surface and peripheral currents. Finally, the impact of peripheral on self-heating and consequently on reliability parameters is deeply investigated. Important information are then provided regarding intrinsic MIM characteristics, process optimization, reliability methodology and design rules.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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